VLSI mcq

Basic MOS Transistors-1

Module 3

1. Electronics are characterized by ____________

a) low cost
b) low weight and volume
c) reliability
d) all of the mentioned
Answer: d

Explanation: Electronics are characterized by reliability, low power dissipation, extremely

low weight and volume, low cost, can cope up with high degree of sophistication and
complexity.

2. Speed power product is measured as the product of ____________

a) gate switching delay and gate power dissipation
b) gate switching delay and gate power absorption
c) gate switching delay and net gate power
d) gate power dissipation and absorption
Answer: a

Explanation: Speed power product is measure in picojoules and it is the product of gate
switching delay and gate power dissipation.

3. nMOS devices are formed in ____________

a) p-type substrate of high doping level
b) n-type substrate of low doping level
c) p-type substrate of moderate doping level
d) n-type substrate of high doping level
Answer: c

Explanation: nMOS devices are formed in a p-type substrate of moderate doping level.
nMOS devices have higher mobility and is cheaper.
4. Source and drain in nMOS device are isolated by ____________
a) a single diode
b) two diodes
c) three diodes
d) four diodes
Answer: b

Explanation: The source and drain regions are formed by diffusing n-type impurity, it gives
rise to depletion region which extend in more lightly doped p-region. Thus Source and
drain in an nMOS device are isolated by two diodes.

5. In depletion mode, source and drain are connected by ____________

a) insulating channel
b) conducting channel
c) Vdd
d) Vss
Answer: b

Explanation: In depletion mode, source and drain are connected by conducting channel
but the channel can be closed by applying suitable negative voltage to the gate.

6. What is the condition for non saturated region?

a) Vds = Vgs – Vt
b) Vgs lesser than Vt
c) Vds lesser than Vgs – Vt
d) Vds greater than Vgs – Vt
Answer: c

Explanation: The condition for non saturated region is Vds lesser Vgs – Vt. In non
saturation region, MOSFET acts as voltage source. Varying Vds will provide a significant
change in drain current.

7. In enhancement mode, device is in _________ condition.

a) conducting
b) non conducting
c) partially conducting
d) insulating
Answer: b
 Explanation: In enhancement mode, the device is in non conducting condition. For n-type
FET, the threshold voltage is positive and p-type threshold voltage is negative.

8. What is the condition for non conducting mode?

a) Vds lesser than Vgs
b) Vgs lesser than Vds
c) Vgs = Vds = 0
d) Vgs = Vds = Vs = 0
Answer: d

Explanation: In enhancement mode the device is in non conducting mode, and its
condition is Vds = Vgs = Vs = 0.

9. nMOS is ____________
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Answer: b

Explanation: nMOS transistors are acceptor doped. Acceptor is a dopant which when
added forms p-type region. Some of the accpetors are silicon, boron, aluminium etc.

10. MOS transistor structure is ____________

a) symmetrical
b) non symmetrical
c) semi symmetrical
d) pseudo symmetrical
Answer: a

Explanation: MOS transistor structure is completely symmetrical with respect to source

and drain.

11. pMOS is ____________

a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Answer: a
 Explanation: nMOS is acceptor doped and pMOS is donor doped devices. Acceptor
doped forms p-type region and donor doped forms n-type region.

12. Inversion layer in enhancement mode consists of excess of ____________

a) positive carriers
b) negative carriers
c) both in equal quantity
d) neutral carriers
Answer: b

Explanation: Inversion layer in enhancement mode consists of excess of negative carriers

that is electron.

13. What is the condition for linear region?

a) Vgs lesser than Vt
b) Vgs greater than Vt
c) Vds lesser than Vgs
d) Vds greater than Vgs
Answer: b

Explanation: The condition for linear region is Vgs > Vt. The power of MOS in the linear
region is less. It is a power dissipating region.

14. As source drain voltage increases, channel depth ____________

a) increases
b) decreases
c) logarithmically increases
d) exponentially increases
Answer: b

Explanation: As source drain voltage Vds increases, the channel depth at the drain end
decreases.

15. In which gates operation is independent of stored charge

a) Dynamic b) static c) Complementary d) all

16. Moor’s law relates to

a) speed of operation of bipolar devices b) speed of operation MOS devices

c) the power rating of MOS devices. d) level of integration of MOS devices

17. In the fabrication of an n-p-n transistor in an IC, the buried layer on the p-type substrate is

a) p+-doped b) n+-doped

c) Used to reduce the parasitic capacitance d) Located in the emitter region

Basic MOS Transistors-2

Module 3

1. MOS transistors consist of which of the following?

a) semiconductor layer
b) metal layer
c) layer of silicon-di-oxide
d) all of the mentioned
Answer: d

Explanation: MOS transistors is formed as a sandwich consisting of a semiconductor

layer, a silicon-di-oxide layer and a metal layer.

2. In MOS transistors _______________ is used for their gate.

a) metal
b) silicon-di-oxide
c) polysilicon
d) gallium
Answer: c

Explanation: In MOS transistors, polycrystalline silicon is used for their gate region
instead of metal. Polysilicon gates have replaced all other older devices.

3. The gate region consists of ____________

a) insulating layer
b) conducting layer
c) lower metal layer
d) p type layer
Answer: b
 Explanation: The gate region is a sandwich consisting of semiconductor layer, an
insulating layer and an upper metal layer.

4. Electrical charge flows from ____________

a) source to drain
b) drain to source
c) source to ground
d) source to gate
Answer: a

Explanation: Electrical charge or current flows from source to drain depending on the
charge applied to the gate region.

5. Source in MOS transistors is doped with ______ material.

a) n-type
b) p-type
c) n & p type
d) none of the mentioned
Answer: a

Explanation: Source and drain in the MOS transistors are doped with N-type material and
substrate is doped with p-type material.

6. In N channel MOSFET which is the more negative of the elements?

a) source
b) gate
c) drain
d) source and drain
Answer: a

Explanation: In N channel MOSFET, source is the more negative of the elements and in
the case of P channel MOSFET, it is the more positive of the elements.

7. If the gate is given sufficiently large charge, electrons will be attracted to ____________
a) drain region
b) channel region
c) switch region
d) bulk region
Answer: b
 Explanation: If the gate is given sufficiently large charge, the negative charge carreirs,
electrons will be attracted from the bulk of the substrate material into the channel region
below the oxide.

8. Enhancement mode device acts as ____ switch, depletion mode acts as _____ switch.
a) open, closed
b) closed, open
c) open, open
d) close, close
Answer: a

Explanation: Enhancement mode transistor acts as open switch whereas depletion mode
transistor acts as normally closed switch.

9. Depletion mode MOSFETs are more commonly used as ____________

a) switches
b) resistors
c) buffers
d) capacitors
Answer: b

Explanation: Depletion mode MOSFETs are more commonly used as resistors than as
switches. As permanently on switch it has high resistance.

10. Enhancement mode MOSFETs are more commonly used as ____________

a) switches
b) resistors
c) buffers
d) capacitors
Answer: a

Explanation: Enhancement mode MOSFETs are more commonly used as switches and
depletion mode devices are more used as resistors.

11. Depletion mode transistor should be large.

a) true
b) false
Answer: a
 Explanation: Depletion mode transistors should be made large that is long and thin to
create the large ‘on’ resistance.

12. Which expression is true?

a) charging time < discharging time
b) charging time > discharging time
c) charging time = discharging time
d) charging time and discharging time are not related
Answer: b

Explanation: When driving a capacitive output load, charging time will be long compared
to the discharging time.

13. Overheating in device occurs due to less number of resistors per unit area.
a) true
b) false
Answer: b

Explanation: When the number of resistors per unit area increases, the device may not
dissipate heat very well. This results in device overheating which leads to its failure.

14. In n channel MOSFET ______________ is constant.

a) channel length
b) channel width
c) channel depth
d) channel concentration
Answer: a

15. In VLSI n-MOS process, the thinox mask

a) patterns of the ion implantation within the thinox region

b) deposited polysilicon all over thinox region

c) patterns thickox regions to expose silicon where source, drain, or gate areas are required

d) grows thickox over thinox regions in gate areas

 VLSI Design
Module 3

1. VLSI technology uses ________ to form integrated circuit.

a) transistors
b) switches
c) diodes
d) buffers
Answer: a

Explanation: Very large scale integration is the process of creating an integrated circuit
with thousands of transistors into one single chip.

2. Medium scale integration has ____________

a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates
Answer: c

Explanation: Small scale integration has one or more logic gate. Further improved
technology is medium scale integration which consists of hundred logic gates. Large
scale integration has thousand logic gates.

3. The difficulty in achieving high doping concentration leads to ____________

a) error in concentration
b) error in variation
c) error in doping
d) distribution error
Answer: b

Explanation: As photolithography comes closer to the fundamental law of optics,

achieving high accuracy in doping concentration becomes difficult, which leads to error
due to variation.

4. _________ is used to deal with effect of variation.

a) chip level technique
b) logic level technique
c) switch level technique
d) system level technique
Answer: d

Explanation: Designers must simulate multiple fabrication process or use system level
technique for dealing with effects of variation.

5. As die size shrinks, the complexity of making the photomasks ____________

a) increases
b) decreases
c) remains the same
d) cannot be determined
Answer: a

Explanation: As the die size shrinks due to scaling, the number of die per wafer increases
and the complexity of making the photomasks increases rapidly.

6. ______ architecture is used to design VLSI.

a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit
Answer: c

Explanation: SoC that is system on a chip architecture is used to design the very high
level integrated circuit.

7. What is the design flow of VLSI system?

i. architecture design

ii. market requirement

iii. logic design

iv. HDL coding

a) ii-i-iii-iv
b) iv-i-iii-ii
c) iii-ii-i-iv
d) i-ii-iii-iv
Answer: a

Explanation: The order of the design flow of VLSI circuit is market requirement,
architecture design, logic design, HDL coding and then verification.

8. What is the design flow of VLSI system?

i. architecture design

ii. market requirement

iii. logic design

iv. HDL coding

a) ii-i-iii-iv b) iv-i-iii-ii c) iii-ii-i-iv d) i-ii-iii-iv

nMOS Fabrication
Module 3

1. nMOS fabrication process is carried out in ____________

a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals
Answer: a

Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with
high purity.

2. ______________ impurities are added to the wafer of the crystal.

a) n impurities
b) p impurities
c) siicon
d) crystal
Answer: b

Explanation: p impurities are introduced as the crystal is grown. This increases the hole
concentration in the device.
3. What kind of substrate is provided above the barrier to dopants?
a) insulating
b) conducting
c) silicon
d) semiconducting
Answer: a

Explanation: Above a layer of silicon dioxide which acts as a barrier, an insulating layer is
provided upon which other layers may be deposited and patterned.

4. The photoresist layer is exposed to ____________

a) Visible light
b) Ultraviolet light
c) Infra red light
d) LED
Answer: b

Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions
where diffusion is to take place.

5. In nMOS device, gate material could be ____________

a) silicon
b) polysilicon
c) boron
d) phosphorus
Answer: b

Explanation: In nMOS device, the gate material could be metal or polysilicon. This
polysilicon layer has heavily doped polysilicon deposited by CVD.

6. Which is the commonly used bulk substrate in nMOS fabrication?

a) silicon crystal
b) silicon-on-sapphire
c) phosphorus
d) silicon-di-oxide
Answer: c

Explanation: In nMOS fabrication, the bulk substrate used can be either bulk silicon or
silicon-on-sapphire.
7. In nMOS fabrication, etching is done using ____________
a) plasma
b) hydrochloric acid
c) sulphuric acid
d) sodium chloride
Answer: a

Explanation: In nMOS fabrication, etching is done using hydrofluoric acid or plasma.

Etching is a process used to remove layers from the surface.

8. Heavily doped polysilicon is deposited using ____________

a) chemical vapour decomposition
b) chemical vapour deposition
c) chemical deposition
d) dry deposition
Answer: b

Explanation: The polysilicon layer consists of heavily doped polysilicon deposited by

chemical vapour deposition.

9. In diffusion process ______ impurity is desired.

a) n type
b) p type
c) np type
d) none of the mentioned
Answer: a

Explanation: Diffusion is carried out by heating the wafer to high temperature and passing
a gas containing the desired ntype impurity.

10. Contact cuts are made in ____________

a) source
b) drain
c) metal layer
d) diffusion layer
Answer: a

Explanation: Contact cuts are made in the desired polysilicon area, source and gate.
COntact cuts are those places where connection has to be made.
11. Interconnection pattern is made on ____________
a) polysilicon layer
b) silicon-di-oxide layer
c) metal layer
d) diffusion layer
Answer: c

Explanation: The metal layer is masked and etched to form interconnection pattern. The
metal layer was formed using aluminium deposited over the formed surface.

12. _______ is used to suppress unwanted conduction.

a) phosphorus
b) boron
c) silicon
d) oxygen
Answer: b

Explanation: Boron is used to suppress the unwanted conduction between transistor

sites. It is implanted in the exposed regions.

13. Which is used for the interconnection?

a) boron
b) oxygen
c) aluminium
d) silicon
Answer: c

Explanation: Aluminium is the suitable material used for the circuit interconnection or
connecting two layers.

14. Physical and electrical specification is given in ____________

a) architectural design b) logic design c) system design d) functional design

CMOS Fabrication
Module 3
1. CMOS technology is used in developing which of the following?
a) microprocessors
b) microcontrollers
c) digital logic circuits
d) all of the mentioned
Answer: d

Explanation: CMOS technology is used in developing microcontrollers, microprocessors,

digital logic circuits and other integrated circuits.

2. CMOS has __________

a) high noise margin
b) high packing density
c) high power dissipation
d) high complexity
Answer: b

Explanation: Some of the properties of CMOS are that it has low power dissipation, high
packing density and low noise margin.

3. P-well is created on __________

a) p substrate
b) n substrate
c) p & n substrate
d) none of the mentioned
Answer: b

Explanation: P-well is created on n substrate to accommodate n-type devices whereas

p-type devices are formed in the ntype substrate.

4. Oxidation process is carried out using __________

a) hydrogen
b) low purity oxygen
c) sulphur
d) nitrogen
Answer: a

Explanation: Oxidation process is carried out using high purity oxygen and hydrogen.
Oxidation is a process of oxidizing or being oxidised.
5. Photoresist layer is formed using __________
a) high sensitive polymer
b) light sensitive polymer
c) polysilicon
d) silicon di oxide
Answer: b

Explanation: Light sensitive polymer is used to form the photoresist layer. Photoresist is a
light sensitive material used to form patterned coating on a surface.

6. In CMOS fabrication, the photoresist layer is exposed to __________

a) visible light
b) ultraviolet light
c) infra red light
d) fluorescent
Answer: b

Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions
where diffusion is to take place.

7. Few parts of photoresist layer is removed by using __________

a) acidic solution
b) neutral solution
c) pure water
d) diluted water
Answer: a

Explanation: Few parts of photoresist layer is removed by treating the wafer with basic or
acidic solution. Acidic solutions are those which have pH less than 7 and basic solutions
have greater than 7.

8. P-well doping concentration and depth will affect the __________

a) threshold voltage
b) Vss
c) Vdd
d) Vgs
Answer: a

Explanation: Diffusion should be carried out very carefully, as doping concentration and
depth will affect both threshold voltage and breakdown voltage.
9. Which type of CMOS circuits are good and better?
a) p well
b) n well
c) all of the mentioned
d) none of the mentioned
Answer: b

Explanation: N-well CMOS circuits are better than p-well CMOS circuits because of lower
substrate bias effect.

10. N-well is formed by __________

a) decomposition
b) diffusion
c) dispersion
d) filtering
Answer: b

Explanation: N-well is formed by using ion implantation or diffusion. Ion implantation is a

process by which ions of a material are accelerated in an electrical field and impacted
into a solid. Diffusion is a process in which net movement of ions or molecules plays a
major role.

11. In accordance to the scaling technology, the total delay of the logic circuit depends on
______

a) The capacitor to be charged b) The voltage through which capacitance must be

charged

c) Available current d) All of the above

nMOS and CMOS Fabrication

Module 3

1. What is Lithography?
a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip
Answer: a

Explanation: Lithography is the process used to develop a pattern to a layer on the chip.

2. Silicon oxide is patterned on a substrate using ____________

a) Physical lithography
b) Photolithography
c) Chemical lithography
d) Mechanical lithography
Answer: b

Explanation: Silicon oxide is patterned on a substrate using Photolithography.

3. Positive photo resists are used more than negative photo resists because ___________
a) Negative photo resists are more sensitive to light, but their photo lithographic resolution is
not as high as that of the positive photo resists
b) Positive photo resists are more sensitive to light, but their photo lithographic resolution is
not as high as that of the negative photo resists
c) Negative photo resists are less sensitive to light
d) Positive photo resists are less sensitive to light
Answer: a

Explanation: Negative photo resists are more sensitive to light, but their photo
lithographic resolution is not as high as that of the positive photo resists. Therefore,
negative photo resists are-used less commonly in the manufacturing of high-density
integrated circuits.

4. The ______ is used to reduce the resistivity of poly silicon.

a) Photo resist
b) Etching
c) Doping impurities
d) None of the mentioned
Answer: c

Explanation: The resistivity of poly silicon is reduced by Doping impurities.

5. The isolated active areas are created by technique known as ___________

a) Etched field-oxide isolation
b) Local Oxidation of Silicon
c) Etched field-oxide isolation or Local Oxidation of Silicon
d) None of the mentioned
Answer: c

Explanation: To create isolated active areas both the techniques can be used. Among
them Local Oxidation of Silicon(LOCOS) is most efficient.

6. In CMOS circuits, which type of power dissipation occurs due to switching of transient
current and charging & discharging of load capacitance?

a) Static dissipation b) Dynamic dissipation c) Both a and b d) None of

these

Ids versus Vds Relationship

Module 3

1. Ids depends on ___________

a) Vg
b) Vds
c) Vdd
d) Vss
Answer: b

Explanation: Ids depends on both Vgs and Vds. The charge induced is dependent on the
gate to source voltage Vgs also charge can be moved from source to drain under
influence of electric field created by Vds.

2. Ids can be given by __________

a) Qc x Ʈ
b) Qc / Ʈ
c) Ʈ / Qc
d) Qc / 2Ʈ
Answer: b

Explanation: Ids can be given as charge induced in the channel(Qc) divided by transit
time (Ʈ). Ids is equivalent to (-Isd).
3. Velocity can be given as __________
a) µ / Vds
b) µ / Eds
c) µ x Eds
d) Eds / µ
Answer: b

Explanation: Velocity can be given as the product of electron or hole mobility(µ) and
electric field(Eds). It gives the flow velocity which an electron attains due to electric field.

4. In resistive region __________

a) Vds greater than (Vgs – Vt)
b) Vds lesser than (Vgs – Vt)
c) Vgs greater than (Vds – Vt)
d) Vgs lesser than (Vds – Vt)
Answer: b

Explanation: In non saturated or resistive region, Vds lesser than Vgs – Vt where Vds is
the voltage between drain and source, Vgs is the gate-source voltage and Vt is the
threshold voltage.

5. What is the condition for saturation?

a) Vgs = Vds
b) Vds = Vgs – Vt
c) Vgs = Vds – Vt
d) Vds > Vgs – Vt
Answer: b

Explanation: The condition for saturation is Vds = Vgs – Vt since at this point IR drop in
the channel equals the effective gate to channel voltage at the drain.

6. Threshold voltage is negative for __________

a) nMOS depletion
b) nMOS enhancement
c) pMOS depletion
d) pMOS enhancement
Answer: a

Explanation: The threshold voltage for nMOS depletion denoted as Vtd is negative.
7. The current Ids _______ as Vds increases.
a) increases
b) decreases
c) remains fairly constant
d) exponentially increases
Answer: c

Explanation: The current Ids remains fairly constant as Vds increases in the saturation
region.

8. In linear region ______ channel exists.

a) uniform
b) non-uniform
c) wide
d) uniform and wide
Answer: a

Explanation: In linear region of MOSFET, the channel is uniform and narrow. This is the
concentration distribution.

9. When the channel pinches off?

a) Vgs > Vds
b) Vds > Vgs
c) Vds > (Vgs-Vth)
d) Vgs > (Vds-Vth)
Answer: c

Explanation: In MOSFET, in saturation region, when Vds > (Vgs – Vth), the channel
pinches off that is the channel current at the drain spreads out.

10. Output of DOMINO CMOS gate is low at beginning of following phase?

a) precharge b) evaluation c) dynamic d) static

nMOS Inverter
Module 3
1. Inverters are essential for ________
a) NAND gates
b) NOR gates
c) sequential circuits
d) all of the mentioned
Answer: d

Explanation: Inverters are needed for restoring logic levels for NAND and NOR gates,
sequential and memory circuits.

2.In basic inverter circuit _____________ is connected to ground.

a) source
b) gates
c) drain
d) resistance
Answer: a

Explanation: A basic inverter circuit consists of transistor with a source connected to

ground and a load resistor connected from drain to positive supply rail Vdd.

3. In inverter circuit ________ transistors is used as load

a) enhancement mode
b) depletion mode
c) all of the mentioned
d) none of the mentioned
Answer: b

Explanation: Depletion mode transistors are preferred to be used as load in inverter

circuits as it occupies a lesser area and are produced on silicon substrate unlike
resistors.

4. For depletion mode transistor, gate should be connected to ________

a) source
b) drain
c) ground
d) positive voltage rail
Answer: a

Explanation: For the depletion mode transistor, gate is connected to source so it is always
on and only the characteristic curve Vgs=0 is relevant.
5. In nMOS inverter configuration depletion mode device is called as ________
a) pull up
b) pull down
c) all of the mentioned
d) none of the mentioned
Answer: a

Explanation: In nMOS inverter configuration, depletion mode devices are called as pull up
and enhancement mode devices are called as pull down transistor.

6. Pass transistors are transistors used as ________

a) switches connected in series
b) switches connected in parallel
c) inverters used in series
d) inverter used in parallel
Answer: a

Explanation: Pass transistors are transistor used as switches in series with lines carrying
logic levels due to its isolated nature of the gate.

CMOS Inverter

Module 3

1. CMOS inverter has ______ regions of operation.

a) three
b) four
c) two
d) five
Answer: d

Explanation: CMOS inverter has five distinct regions of operation which can be
determined by plotting CMOS inverter current versus Vin.

2. If n-transistor conducts and has large voltage between source and drain, then it is said to
be in _____ region.
a) linear
b) saturation
c) non saturation
d) cut-off
Answer: b

Explanation: If n-transistor conducts and has large voltage between source and drain,
then it is in saturation.

3. If p-transistor is conducting and has small voltage between source and drain, then it is
said to work in ________
a) linear region
b) saturation region
c) non saturation resistive region
d) cut-off region
Answer: c

Explanation: If p-transistor is conducting and has small voltage between source and
drain, then it is said to be in unsaturated resistive region.

4.If βn = βp, then Vin is equal to ________

a) Vdd
b) Vss
c) 2Vdd
d) 0.5Vdd
Answer: d

Explanation: If βn = βp, then Vin = 0.5Vdd which implies that the changeover between
logic levels is symmetrically disposed about the point.

5. Mobility depends on ________

a) Transverse electric field
b) Vg
c) Vdd
d) Channel length
Answer: a

Explanation: Mobility is affected by the transverse electric field and thus also depends on
Vgs and the mobility of p-device and n-device are inherently unequal.

6. In CMOS inverter, transistor is a switch having ________

a) infinite on resistance
b) finite off resistance
c) buffer
d) infinite off resistance
Answer: b

Explanation: In CMOS inverter, transistor is a switch having finite on resistance and

infinite off resistance.

7. CMOS inverter has ______ output impedance.

a) low
b) high
c) very high
d) none of the mentioned
Answer: a

Explanation: CMOS inverter has low output impedance and this makes it less prone to
noise and disturbance.

8. What is the input resistance of CMOS inverter?

a) high
b) low
c) very low
d) none of the mentioned
Answer: a

Explanation: Input resistance of CMOS inverter is extremely high as it is a perfect

insulator and draws no dc input source.

Stick Diagram

Module 4

1. Stick diagrams are those which convey layer information through?

a) thickness
b) color
c) shapes
d) layers
Answer: b

Explanation: Stick diagrams are those which convey layer information through color
codes. Thickness is not considered in this stick diagram representation.

2. Which color is used for n-diffusion?

a) red
b) blue
c) green
d) yellow
Answer: c

Explanation: Green color is used to show the presence of n-diffusion layer. The n-type
diffusion will dope the source or drain region in the p-well region.

3. Which color is used for implant?

a) red
b) blue
c) green
d) yellow
Answer: d

Explanation: Yellow color is used to represent implant layer.

4. Which color is used for contact areas?

a) red
b) brown
c) black
d) blue
Answer: c

Explanation: Black color is used to represent contact areas. This is the part where two
different touch or cross each other.

5. Which color is used for polysilicon?

a) brown
b) red
c) white
d) orange
Answer: b

Explanation: Red is used to represent polysilicon layers. It is a semi-conductor like

material and is a hyper pure form of silicon.

6. n and p transistors are separated by using __________

a) differentiation line
b) separation line
c) demarcation line
d) black line
Answer: c

Explanation: Demarcation line separates n and p transistors. Demarcation line is similar

to dotted line in brown.

7. _______ layer should be over ______ layer.

a) ntype, polysilicon
b) polysilicon, ntype
c) ptype, ntype
d) ntype, ptype
Answer: b

Explanation: Polysilicon layer should be over n-type layer. This is the standard pattern
used in stick diagram representation.

8. Implant is represented using ___________

a) black, dark line
b) black, dotted line
c) yellow, dark line
d) yellow, dotted line
Answer: d

Explanation: Implant is represented using yellow color dotted lines. It is drawn in the
middle of the nMOS or pMOS wherever the implant is used.

Design Rules and Layout-1

Module 4
1. What should be the width of metal 1 and metal 2 layers?
a) 3λ, 3λ
b) 2λ, 3λ
c) 3λ, 4λ
d) 4λ, 3λ
Answer: c

Explanation: The width of the metal 1 layer should be 3λ and metal 2 should be 4λ.

2. Implant should extend _______ from all the channels.

a) 2λ
b) 3λ
c) 4λ
d) λ
Answer: a

Explanation: Implant for a n-mos depletion mode transistor should extend minimum of 2λ
from the channel in all the directions.

3. Which type of contact cuts are better?

a) buried contacts
b) butted contacts
c) butted & buried contacts
d) none of the mentioned
Answer: a

Explanation: Buried contacts are much better than butted contacts. In butted contacts the
two layers are joined together or binded together using adhesive type of material where
as in buried contact one layer is interconcted or fitted into another.

4. Which design method occupies or uses lesser area?

a) lambda rules
b) micron rules
c) layer rule
d) source rule
Answer: b

Explanation: Micron rules occupies or consumes lesser area. 50% of the area usage can
be reduced by using micron rules over lambda rules.
5. Which gives scalable design rules?
a) lambda rules
b) micron rules
c) layer rules
d) thickness rules
Answer: a

Explanation: Lambda rules gives scalable design rules and micron rules gives absolute
dimensions.

6. The width of n-diffusion and p-diffusion layer should be?

a) 3λ
b) 2λ
c) λ
d) 4λ
Answer: b

Explanation: The width of n-diffusion and p-diffusion should be 2λ according to design

rules.

7. What should be the spacing between two diffusion layers?

a) 4λ
b) λ
c) 3λ
d) 2λ
Answer: c

Explanation: The spacing between two diffusion layers should be 3λ according to design
rules and standards.

8. What are the advantages of design rules?

a) durable
b) scalable
c) portable
d) all of the mentioned
Answer: d
 Explanation: Some of the advantages of generalised design rules are those are durable,
scalable, portable, increases designer efficiency and automatic translation to final layout
can be done.

9. Minimum diffusion space is __________

a) 2λ
b) 3λ
c) 4λ
d) λ
Answer: b

Explanation: Minimum diffusion space is 3λ to avoid the possibility of their associated

regions overlapping and conducting current.

10. Contact cuts should be ____ apart.

a) 2λ
b) 3λ
c) 4λ
d) λ
Answer: a

Explanation: Two contact cuts should be 2λ apart to prevent holes from merging.

Noise margin

Module 3

1. Noise Margin is:

a) Amount of noise the logic circuit can withstand
b) Difference between VOH and VIH
c) Difference between VIL and VOL
d) All of the Mentioned
Answer: d

Explanation: Noise Margin is defined as the amount of noise the logic circuit can
withstand, it is given by the difference between VOH and VIH or VIL and VOL.
2. The VIL is found from transfer characteristic of inverter by:
a) The point where the straight line at VOH ends
b) The slope of the transition at a point at which the slope is equal to -1
c) The midpoint of the transition line
d) All of the mentioned
Answer: b

Explanation: The VIL is the input voltage at which the slope of the transition will be equal
to -1

3. The VIH is found from transfer characteristic of inverter by:

a) The point where straight line at VOH ends
b) The slope of the transition at a point at which the slope is equal to -1
c) The midpoint of the transition line
d) All of the mentioned
Answer: b

Explanation: The VIH is the input voltage at which the slope of the transition will be equal
to -1. In Transfer characteristics at 2 points we will find the slope to be -1.

4. The relation between threshold voltage and Noise Margin is:

a) Vth = sqrt(Noise Margin)
b) Vth = NMH – NML
c) Vth = (NMH+NML)/2
d) None of the metioned
View Answer

Answer: d

5. The Lower Noise Margin is given by:

a) VOL – VIL
b) VIL – VOL
c) VIL ~ VOL(Difference between VIL and VOL, depends on which one is greater)
d) All of the Mentioned
Answer: b
 Explanation: Noise margin = VIL-VOL.

6. The Higher Noise Margin is given by:

a) VOH – VIH
b) VIH – VOH
c) VIH ~ VOH(Difference between VIH and VOH, depends on which one is greater)
d) All of the mentioned
Answer: a

Explanation: Noise margin = VOH – VIH.

CMOS Logic Structures

Module 5

1. The BiCMOS are preferred over CMOS due to ______________

a) Switching speed is more compared to CMOS
b) Sensitivity is less with respect to the load capacitance
c) High current drive capability
d) All of the mentioned
Answer: d

Explanation: These are the 3 advantages of BiCMOS over CMOS.

2. The transistors used in BiCMOS are __________

a) BJT
b) MOSFET
c) Both BJT and MOSFETs
d) JFET
Answer: c

Explanation: BiCMOS is a combination of both MOSFET and BJT.

3. What is the standard form of CVSL?

a) CMOS Voltage Switch Logic
b)Common Voltage Switch Logic
c) Cascade Voltage Switch Logic
d) None of the above
Answer: c

4. In Pseudo-nMOS logic, n transistor operates in

a) cut off region
b) saturation region
c) resistive region
d) non saturation region
Answer: b

Explanation: In Pseudo-nMOS logic, n transistor operates in saturation region and p

transistor operates in resistive region.

5. In dynamic CMOS logic —---- is used

a) two phase clock
b) three phase clock
c) one phase clock
d) four phase clock
Answer: d

Explanation: In dynamic CMOS logic, four phase clock is used in which actual signals are
used to derive the clocks.

6.In clocked CMOS logic, output in evaluated in

a) on period
b) off period
c) both periods
d) half of on period
Answer: a
Explanation: In clocked CMOS logic, the logic is evaluated only in the on period of the
clock. And owing to the extra transistor in series, slower rise time and fall times are
expected.

7. In CMOS domino logic —----- is used

a) two phase clock
b) three phase clock
c) one phase clock
d) four phase clock
Answer: c

Explanation: In CMOS domino logic, single phase clock is used. Clock signals distributed
on one wire is called as single or one phase clock.

8.CMOS domino logic is same as with inverter at the output line

a) clocked CMOS logic
b) dynamic CMOS logic
c) gate logic
d) switch logic
Answer: b

Explanation: CMOS domino logic is same as that of the dynamic CMOS logic with
inverter at the output line.

9. CMOS domino logic occupies

a) smaller area
b) larger area
c) both of the mentioned
d) none of the mentioned
Answer: a

Explanation: CMOS domino logic structure occupies smaller area than conventional
CMOS logic as only n-block is used.

10. CMOS domino logic has

a) smaller parasitic capacitance
b) larger parasitic capacitance
c) low operating speed
d) very large parasitic capacitance
Answer: a

Explanation: CMOS domino logic has smaller parasitic capacitance and higher operating
speed.

Microcontroller:

Module 1

1.Which of the following should a microcontroller at-least should consist of?

a) CPU, ROM, I/O ports, and timers
b) RAM, ROM, I/O ports, and timers
c) CPU, RAM, I/O ports, and timers
d) CPU, RAM, ROM, I/O ports, and timers
Answer D

2. 8051 is ........................ bit Microcontroller

a. 4
b. 8
c. 16
d. 32
Answer B

3. 8051 has......................... pins

a. 50
b. 60
c. 40
d. 20
Answer C

4. 8051 MC has ......................... Computer Architecture

a) Harvard
b) Von neumann
c) Both
d) None
Answer A

5. In 8051 MC how many interrupts are there

a) 3
b) 5
c) 2
d) 4
Answer C

6. In One machine cycle how many states and ALE signals are there respectively
a) 12 and 4 b) 12 and 2 c) 6 and 2 d) 6 and 4
Answer B

7. Which locations of 128 bytes on-chip additional RAM are generally reserved
for special functions?
a) 60H to 0FFH b) 80H to 0FFH c) 70H to 0FFH d) 90H to 0FFH
Answer B

8. If we say microcontroller is 8-bit then here 8-bit denotes size of:

a) Data Bus
b) ALU
c) Control Bus
d) Address Bus
Answer: b

Explanation: If we say a microcontroller is 8-bit it means that it is capable of processing

8-bit data at a time. Data processing is the task of ALU and if ALU is able to process 8-bit
data then the data bus should be 8-bit wide. In most books it tells that size of data bus but
to be precise it is the size of ALU because in Harvard Architecture there are two sets of
data bus which can be of same size but it is not mandatory.

9. Abbreviate CISC and RISC.

a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
Answer: b
 Explanation: CISC means Complete Instruction Set Computer because in this a
microcontroller has an instruction set that supports many addressing modes for the
arithmetic and logical instructions, data transfer and memory accesses instructions. RISC
means Reduced Instruction Set Computer because here a microcontroller has an
instruction set that supports fewer addressing modes for the arithmetic and logical
instructions and for data transfer instructions.

10.Give the names of the buses present in a controller for transferring data from one place
to another?
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
Answer: c

Explanation: There are 3 buses present in a microcontroller they are data bus (for
carrying data from one place to another), address bus (for carrying the address to which
the data will flow) and the control bus (which tells the controller to execute which type of
work at that address may be it read or write operation).

11. Why microcontrollers are not called general purpose computers?

a) because they have built in RAM and ROM
b) because they design to perform dedicated task
c) because they are cheap
d) because they consume low power
Answer: b

Explanation: Microcontrollers are designed to perform dedicated tasks. While designing

general purpose computers end use is not known to designers.

12. Which architecture is followed by general purpose microprocessors?

a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: b

Explanation: General purpose microprocessors make use of Von Neumann architecture

as here a simpler design is offered.
13. Which architecture involves both the volatile and the non volatile memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a

Explanation: In Harvard architecture, both the volatile and the non volatile memories are
involved. This is done to increase its efficiency as both the memories are being used over
here.

14. Harvard architecture has _____________

a) dedicated buses for data and program memory
b) pipeline technique
c) complex architecture
d) all of the mentioned
Answer: d

. Explanation: Harvard Architecture has dedicated buses for data and program memory and
pipeline technique because of this architecture is complex.

15.8051 series has how many 16 bit registers?

a) 2
b) 3
c) 1
d) 0
Answer: a

Explanation: It has two 16 bit registers DPTR and PC.

16. When the microcontroller executes some arithmetic operations, then the flag bits of
which register are affected?
a) PSW
b) SP
c) DPTR
d) PC
Answer: a

Explanation: It stands for program status word. It consists of carry, auxiliary carry,
overflow, parity, register bank select bits etc which are affected during such operations.
 17.How are the status of the carry, auxiliary carry and parity flag affected if the write
instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Answer: b

Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so
CY and AC are set to 1. In the result, the number of 1’s present are even so parity flag is
set to zero.

18.If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned

Answer: a

Explanation: If we push elements onto the stack then the stack pointer increases with
every push of element.

19.What is the order decided by a processor or the CPU of a controller to execute an

instruction?
a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
Answer: d

Explanation: First instruction is fetched from Program Memory. After fetching, instruction
is decoded to generate control signals to perform the intended task. After decoding,
instruction is executed and the complete intended task of that particular instruction.

20. What is the most appropriate criterion for choosing the right microcontroller of our
choice?
a) speed
b) availability
c) ease with the product
d) all of the mentioned
Answer: d

Explanation: For choosing the right microcontroller for our product we must consider its
speed so that the instructions may be executed in the least possible time. It also depends
on the availability so that the particular product may be available in our neighboring
regions or market in our need. It also depends on the compatibility with the product so
that the best results may be obtained.

21. Why microcontrollers are not called general purpose computers?

a) because they have built in RAM and ROM
b) because they design to perform dedicated task
c) because they are cheap
d) because they consume low power
Answer: b

Explanation: Microcontrollers are designed to perform dedicated tasks. While designing

general purpose computers, end use is not known to designers.

22. Random access memory holds _____ bytes of storage in 8051.

a) 128 b) 124 c) 324 d) 126

23. When 8051 wakes up then 0x00 is loaded to which register?

a) PSW b) PC c) SP d) None of these

24. Which addressing mode is used in pushing or popping any element on or from the stack?

a) register b) immediate c) direct d) indirect

Module 2
22. which Registers will be used in Indirect addressing mode
a) R1 and R2 b) R2 and R3 c) R0 and R1 d) R0 and R2 01
Answer C

7. MOV R1,R2
a) Move the data from R1 to R2 b) Move the data from R2 to R1 c) Both a and b
d) None of the above
Answer B

23. What is the bit addressing range of addressable individual bits over the on-
chip RAM?
a) 00H to FFH b) 01H to 7FH c) 00H to 7FH d) 80H to FFH
Answer C

24. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Answer: b

Explanation: On power up register bank 0 is selected which has memory address from
00H-07H.

25. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Answer: c

Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.

26. When the call instruction is executed the topmost element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
 Answer: b

Explanation: The topmost element of the stack is the address of the instruction next to the
call instruction so that when RET is executed then PC is filled with that address and so
the pointer moves to the main program and continue with its routine task.

27.LCALL instruction takes

a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte

Answer: c

Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte

instruction.

28. What is the meaning of the instruction MOV A,05H?

a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
Answer: c

Explanation: If we need to store the address in the accumulator, then directly the address
is moved to it unlikely of using # used for storing data in any register.

29. To initialize any port as an output port what value is to be given to it?
a) 0xFF
b) 0x00
c) 0x01
d) A port is by default an output port
Answer: d

Explanation: In 8051, a port is initialized by default in its output mode no need to pass
any value to it.
30. Which addressing mode is used in pushing or popping any element on or from the
stack?
a) immediate
b) direct
c) indirect
d) register
Answer: b

Explanation: If we want to push or pop any element on or from the stack then direct
addressing mode has to be used in it, as the other way is not accepted.

31.DAA command adds 6 to the nibble if:

a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Answer: b

Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater
than 9.

32.A valid division instruction always makes:

a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Answer: c

Explanation: When we divide two numbers then AC and CY become zero.

33.Which instructions have no effect on the flags of PSW?

a) ANL
b) ORL
c) XRL
d) All of the mentioned
Answer: d

Explanation: These instructions are the arithmetic operations and the flags are affected
by the data copy instructions, so all these instructions don’t affect the bits of the flag.
34. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
Answer: c

Explanation: ANL instruction is used to AND the contents of the two registers and is also
used to mask the status of the bits of the register.

35. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
Answer: c

Explanation: SUBB command subtracts with borrow the contents of an accumulator with
that of the register or some immediate value. So A-R4 is being executed.

36.In unsigned number addition, the status of which bit is important?

a) OV
b) CY
c) AC
d) PSW
Answer: b

Explanation: If unsigned numbers operations are involved, then the status of CY flag is
important and in signed number operation the status of OV flag is important.

37. CJNE instruction makes _______

a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source
register
c) sets CY=0, if the contents of the destination register are smaller then that of the source
register
d) none of the mentioned
Answer: d
 Explanation: In CJNE command, the pointer jumps if the values of the two registers are
not equal and it resets CY if the destination address is larger then the source address
and sets CY if the destination address is smaller then the source address.

38.. XRL, ORL, ANL commands have _______

a) accumulator as the destination address and any register, memory or any immediate data
as the source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data
as the source address
d) any register as the destination address and any immediate data as the source address
Answer: a

Explanation: These commands have accumulator as the destination address and any
register, memory or any immediate data as the source address.

39.When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
Answer: c

Explanation: For addition purposes, the destination address must always be an

accumulator. Example- ADD A,R0; ADD A, @R1; ADD A,@ DPTR

40.JZ, JNZ, instructions checked content of _______ register.

a) DPTR
b) B
c) A
d) PSW
Answer: c

Explanation: JZ and JNZ instructions checked the content of A register and if condition
was satisfied or true then jump to target address.

41. What is the time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
Answer: b

Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal
frequency) /12

42. What is the meaning of the instruction MOV A,05H?

a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
Answer: c

Explanation: If we need to store the address in the accumulator, then directly the address
is moved to it unlikely of using # used for storing data in any register.

43. What is the advantage of register indirect addressing mode?

a) it makes use of registers R0 and R1 b) it uses the data dynamically

c) it makes use of operator @ d) it is easy

44. RD is _________ pin in 8051. a) 23 b) 24 c) 18 d) 17

Question Bank

MICROCONTROLLER

Module 1

1. With a neat block diagram explain the features of microcontroller 8051.

2. With a neat block diagram explain the architecture of 8051 microcontroller
3. With a neat diagram explain 8051 internal RAM organization.
4. Explain sequence of events of Call and Stack
5. With a generic waveform elucidate 8051 Oscillator Circuit.
6. With a neat diagram explain 8051 internal and external ROM organization.
7. Write the Pin diagram of 8051 MC and explain the significance of each pin.
8. Bring out the difference between Microprocessor and Microcontroller.
9. Explain the stack operation of 8051 microcontroller with necessary diagrams and
example.
10. Write a brief note on 8051 General Operational Features and General Physical
Features.
11. Write a brief note on 8051 input/output port functions.
12. What is a subroutine. Explain the call and return instructions with suitable examples.
13. Draw the structure of the program status word and explain the significance of each
field.
14. List the difference between von Neumann architecture and Harward architecture.
15. a.Find the elapse time of the machine cycle for: i. XTAL = 11.0592 MHz, ii. XTAL =
16 MHz, iii.XTAL = 20 MHz

12.b. State the contents of RAM locations after the following program:
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH
MOV R7, #63H
MOV R5, #12H

12.c. State the contents of RAM locations after the following program:
SETB PSW.4
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH
MOV R7, #63H
MOV R5, #12H

16. a.Show the stack and stack pointer for the following. Assume the default stack area.
MOV R6, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH 6
PUSH 1
PUSH 4

13.b. Examine the stack, show the contents of the registers and SP after execution
of the following instruction. All values are in hex.
POP 3 ;POP stack into R3
POP 5 ;POP stack into R5
POP 2 ;POP stack into R2

13.c. Show the stack and stack pointer for the following.
 MOV SP, #5FH
MOV R2, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH 2
PUSH 1
PUSH 4
14. Explain the Machine Cycle of 8051 microcontroller also Find the elapse time of
the machine cycle for:
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz
(c) XTAL = 20 MHz

Module 2

17. Explain the Different addressing modes in 8051 MC with an example for each.
18. Write an Assembly program to add two 16 bit number stored in R4R5 and R6R7.
Store the result in R0,R1,R2 (From MSB to LSB)
19. List the different types of branch instructions with examples.
20. List the different types of bit manipulation instructions with examples.
21. Comment on the different types of Arithmetic instruction used in 8051 microcontroller
with an example and Mnemonic.
22. Illustrate the different types of byte and bit logical operations used in 8051
microcontrollers with an example and Mnemonic.
23. Write a short note on rotate and swap instructions used in 8051 microcontrollers.
24. Illustrate the different types of data movement instructions used in 8051
microcontrollers with an example and Mnemonic.
25. Explain the different types of bit jumps which operate on the status of C flag with
examples.
26. Explain the different types of byte jumps that test the byte of data with examples.
27. Write a short note on unconditional jumps of 8051 microcontrollers.
28. Write an ALP to compare two eight bit numbers NUM1 and NUM2 stored in external
memory locations 8000h and 8001h respectively. Reflect your result as: If NUM1NUM2,
SET MSB of location 2FH (bit address 7FH). If NUM1 = NUM2, then Clear both LSB &
MSB of bit addressable memory location 2FH.
29. Write a Program to check whether a given number is palindrome or not. If palindrome
stores 0FFH else store 00 H.
30. Write a Program to generate arithmetic progression using 8051 microcontroller
instruction set.
31. Write a Program to find the 2 out of 5 code, display 0FFH for a valid 2 out of 5 code and
00h for not a valid 2 out of 5 code.
32. Write a Program to generate the first ten Fibonacci numbers using 8051 microcontroller
instruction set.
33. Write a Program for given below problem using 8051 microcontroller instruction set.
Treat r6-r7 and r4-r5 as two 16 bit registers. Perform subtraction between them. Store
the result in 20h (lower byte) and 21h (higher byte).
34. Write a Program to unpack packed number stored in 50H using 8051 microcontroller
instruction set.

CMOS VLSI

Module 3

35.Explain the operation and V-I characteristics of a MOS transistor for different
values of Vgs and Vds with necessary diagrams and find the current equation in
all three regions of operation.
36.Derive the minimum threshold voltage equation required between gate to
source to effectively conduct the MOSFET.
37.Obtain the DC Characteristics of a CMOS inverter and mark all the regions
showing the PMOS and NMOS status with necessary equations.
38.Compare CMOS and bipolar technologies.
39.With a neat diagram explicate the VLSI Design Flow.
40.Derive Drain to Source current in Cutoff, Linear and Saturation Region.
41.Explain the following i)Channel length modulation ii) Impact Ionization
iii)Mobility variation.
42.Explain the following i)Tunneling ii)Drain Punchthrough iii) Body effect.
43.Explain βn / βp ratio with respect to CMOS inverter.
44.Analyze the noise margin for CMOS inverter with neat diagrams and obtain the
values of low and high noise margin.
45.Demonstrate the steps involved in n-Well CMOS fabrication process with
masks used.
46.Demonstrate the steps involved in P-Well CMOS fabrication process with
masks used.
47.Discuss the working of the following i. Tristate inverter. ii. Pass
transistor. Iii. Differential inverter.
48.What do you mean by static load inverter?. Derive the output voltage for the
pseudo inverter with DC characteristics.
49.What is transmission gate? Explain with a neat structure how N- device is poor
transmission of logic 1 with good transmission of logic 0 and P- device is a
good transmission of logic 1 with poor transmission of logic 0.

Module 4

50.Discuss the Lambda based design rule with necessary diagram.

51.List the color, stick encoding, mask layout encoding and CIF layers for the
NMOS and CMOS monochrome encoding styles.
52. Draw the physical design of NAND gate and NOR gate,
53.Draw the schematic and Layout diagram using CMOS logic for i) 3
input NAND Gate ii) Y = ((A+B+C).D)’
54.Implement the following Boolean equations using CMOS Logic and Sketch the
layout diagram. i) Y ‘= A.(B+C) + D.E ii) Y’ = A.B+C.D
55.Draw the symbol, truth table, schematic and layout of NOR gate using NMOS
depletion style.
56.The Stick Diagram is an important concept which stands as an interface
between the symbolic circuit, Stick Diagram and Layout. Apply the concept of
Lamda based design rules for the given expression Y=A+BC. Implement using
logic, stick and layout diagram using CMOS design styles
57.Apply the concept of Lamda based design rules for the given expression
Y=(A+B+C)!. Implement using logic, stick and layout diagram using CMOS
design styles.
58.The Stick Diagram is an important concept which stands as an interface
between the symbolic circuit and Layout. Using the standard rule of Stick
Diagram, implement the given expression Y=(A+B)! along with the truth table
and logical circuit using NMOS design styles.
59.The Stick Diagram is an important concept which stands as an interface
between the symbolic circuit and Layout. Using the standard rule of Stick
Diagram implement the nMOS depletion inverter along with truth table and
logical circuit.
60. Draw the stick diagram for CMOS inverter and n-well based BiCMOS inverter
61. Using lambda-based design rules, draw the layout diagram for CMOS inverter and 2 input NMOS
NOR gate
62. Write the stick diagram for the following a) 4:1 nmos inverter b) Nmos shift register cell
 Module 5

63.Write a short note on complementary logic structure .

64.Explain the working of Bicmos logic for a NAND gate with NPN pull down
circuit and nmos pull down circuit.
65.Explain pseudo nMOS logic structure with an example and illustrate how
multidrain and Ganged CMOS circuits can be used to improve the static power
dissipation.
66.Explain a clocked cmos logic circuit with a suitable example.
67.Demonstrate the working of Dynamic CMOS logic structure with precharge
and evaluate states.
68.Interpret pass transistor logic structure for a 2 input XNOR gate.
69.Implement a 2 input NOR and 2 input NAND gate using pass transistor logic.
70.Explain the CMOS domino logic structure with its limitations and solution to
overcome the charge redistribution problem.
71.IImplement the following using dynamic Cascaded voltage switch logic
structure i. AND/NAND ii. 4 input XOR/XNOR

63. Implement the following using Cascaded voltage switch logic structure: i.
AND/NAND ii.OR/NOR iii. XOR/XNOR iv. Q=A(B+C)+DE