M

&C Morgan & cLaypool publishers

˛ˇ
Z
VDC
 S1
+ G1 D1
VDC
ES LS RS E1

C + O
IO
+
VDC G2
D2
S2 E
2

RS
LS ES

ES
 G1 E1

G2 E2

VDC
IO ES

S1 VOC CVDC
S2 !VDC

IO
 ˙VDC

ES RS IO

ˇ ˇ
ˇ d IO ˇ VDC
ˇ ˇ
ˇ dt ˇ " L :
S
 IO

TS S1 S2 tON1 tON2
LS =RS
TS

S1 tdead
VGE1 VGE 2 tdead
S2 S1

600 40 1µ

S1
S1
S2
 tdead
*
VGE1

Logic gate signals

TS t
*
VGE 2
tON1

TS t
tON2
VGE1
Applied gate signals

TS t
VGE2

TS t
VOC +VDC
Load voltage

TS t

-VDC

IO
S1

!VOC

tdead
!VOC D !2VDC .IO /;
TS
 *
c(t), m(t) VGE1(t)
cPK c(t)
m(t)
m(t)
+
VMO(t)
c(t) - *
TS t VGE2(t)
* COMPARATOR
VGE1(t)
DRIVER

t
*
VGE2(t)

dTS t
VOC(t) +VDC

t
-VDC

c.t / m.t/
 VOC
fS D 1=TS TS
c.t/ d
CVDC
TS

m.t /
m

m cPK m
D , dD :
d TS TS cPK

m.t/ 1=TS
m.t /

m.t/

m.t /

m.t/

m.t/
m.t/ VOC .t/
VOC .t /

VOC IO

RS LS
LS =RS TS
IO
m.t/
 VOC(t) VOC(t)

ES(t)
IO(t)

t
IO(t)

VOC .t/
IO .t/ INO .t /
V OC .t / ES

!
xP D Ax C Bu
;
y D C x C Du
x D ŒIO " u D ŒVOC ; ES "T y D ŒIO "

A D Œ!RS =LS " ; B D Œ1=LS ; !1=LS " ; C D Œ1"; D D Œ0; 0":

VOC IO ; GIO VOC

 1 1
GIO VOC .s/ D C .sI ! A/!1 B11 D :
RS LS
1Cs
RS
VOC
IO

VOC IO v

Z t CTs
1
N /D
v.t v.# / d #;
TS t

TS
TS

VOC

Z tCTs
1
V OC .t/ D VOC .# / d #
Ts t
1
D .TS VDC d.t / ! VDC .1 ! d.t // TS / D VDC .2d.t / ! 1/;
TS
d.t/
d V OC

@V OC
D 2VDC ;
@d
VDC

IQO .s/ 2VDC 1

G.s/ D D ;
Q
D.s/ RS LS
1Cs
RS

IQO .s/ Q
D.s/
IO d
 m.t /

m.t/
M Q
m m.t/ D M C m.t
Q /

n 16 8

Ne
 Clock Binary Counter Timer Interrupt

n bits

Binary Comparator Match Interrupt

n bits

Duty-Cycle

Gate signal

Timer interrupt request

t
Programmed duty-cycle

Timer count

TS t

Ne

Ne
2 " #3
fclock
6 10
fS 7
Ne D 6 7 C 1;
4 5
10 2

fclock fS D 1=TS
fclock

Ne n

m.t/

m.t/
ms .t/ c.t /
c.t/
 m(t) mS (t)
ZOH + VMO (t)
TS
c(t)

c(t), m(t) c(t), m(t)

cPK cPK
c(t) m(t) c(t) m(t)
ms(t) ms(t)

TS t TS t

VMO(t) VMO(t)

t t

c(t), m(t) c(t)

cPK
m(t)
ms(t)

TS t

VMO(t)

t
 m.t/
VMO .t/

VMO .s/ e !sDTS

.s/ D D ;
M.s/ cPK
VMO .s/ M.s/ VMO .t / m.t /

D
m.t /
ms .t / c.t /

VMO .s/ e !s.1!D/TS

.s/ D D
M.s/ cPK

VMO .s/ 1 $ !s.1!D/ TS TS %

.s/ D D e 2 C e !s.1CD/ 2 :
M.s/ 2cPK

D D0 D0 D 1 ! D
 Gate signal
t

Timer interrupt request

t
Programmed duty-cycle

Timer count

t
TS

Ne
fclock

VMO .s/ 1 $ !sD Ts Ts

%
.s/ D D e 2 C e !s.1!D/ 2 :
M.s/ 2cPK

. .j!// D !!TS =2 . .j!// D

!!TS =4
 c(t), m(t)
cPK
c(t) m(t)
ms(t) ms(t)
m(t)
ZOH + VMO(t)
TS/2 -
c(t)
TS t

VMO(t)

N
Tsampling D TS =N
m.t /

ms .t/
fsampling D N fS
Thold D Tsampling D TS =N

1
.s/ D e !std ;
cPK

floorŒN D"
td D DTS ! TS ;
N
floorŒN D" N D
 D TS
N

N
N

c(t), m(t)
cPK
m(t)
c(t)
ms(t)
m(t) ms(t)
ZOH + VMO(t)
TS/N
c(t) - t
Tsample
VMO(t)

t
 Rated output power, PO 1500 (W)
Phase inductance, LS 1.2 (mH)
Phase resistance, RS 1 (⌦)
Phase voltage, ES 120 (VRMS )
Load frequency, fO 60 (Hz)
DC link voltage, VDC 250 (V)
Switching frequency, fS 20 (kHz)
PWM carrier peak, cPK 4 (V)
C
Current transducer gain, GTI 0.1 (VA 1 )

PO ES RS

ES fO
GTI

KP KI
 PWM model G (s )

PI controller Static gain Delay effect (Pade Inverter gain Load admittance
approximation)

TS 1 1
IOREF 1− s . IO
K m 1 4 d
KP + I 2VDC RS L
+ s c PK T 1+ s S
- 1+ s S RS
4

GTI
Current transducer

KP KI

IOREF
 IO IO
15
16

10
14

5
12
[A] [A]
0
10

-5
8

-10
6

-15
4
20 25 30 35 40 45 37.6 37.8 38.0 38.2 38.4
t t
[ms] [ms]

IO T
16

14

12

[A]
10

1->
6

4
9.7 9.8 9.9 10 10.1 10.2 10.3
t Ch1: 2 A/div 100 µs/div
[ms] 12/12/14 17:22:43

IO
 " # TS
KI 2VDC 1 ! s 4 GTI 1
GOL .s/ D KP C :
s cPK T S RS LS
1Cs 1Cs
4 RS

fCL
fS 60ı phm
KP KI

! D !CL D 2$fCL

TS
2VDC 1 ! j!CL 4 GTI 1
GOL .j!CL / Š KP ;
cPK T S RS LS
1 C j!CL 1 C j!CL
4 RS
KI $ !CL KP
 s
" #
cPK RS LS 2
KP D 1 C !CL :
2VDC GTI RS

|GOL(!)|
40

20

[dB] 0

-20

-40

102 103 104 105 106

6 GOL(!)
-100

-120

[deg]
-140

-160

102 103 104 105 106

! [rad/s]

KI
phm
" # " # " #
ı ı !1 TS !1 LS !1 KP
! 180 C phm D !90 ! 2 !CL ! !CL C !CL ;
4 RS KI

!CL KP
KI D " " # " ## :
TS LS
!90ı C phm C 2 !1 !
CL C !1 !CL
4 RS
 KP
!1
!CL D 2$ fS =6 Š 20:94

KP D 2:012
!1
KI D 2:162 % 103 . /:

KI $ !CL KP

8̂ K !CL
" " # " ##
I
ˆ
ˆ D
ˆ
ˆ K TS LS
ˆ
ˆ
P
!90ı C phm C 2 !1 ! C !1 !CL
ˆ
ˆ
CL
4 RS
ˆ
ˆ
ˆ
<
v
u " # :
ˆ
ˆ u LS 2
ˆ
ˆ u 1 C !CL
ˆ
ˆ
ˆ cPK RS uu RS
ˆ
ˆ K D u " #
ˆ
ˆ
P
2VDC GTI t 1 KI 2
:̂ 1C
!CL KP
!1
KP D 2:01; KI D 2:159 % 103 . /
VDC ES
 +VDC

1
IOREF LS RS
-
+ +
0 IO
IO ES

-VDC

T T

1- > 1- >

Ch1: 2 A/div 100 µs/div Ch1: 2 A/div 100 µs/div

13/01/15 14:37:17 13/01/15 14:35:22

!10
C10 fS D 18

ES
 Ne

" FSR
#
10 SPP
Ne D n ! floor ;
10 2

SPP FSR
n
 +VDC
IO transduced

LS RS
Signal
Conditioning
IO +
ES

-VDC

n bits
Digital Control
PWM Algorithm

A/D Conversion
(Ideal sampler + Quantizer)
Microcontroller or DSP

Discrete time

fNyq
fsampling

n
 s(t) original signal spectrum replicas (due to sampling)
S(f)

...
t
fsampling 2fsampling f
original signal spectrum
reconstructed signal
sample aliasing error
a)

aliasing affected spectrum

S(f) replicas
S(f) original spectrum

fNyq fsampling 2fsampling nfsampling f

fsampling
Nyquist frequency =
2

eq
 y
100
1
011 0.8
0.6
010
0.4
001 1 LSB 0.2

000 0

0 1 2 3 4 x -0.2
-0.4
eq
-0.6
+1/2 LSB -0.8
-1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x
-1/2 LSB [s]
b)

eq
 Reconstructed
signals

Sampled signal
(load current)

Vdc Instantaneous
load voltage
-Vdc
t
TS
Not synchronized Synchronized

N x

8̂ ! " ! "
1 1
ˆ
ˆ N! q<x< N C q ) xq D N
< 2 2
ˆ
ˆ
:̂ q D FSR D LSB;
2n
n FSR
q

q
x
xq x
q xq

LSB2
!q2 D :
12
 ! "
12 2n
SNR D 10 10 2 D 6:02 n C 1:76 Π":
8

SNR SNR
d

x
d

d x

0.500 desired setpoint

"x <0
0.375

0.250

0.125
"x >0

001 010 011 100 dq t

TLCO

d
TLCO
d x
 LSB
qDPWM
x.t/ x.t /
 DPWM x
levels
Power converter
vin +1 LSB
error bin
x(t)
+qADC /2
io

ADC Max(Gdc · qDP W M , KI · qADC · Gdc )

0 0 bit
levels
A/D qADC xref error bin

Gate signal
qADC /2
x(k) 1 LSB
_
d(k) Digital x ref error bin
DPWM
regulator ε x (k) +
a) qPWM

x.t /

qADC G.s/
d x.t /

qDPWM Gdc < qADC ;

Gdc Gdc D jG.j 0/j > 1/

x.t /
KP qADC

KP qADC < qDPWM ;

KP
 x.t / KI qADC KI
KP
KI qADC < qDPWM

KI Gdc < 1;

KI

qADC
 IOS .k/
TS
 k k TS k
m.k/
m

IOREF IOS

G(s )

Inverter gain Load admittance

Digital PI controller

KP 1 . 1
IOREF (k) εI (k) + m(k) d(t) IO(t)
DPWM 2VDC RS LS
1 +s
+ − z . TS + RS
KI
z -1

ADC gain
Current transducer
I (k)
S
O 1
GTI
FSR

Microcontroller or DSP

m.k/
d.t/
m.k/
m
m.k/
 Digital PI Sample and Hold
ld
controller
IOREF IO IOREF IO
G (s ) KI
PI(z) DPWM KP + DPWM G (s )
+ + s
- -

1 1
GTI GTI
FSR FSR
ADC gain ADC gain
Current transducer Current transducer
 cPK D 1
! "
1 # !s.1!D/ TS TS $ TS TS TS
DPWM.s/ D e 2 C e !s.1CD/ 2 D e !s 2 ! D Š e !s 2 ;
2 2

1=TS
D

TS
T
1!s
e !s 2S
Š 4 ;
TS
1Cs
4

TS

FSR D cPK
 DPWM model G (s )

PI controller Static gain Delay effect (Padé Inverter gain Load admittance
approximation)

Ts 1 1
IOREF 1– s . IO
K m 4 d
KP + I 1 2VDC RS LS
+ s Ts 1+ s
- 1+ s RS
4

1
GTI
FSR
ADC gain Current transducer
 Z

s
Z z

Backward
Euler

Forward
Euler

(k-1)TS kTS (k+1)TS t (k-1)TS kTS (k+1)TS t

s
z

METHOD Z-FORM 3% DISTORTION LIMIT

Backward Euler s= z-1 fs
zTs f > 20
Forward Euler s = z T- 1 fs
> 20
s f
Trapezoidal (Tustin) s = T2 z-1
z+1
fs
> 10
s f
 !1
KP D 2:01 KI D 2:16 # 103 . /

KP
1Cs
KI
PI.s/ D KI :
s

z ! 1 KP
1C
z TS KI .KP C KI TS / z ! KP z
PI.z/ D KI D D KP C KI TS :
z!1 z!1 z!1
z TS

KP mP(k)
+ m(k) m(k-1)
εI(k)
z-1
+ mI(k) +
KITS
+
calculation delay
z-1

Z
 (
mI .k/ D KI TS "I .k/ C mI .k ! 1/
m.k/ D mP .k/ C mI .k/ D KP "I .k/ C mI .k/;

"I .k/ kTS

8
< m .k/ D K T "I .k/ C "I .k ! 1/ C m .k ! 1/
I I S I
2
:
m.k/ D mP .k/ C mI .k/ D KP "I .k/ C mI .k/:

(
KI dig D KI TS
KP dig D KP ;
 60

50

Magnitude [dB]
40

30

20

10

0
0
Phase [deg]

-45

-90
1 2 3 4 5
10 10 10 10 10

Frequency [rad/s]

z !1

.3=2/TS

f
fS D 1=TS
f
33

m
 IO IO
15
16

10
14

5
12
[A] [A]
0
10

-5
8

-10
6

-15
4
20 25 30 35 40 45 37.6 37.8 38.0 38.2 38.4
t t
[ms] [ms]

IO T
16

14

12

[A]
10

1- >
6

4
9.7 9.8 9.9 10 10.1 10.2 10.3
t Ch1: 2 A/div 100 µs/div
[ms] 30/01/15 16:15:02

IO
 IO IO
15 15

10 10

[A] [A]
5 5

0 0

-5 -5

38.0 38.5 39.0 39.5 40.0 40.5 38.0 38.5 39.0 39.5 40.0 40.5
t t
[ms] [ms]

TS

fS =15
 Z

PWM.s/ G.s/
x s .t/

Td .z/
 Td
z !1

h Modulatorr
Pulse Width Converter
Digitall Computation transfer
controller
l r delay function
s s
x REF (t) s
ε x(t)
s
m r(t) m (t) s
Reg(z) e
-sTd
ZOH + x(t) x (t)
+ - G(s)
-
c(t)

msr(k) xs(k)
e-sTTd PWM(s) G(s)

GT(z)

msr(k) xs(k)
z-1 ZOH G(s)

GT(z)
 30 30

IO IO
IOREF IOREF
20 20
[A] [A]

10 10

"I "I
0 0

7 8 9 10 11 12 13 14 t 7 8 9 10 11 12 13 14 t
[ms] [ms]
 Anti-wind-up

mMAX
mP(k)
KP
+ m(k)
εI(k)
LI(k)
+ +
KITS
+ mI(k)

z-1

mMAX

jLI .k/j D mMAX ! jKP "I .k/j :

1=TS

TS
PWM.s/ GT .z/

% &
GT .z/ D Z e !sTd Ts PWM.s/ G.s/ :
Z
 z !1
TS PWM.s/

GT .z/ D z !1 Z ŒH.s/ G.s/";

1 ! e !sTS
H.s/ D
s
G.s/
RS D 0
2 VDC
G.s/ D
s LS
Td D TS

' (
1 ! e !sTS 2 VDC
GT .z/ D z !1 Z
s s LS
' (
2 VDC !1 1 2 VDC TS 1
D z .1 ! z !1 /Z 2 D
LS s LS z.z ! 1/

' (
!sTS 2 VDC
GT .z/ D Z e TS PWM .s/
s LS
' (
2 VDC TS !1 PWM.s/ 2 VDC TS 1
D z Z D ;
LS s LS z.z ! 1/
PWM.s/ cPK D 1

' (
!sTd TS
GT .z/ D Z e PWM.s/ G.s/ ;
N
Z TS =N

Td
TC
Td << TS TS
x.t / IO .t /

Td
TS
Z Td
Td TS Z
Z

Td
p D1! ;
TS
 PWM carrier
c(t)
driver signal
toff ton toff

PWM PWM
update x(t) update
sampling

TC Td

x.t /

0$p$1 g.t/ G.s/

% & Z
g.t / Z L!1 ŒG.s/" .k TS / Z ŒG.s/"
L!1

2 3
6 X
1
!s p TS 7
Z 4H.s/ G.s/ e 5D z !k g1 .kTS ! Td / D Zm ŒG1 .s/" D G1 .z; p/;
„ ƒ‚ …
kD0
G1 .s/

g1 .t/ G1 .s/ G1 .z; p/ Zm ŒG1 .s/" Z

G1 .s/ H.s/ D .1 ! e !sTS /=s

2 3
' ( ' (
6 1 ! e !sTS 7 z!1 G.s/ !s p TS z!1 G.s/
6
GT .z; p/ D Z 4 !s p TS 7
s …
G.s/e 5D z Z s
e D
z
Zm
s
:
„ ƒ‚
H.s/

Z Z
Z
Z
M.z/ IO .z/

IO .z/ 2 VDC TS z p ! .p ! 1/
D :
M.z/ LS z.z ! 1/

pD0

IO .z/ 2 VDC TS 1
D ;
M.z/ LS z.z ! 1/

p>0

C50ı
ı
!130
BW i

pD0 p D 0:5

BW i pa

p 0 0.5 0.8
BWi fs /13.4 fs / 9 fs / 6.2
a
Phase margin is 50 º and the current
regulator is purely proportional.
 V OC
INO
k TS
 V OC
.k C 1/ TS .k C 2/ TS
.k C 2/ TS

IOREF
IO
IO

+VDC VOC

VOC
LS RS

+ +
IO -VDC
VOC ES
kTS Tlimit (k+1)TS (k+2)TS t

TS

.k C 1/TS

TS % &
INO .k C 1/ D INO .k/ C V OC .k/ ! ES .k/ ;
LS

RS

V OC .k/
k TS

V OC .k/
INO .k C 1/ IOREF .k/
V OC .k/
 Tlimit
Tlimit k TS

V OC .k/
V OC .k C 1/

TS % &
INO .k C 2/ D INO .k C 1/ C V OC .k C 1/ ! ES .k C 1/
LS
TS % &
D INO .k/ C V OC .k C 1/ C V OC .k/ ! ES .k C 1/ ! ES .k/ ;
LS

INO .k C 1/ ES

ES .k C 1/ Š ES .k/

LS % N &
V OC .k C 1/ D !V OC .k/ C IO .k C 2/ ! INO .k/ C 2 ES .k/ ;
TS

INO .k C 2/ IOREF .k/

.k C 1/ TS
.k C 2/ TS

ES
 LS 1 % S &
m .k C 1/ D ! m .k/ C IOREF .k/ ! IOS .k/
TS 2 GTI VDC
1
C2 E S .k/ ;
2 GTE VDC S

m.k/

ES

TS % &
INO .k/ ! INO .k ! 1/ D V OC .k ! 1/ ! ES .k ! 1/ ;
LS
 IO IO
15
16

10
14

5
12
[A] [A]
0
10

-5
8

-10
6

-15
4
20 25 30 35 40 45 37.6 37.8 38.0 38.2 38.4
t t
[ms] [ms]

IO T
16

12

[A]
8

1- >
4

9.7 9.8 9.9 10 10.1 10.2 10.3

t Ch1: 2 A/div 100 µs/div
[ms] 03/02/15 14:42:24

IO

ES .k ! 1/

LS % N &
EO S .k ! 1/ D V OC .k ! 1/ ! IO .k/ ! INO .k ! 1/ :
TS
 RS

(
xP D Ax C Bu
y D C x C Du;

x D ŒINO " u D ŒV OC ; EN S "T

y D ŒINO "

A D Œ!RS =LS "; B D Œ1=LS ; !1=LS "; C D Œ1"; D D Œ0; 0":

(
x.k C 1/ D ˚x.k/ C # u.k/
y.k/ D C x.k/ C Du.k/;
˚ D eA TS
# D .˚ ! I / A!1 B ˚ #

! LS
R
TS RS !0
˚ D eA TS
De S !! 1
2 3
R
! LS TS
R
! LS TS ' (
e !1 e ! 15 RS !0 TS TS
# D 4!
S S
!! ! ;
RS RS LS LS
 RS

RS

8
< IN .k C 1/ D IN .k/ C TS V .k/ ! TS E .k/
O O OC S
˙ W LS LS
:
y.k/ D INO .k/:

ES

ES V OC

V OC .k C 1/ D K2 V OC .k/ C K1 ŒIOREF .k/ ! INO .k/";

INO D y ˙
˙A

8̂ TS TS
ˆ
ˆ INO .k C 1/ D INO .k/ C V OC .k/ ! E S .k/
ˆ
ˆ L L
< S S

˙A W V OC .k C 1/ D K2 V OC .k/ C K1 ŒIOREF .k/ ! IN.k/" C K3 E S .k/

ˆ
ˆ ' (
ˆ
ˆ INO .k/
:̂ y.k/ D Œ1 0" ;
V OC .k/
 xA D ŒINO V OC "T
T
uA D ŒE S IOREF "
K3

ES

VOC - TS + I O (k ) y = IO
z–1 1
+ + LS +

1
Σ
ideal disturbance approximated
ES compensation disturbance ES
compensation

K3

VOC (k ) + + - IOREF
z–1 K1
+

K2
controller with
ΣA calculation delay

2 3 2 3
TS TS
1 ! j 0 5
˚A D 4 LS 5 ; #A D Œ#A1 j #A2 " D 4 LS ;
!K1 K2 K3 j K1
CA D Œ1 0"; DA D Œ0 0":

K1 ; K 2 K3

LS
K1 D ; K2 D !1
TS
˙A
 IOREF
INO

INO 1
.z/ D CA .zI ! ˚A /!1 #A2 D ;
IOREF z2

INO 1 TS
.z/ D CA .zI ! ˚A /!1 #A1 D 2 .!z ! 1 C K3 /:
ES z LS
K3

K3 D 2
K3 D 2

TS
INO .k/ D Œ!ES .k ! 1/ C ES .k ! 2/";
LS
ES
K1 ; K 2 K3

LS
V OC .k C 1/ D !V OC .k/ C ŒIOREF .k/ ! INO .k/" C 2 E S .k/:
TS
 ES
ES

INO
EO S
EO S

LS
LS

LS ˙ $LS % N &
V OC .k C 1/ D !V OC .k/ C IO .k C 2/ ! INO .k/ C 2 ES .k/ ;
TS

LS LS ˙ $LS
$LS
$LS

" TS
#
0 1 LS
˚A D :
! LS ˙!L
TS
S
!1
 0
˚A

s s
$LS $LS
%1;2 D ˙ ) j%1;2 j D :
LS LS

LS
LS LS

$LS

15
IsO
LS = 0

10
LS = 95%
IOREF
[A]

5
LS = 50%

37 38 39 40 t
[ms]

LS IO
 Z

$LS $LS
% .z/ D z 3 ˙ 3 z˙2 :
LS LS

$LS

$LS

Im(z)
1

(b)
(c)

(b) (a)
(c)
1 Re(z)

(c)
(b)

-1

LS
$LS D 0 $LS D 0:2 LS $LS D 0:3 LS
ES INO

INO 1 TS
.z/ D .z C 1/ ;
ES z 2 LS
 15
IO, IOREF IOREF

10

IO
5

[A]
0

-5

-10

-15
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016

[s] t
. Sample=s/
 12

Component Model Parameter Value

Slices 6822
DSP48s 58
FPGA Spartan-6 LX45 Max. clock frequency 200 MHz
Arithmetic resolution 16 bit
Max. sampling rate 65 MSample / s
Full scale range 3V
ADC AD9226
Resolution 12 bit
Latency @ 30MHz 0.286 µs

16
 Clock
current sense FPGA
amplif ier nbit bits
IO PI
GT I ADC Current
Control

÷Q switch
ADC clock DP W M clock drivers
f requency divider
galvanic isolation

2M

fDP W M
M D :
2 fS

Q Q
M M=Q D P; P 2 N
N
M
N D2 :
Q
M

TS =2
VM O

t
M Tsample
m

TDP W M
0
0 t
TS 2 TS
2 M TDP W M

cpk M

33 0:067
3:3

fCL fS =6 60ı

WIPI
 Parameter Symbol Value
Clock frequency fclock 30 MHz
DPWM resolution M 750
Oversampling rate N 50
ADC resolution nbit 12 bit
Current sensor gain GT I 100 mV/A
Current sensor FSR IM AX ±30 A

IO .s/ P W M.s/ G.s/ P I.s/

WIPI .s/ D D ;
IOREF .s/ 1 C P W M.s/ G.s/ P I.s/

1 ! TS
P W M.s/ D e 2N I
M

GT I 1 2 VDC
G.s/ D I
F SR RS 1 C s LS
RS

KI
PI.s/ D KP C :
s
 qADC

2 VDC 2nbi t VDC

fDP W M ! D ;
LS qADC LS jIMAX j

IMAX Π! nbi t
5

10 3:5

ES
 1

M agnitude [dB]
0

Experimental
Analytic Model
-4
0

-10
P hase [deg]

-20

-30
Experimental
-40 Analytic Model

-50
1 2 3
10 10 10
F requency [Hz]

current sense Clock

amplif ier FPGA
IO
nbit bits
GT I Predictive
ADC Current
ES Control
GT E ÷Q
switch
ADC clock DP W M clock drivers
voltage sense f requency divider
amplif ier
galvanic isolation
 "I
‚ …„ ƒ
S
L S fS IOREF .k/ " IOS .k/ ESS .k/ 1
m.k/ D C C :
VDC GT I 2 VDC GTE 2
„ ƒ‚ …
k"

kt h
k th

2
 IO
IO

t
VM O

t
M Tsample
"I

TDP W M Q=3
0
k 1 k k+1 t
TS 2 TS
2 M TDP W M

N !2

"I

1=M

qADC
 1 2 VDC 2nbi t
# qADC , fDP W M ! ;
M k" LS jIMAX j
IMAX
28:44
fclock D 30

Parameter Symbol Value

Clock frequency fclock 30 MHz
DPWM resolution M 750
Oversampling rate N 50
ADC resolution nbit 12 bit
Current sensor gain GT I 100 mV/A
Voltage sensor gain GT E 15 mV/V
Current sensor FSR IM AX ±30 A

2M D N Q N; M; Q 2 N; M ! N
 IO .z/ G.z/H.z/
WIDB .z/ D D D z !1 ;
IOREF .z/ 1 C G.z/H.z/

VDC z !1
G.z/ D I
LS fS 1 " z !1

LS fS
H.z/ D :
VDC

RS D 0
TS =2

sTS
WIDB .s/ D e ! 2 ;
 1
M agnitude [dB]

Experimental
Analytic Model
-4
0

-10
P hase [deg]

-20

-30
Experimental
-40 Analytic Model

-50
1 2 3
10 10 10
F requency [Hz]

3
ı ı
49 28
 Tclock N N
TS" N

RS TS D 1=fS

d "I .t/ 1 d IOREF .t /

D .VOC .t / " ES .t // " ;
dt LS dt
 Clock
IOREF dif f erential
FPGA
amplif ier nbit bits
Virtual
"I
IO
A
+ i
ADC Hysteresis
Current
Controller

ADC clock switch

drivers
galvanic isolation

Frequency
Divider

CountRU
Run-up Clock
Counter
FPGA
clock

Run-down CountRD
Counter Positive
Threshold
Update

nbit Zero Negative

+

"I Crossing Threshold

Current Detector Update
error
sample

+
S1
Threshold Driver
with
Crossing dead-time
Detector TD S2

ClockAD
Timer and ADC clock

t 2 Œ0; TS ! IOREF ES

ˇ
˙VDC " ES .0/ d IOREF .t/ ˇˇ
s ˙ .t/ Š s ˙ .0/ D " ˇ ;
LS dt t D0
 t D0

d IOREF .t /
ES .t/ C LS
h.t / D dt ;
VDC

VDC
s ˙ Š s ˙ .0/ D .˙1 " h.0// :
LS

ˇ"

TS"
VDC TS" ! "
ˇ" D 1 " h2 .0/ :
4 LS

ˇ"

kt h
t0 D .k " 2/TS" =2
 ✏iL t0 + t1 t2
(k 2)
+ +
(k) ⇤
+
THP (k) s

"I s+

t
+
THP (k 1)
(k 1)
⇤
(k + 1)
Terr (k 1))
Ts⇤
CountRU (k 2)
N= Tclock
CountRD
CountRU

CountRD (k 1)

CountRU (k 1) synch pulses

Ts⇤ Ts⇤ Ts⇤ Ts⇤ Ts⇤
(k 2) · 2 (k 1) · 2 k· 2 (k + 1) · 2 (k + 2) · 2 t

Tclock D TS" =N N

TS" =2

N TS"

t1
 Ts" " 2 Terr .k " 1/ "
ˇ ! .k " 1/ D " ˇ ;
Ts"

Terr .k " 1/

Terr
Tclock D TS" =N

TS"
TS" =2

Terr .k " 1/ TS"

D C ountRD .k " 1/ " ;
Tclock 2 Tclock
C ountRD .k " 1/ .k " 1/th
ˇ"
ˇ "
TS" =2

ˇ ˇ TS"
ˇ " D ˇˇ C .k " 2/ˇ C
;
2 THP .k " 1/
C
THP .k " 1/

C
THP .k " 1/

C
THP .k " 1/
D C ountRU .k " 1/ " C ountRU .k " 2/;
Tclock
C ountRU . /
C
THP .k " 1/
TS!
!
" Terr .k " 1/
ˇ .k " 1/ D " 2
C
ˇ C .k " 2/:
THP .k " 1/

t2 D kTS" =2
 ˇ C .k/
!
Terr .k/ Š 0 THP .k/

TS"
VDC LS

ˇC ˇ!
 "ˇ ˙ . /

TS!
! 2
" Terr .k " 1/
ˇ .k " 1/ D " C
THP .k " 1/
# C $
ˇ .k " 2/ C "ˇ .k " 2/ " "ˇ ! .k " 3/:
C

TS" "ˇ ! .k " 1/ Š

!
"ˇ .k " 3/
 ∆β + (k + 1)
+
∆β (k − 2)
"iL β + (k − 2)
β+ +β ∗
β−
β + (k)
εI

t
β − (k + 1)
β − (k − 1)
(a)
−β ∗
k-2 k-1 k k+1 k+2
iteration
"iL number
Terr (k)

t
β (k + 1)
−

β (k − 1)
−

(b)

TD ∆β − (k − 1)

"ˇ "

ˇ C . / D "ˇ ! . /
 Tclock

˙
THP

TS" ˇ˙. /

2 Tclock " 2
"ˇLCO D ˙ " ˇ D˙ ˇ";
TS N

Tclock ˇ"

˙2=N

Tclock

1 VDC 2nbi t C1
fclock D D ;
Tclock Ls IMAX
 S1
S2
Tlat

TD

% &
TD Tlat
M D 1"4 " ; 1"4 " ;
TS TS

Tlat 550 0:956

60 10
1
N
 NHyst D 100

fS" D 20 ˙2

Parameter Symbol Value

Clock frequency fclock 2 MHz
Target switching frequency fs∗ 20 kHz
Oversampling rate NHyst 100
AD converter latency ∆tAD 0.2 µs
Current sensor gain GT I 100 mV/A
Circuit latency (worst case) Tlat 550 ns

"3ı 3:0
 1

M agnitude [dB]
0

Experimental
Simulation Model
-4
0

-10
P hase [deg]

-20

-30
Experimental
-40 Simulation Model
-50
1 2 3
10 10 10
F requency [Hz]

0 10 10 0
ı
˙180
ES
0:8

ES D 140 0:8
 T T

1- > 1- >

Ch1: 2 A/div 100 µs/div Ch1: 2 A/div 100 µs/div

08/10/14 11:08:23 08/10/14 11:11:47

1- >

Ch1: 2 A/div 2 ms/div

08/10/14 11:24:38

C10 "10
180ı
 T T

1- > 1- >

Ch1: 2 A/div 100 µs/div Ch1: 2 A/div 100 µs/div

09/10/14 14:23:51 09/10/14 14:25:13

1- >

Ch1: 2 A/div 2ms/div

09/10/14 14:30:04

C10 "10
180ı

50
 T T

1- > 1- >

Ch1: 2 A/div 100 µs/div Ch1: 2 A/div 100 µs/div

13/10/14 10:05:24 13/10/14 10:09:49

1- >

Ch1: 2 A/div 2 ms/div

13/10/14 10:21:50

C10 "10
180ı

2
1 ES
10
ES
40

ES Š 2:5
 PI Predective Hysteretic
Phase shift @ 0.5 kHz −8 ◦
−5 ◦
−0◦
Phase shift @ 1.0 kHz −18◦ −10◦ −1◦
Phase shift @ 2.0 kHz −37◦ −19◦ −2◦
Phase shift @ 3.0 kHz −49◦ −28◦ −3◦
THD of 50Hz sinusoid 1.52% 0.82% 1.47%

ES

5 50

0:55 µ 11
20
7
 ˛ˇ

˛ˇ
˛ˇ

˛ˇ
 ! "T
xEabc D xa xb xc
T˛ˇ!
2 3
2 3 2 3 r 1 !1=2 !1=2 2 3
x˛ xa
26 p . p . 7 xa
4 xˇ 5 D 4 xb 5 D 6 0 3 2 ! 3 2 7 4 xb 5
3 4 .p .p .p 5
˛ˇ!
x! xc 1 2 1 2 1 2 xc

abc
˛ˇ!
R3 Babc
n! "T ! "T ! "T o
Babc D 1 0 0 ; 0 1 0 ; 0 0 1 ;

B˛ˇ!
p n ! "T
B˛ˇ! D 2=3 1 !1=2 !1=2 ;
h p . p . iT h .p .p .p iT #
0 3 2 ! 3 2 ; 1 2 1 2 1 2 :

B˛ˇ! p
2=3

T˛ˇ!
!1 T
T˛ˇ! D T˛ˇ!
eabc ; Eiabc i D hE
hE e˛ˇ! ; Ei˛ˇ! i
hi eE Ei

T˛ˇ!

xa C xb C xc D 0 ) x! D 0;

"
B˛ˇ! "
" B˛ˇ!
" "

T˛ˇ!
 ˛ˇ

b
γ β
b
π ≡ xa + xb + xc = 0

a α a

c α
β
c

b)

T˛ˇ!

"
" ˛ˇ
2 3 r " #2 x 3
$ % xa 1 !1=2 !1=2 a
p . p .
x˛ 4 xb 5 D 2 4 xb 5 ;
D T˛ˇ
xˇ 3 0 3 2 ! 3 2
xc xc

2 3
2 3 2 3 r 0
xa x˛ p . $ % $ %
2 6 1 7 x˛ x˛
4 xb 5 D T T 4 xˇ 5 D 6 !1=2 3 2 7 D T
T˛ˇ :
˛ˇ!
34 p . 5 xˇ xˇ
xc 0 !1=2 ! 3 2

! "T
xEabc D xa xb xc "
! "T
! xEabc D xa xb xc !

˛ˇ
" Babc 120ı

T˛ˇ
 ESa
Ia LSa RSa
Va
+
Ib LSb RSb + ESb
+ Vb N
VDC
-
Ic LSc RSc +
Vc

ESc

ea D UM .! t /
eb D UM .! t ! 2 "=3/
ec D UM .! t C2 "=3/

r
3
e˛ D UM .! t /
2
r
3
eˇ D ! UM .! t /:
2
eEabc
q ˛ˇ
3
eE˛ˇ 2
UM
!
 N
Va ; Vb Vc G

ESa ; ESb ESc

! "T
VEabc D Va Vb Vc ˛ˇ

VDC

"

˛ˇ

VE˛ˇ
"

VE100 VE110
VE˛ˇ
"

V1
V2 ı

jV1 j jV2 j
ı1 D ˇ ˇ ı2 D ˇ ˇ:
ˇE ˇ ˇE ˇ
ˇV100 ˇ ˇV110 ˇ

ı3

ı1 C ı2 C ı3 D 1;

VO
"
V O D ı1 V100 C ı2 V110 C ı3 V111 D V1 C V2 D VE˛ˇ ;

VE111 VE000
Vector 100: Va = VDC Vb = 0 Vc = 0 Vector 110: Va = VDC Vb = VDC Vc = 0

V110
Va Va
V100
+ Vb + Vb
- VDC - VDC
Vc Vc

G G

Vector 010: Va = 0 Vb = VDC Vc = 0 Vector 011: Va = 0 Vb = VDC Vc = VDC

V010
Va Va
V011
+ Vb + Vb
- VDC - VDC
Vc Vc

G G

Vector 001: Va = 0 Vb = 0 Vc = VDC Vector 101: Va = VDC Vb = 0 Vc = VDC

Va Va
+ Vb + Vb
- VDC - VDC
Vc Vc
V001
V101
G G

Vector 111: Va = VDC Vb = VDC Vc = VDC Vector 000: Va = 0 Vb = 0 Vc = 0

Va Va
V111 V000
+ Vb + Vb
- VDC - VDC
Vc Vc

G G

"
 V110 V110
*
Vαβ
*
Vαβ V1= δ1V110
V1
V100
V2 V100 V3=δ3V000 V2=δ2V100

V1 V2

˛ ˇ
VE˛ˇ
"

VE˛ˇ
"
V1 V2
ı1 ı2 ı3

˛ˇ

ı1 ı2 ı3

ı1 ı2 ı3
ı1 ı2 ı3

UMMAX

r r p
3 2 3 2 VDC VDC
UMMAX D VDC , UMMAX D p Š 1:15 ;
2 3 2 3 2 2
 VE˛ˇ
"

"
!

V110
V111 1
VDC
2

V011
V010
1
− VDC
V000 V101 2
V100

V001

˛ˇ

Z1y Z2y Z2x Z3x

2
3 1

4 6 Z1x Z3y
5
 VE˛ˇ
"

2 3 2 3 2 3
1 1 2
1 !p 1 p 0 p
6 3 7 6 3 7 6 3 7
M1 D 6
4
7 M2 D 6 7 M3 D 6 7;
2 5 4 1 5 4 1 5
0 p !1 p !1 ! p
3 3 3
˛ ˇ Zi ; i 2
f1; 2; 3g

Zix Ziy

V!
tmp D pˇ
3

Z1x D V˛" ! tmp Z1x

Z2y D !Z1x Z2y

Z1y D 2tmp Z1y

Z3x D Z1y Z3x

Z2x D V˛" C tmp Z2x

Z3y D !Z2x Z3y

Zix Ziy

Zix Ziy
 Yes No
Z1x.Z1y < 0

Yes No
Z1x > 0

st th
1 4

Yes No
Z2x.Z2y < 0

Yes No
Z2x > 0
nd th
2 5

Yes No
Z3x > 0
rd th
3 6

VDC Va VDC Va
VDC VDC
Vb Vb
VDC VDC
Vc Vc
V100 V110 V111 V111 V110 V100 V000 V100 V110 V111 V110 V100 V 000
δ 2Ts δ1 Ts δ 3Ts δ 3Ts δ1 Ts δ 2Ts δ 3 Ts/2 δ 2Ts δ1 Ts δ 3 Ts δ1Ts δ 2Ts δ 3 Ts/2

Ts Ts Ts Ts
 !
"

N G; VNG

VNG
!

VEabc

˛ˇ

˛ˇ
 ES
Iabc LS RS
+ + N
VDC
-

V1

V2
abc
αβ
SVM

Vβ* Vα* Iβ Iα
-
α-controller Iα_ref
+

-
β-controller
+ Iβ_ref
DSP

˛ˇ

˛ ˇ

2 3 2 3 2 3 2 3 2 3
I 1 0 0 Ia 2 !1 !1 Va
d 4 a 5 RS 4 5 4 Ib 5 C 1 4 !1
Ib D! 0 1 0 2 !1 5 4 Vb 5
dt LS 3LS
Ic 0 0 1 Ic !1 !1 2 Vc
2 3 2 3
1 0 0 ESa
1 4 5 4 ESb 5 ;
! 0 1 0
LS
0 0 1 ESc
1
VNG D 3
.Va C Vb C Vc /
T˛ˇ
 T
xEabc T˛ˇ xE˛ˇ

2 3
2 !1 !1
d E RS 1 4 !1
I˛ˇ D ! T T
I3 T˛ˇ IE˛ˇ C T 2 !1 5 T˛ˇ
T
VE˛ˇ
dt LS ˛ˇ 3LS ˛ˇ
!1 !1 2
1
! T T
I3 T˛ˇ EES˛ˇ ;
LS ˛ˇ

I3 3#3

d E RS 1 1
I˛ˇ D ! I2 IE˛ˇ C I2 VE˛ˇ ! I2 EES˛ˇ ;
dt LS LS LS

I2 2#2 VNG
T˛ˇ

˛ ˇ

˛ˇ

VNG
T˛ˇ

VNG

VNG
 ˛ˇ

q
q β
r
V
b β

d
ϕ
θ
α a θ2 d
θ1
c
α
d q ˛ˇ !
# D!t
˛ˇ
90ı
VE

! dq VE
#1 #2
! '
VE d q

! dq

dq
!

$ % $ % $ %$ %
xd x˛ # # x˛
D Tdq D ;
xq xˇ ! # # xˇ

# D !t

& '
xEdq D xd C j xq D x˛ C j xˇ . # !j # / D xE˛ˇ e !j" :

Tdq R2

$ % $ % $ %$ %
x˛ T xd # ! # xd
D Tdq D ;
xˇ xq # # xq
 xE˛ˇ D xEdq e Cj"

2 RS 3
! C!
d E 6 LS 7 E 1 E 1 E
Idq D 4 RS 5 Idq C LS I2 Vdq ! LS I2 ESdq ;
dt !! !
LS

I~abc

V1

V2

SVM
abc
↵
V* V*↵ I I↵
de-coupling
✓ ↵ ✓ ↵
!LS
dq dq
!LS
Iq Id
+
+ +
-
d-controller Id ref
+
-
q-controller
DSP + Iq ref

dq

dq
 ˛ˇ

˛ˇ

T
Tdq Tdq
˛ˇ
dq

dq

e ˙j" # D !t
KP0

I~abc rotating reference controller

j✓
e ej✓
abc KI
↵ s

I~↵ ej✓ e j✓
~⇤
V
KI ↵
I~↵⇤ +
+ ~"I↵ s ++

2K0P

proportional controller

!
 I~abc rotating reference controller
j✓
e ej✓
abc
z
K I TS z 1
↵

I~↵ ej✓ e j✓
~⇤
V ↵
I~↵⇤ z
K I TS z 1
+
+ ~"I↵ ++

KP

proportional controller

KP D 2KP0

h ( )i
L e #t f .t / .s/ D ŒL .f /$ .s ! %/

e #t

VEdqC
"
VEdq!
"
 j✓
e ej✓
~⇤
V ~⇤
V ~⇤
V
~"I↵ KI dq+ ↵ + ~"I↵ KI ↵ +

s s j!
ej✓ e j✓

~"I↵ KI ~⇤
V ~⇤
V ~"I↵ ~⇤
V
dq ↵ KI ↵
s s+ j!

VE˛ˇ
"
.s/ VE˛ˇ
"
C
.s/ VE˛ˇ
"
!
.s/ KI KI s
D C D C D 2KI 2 :
"EI ˛ˇ .s/ "EI ˛ˇ .s/ "EI ˛ˇ .s/ s ! j! s C j! s C !2

KI

KI
KP KI

KP Fo .s/

2KI s
Fo .s/ D ;
s2 C !o2

!o VDC D 250
!1
fo D 60 ; LS D 3:5 RS D 1 ˝; fS D 10 GTI D 0:1
Z KP
!CL
!CL D 0:1!S KP D
2KP0 Š 2 !CL LS =.2VDC GTI / D 0:88 KI
Fo .s/ phm
!CL $ !o Fo .s/ % 2KI =s KI

phm D 45ı KI D KIN D 1:25 s !1

IOREF !o IO
"I
!o

P + resonant controller
PWM Load
Inverter
t admittance
itt c
mI(k) gain
Fo(z) 1 1
IOREF
E (k) + m(k)
k d(t)
t IO
εI(k) 1 2VDC RS LS
1+ s
+ - mP(k) + RS
KP

re
Current
Delay effect
ef transducer
Io(k)
z-1-1 GTI

KI D 2KIN
KI D KIN KI D 0:1KIN KI

!o KI
KI
 2
IO

[A]
0

-2 IOREF
0 10 20 30 40 50 60
[ms]

2
εΗ
I
I

[A]
0

-2

0 10 20 30 40 50 60
[ms]]

IOREF IO "I

2 IOREF
[A]

0
IO
-2

0 10 20 30 40 50 60
[ms]

2
εΗ
I
[A]

-2

0 10 20 30 40 50 60
[ms]

IOREF IO "I
C

KI

KP Fo .s/
 Fo .s/

mI .s/ 1 KP G.s/ 1
Go .s/ D D D WP .s/;
eI .s/ KP 1 C KP G.s/ KP
„ ƒ‚ …
WP .s/

WP .s/
WP .s/
!CL WP .s/

100

80
Magnitude (dB)

Crossover
60
(a) (b) frequency
40

20
(c)
0
-20
45
0
(b)
Phase (deg)

-45
(c)
-90
-135
-180
(a)
-225
2 3 4
10 10 10
ω [rad/s]

KI D 2KIN KI D KIN I .c/KI D KIN =10

KI =s
1=KP KI
!ro tro D 1=!ro

KP KP
KI D D 2:2 ;
tro tr
tr D no TO
fO tr D 2 no D 0:12
 fO

fO
C90ı
ı
!90
fO
WP .j 2"fO / !90ı !180ı

!L

5
Magnitude (dB)

-5

-10

-15
0
-45
Phase (deg)

-90
-135
-1
-180
ωL
-225
2 3 4
10 10 10
ω [rad/s]

WP .s/
 Fo
X 2KIk s
Fo .s/ D :
s 2 C .k!o /2
k2Nk

Nk
KIk
KIk

2:2KP 2:2KP
KIk D D ;
tr;k no;k TO

tr;k D no;k TO
no;k TO
k th
!L
!L

!L k D 17

&k
RkDC .s/

RkDC .s/
RkAC .s/

RkAC .s/ D &k ŒRkDC .s ! j k!o / C RkDC .s C j k!o /$

Cj &k ŒRkDC .s ! j k!o / ! RkDC .s C j k!o /$ :
 2
IOREFF

[A]
0
-2
0 10 20 30 40
[ms]
2
IO

[A]
0
-2
0 10 20 30 40
[ms]
2

[A]
0 εI
-2
0 10 20 30 40
[ms]

IOREF IO "I
k!0 k

ej✓ e j(✓+ k)

KIk
s
+
"I mI

KIk +
s

j✓
e ej(✓+ k)

&k

&k D 0 &k
kfO WP .s/

RkDC .s/ D KIk =s

&k
* +
.&k /
X 2KIk s ! .&k /
.&k /
RAC .s/ D ;
s 2 C .k!o /2
k2Nk
 2
IOREF

[A]
0
-2
0 10 20 30 40
[ms]
2
IO

[A]
0
-2
0 10 20 30 40
[ms]
2
[A]

0 εI
-2
0 10 20 30 40
[ms]

IOREF IO "I
k!0 &k
k

2
[A]

0
IOREF
-2
10 20 30 40 50
[ms]
2
[A]

0 IO
-2
10 20 30 40 50
[ms]
0.5
εI
[A]

0
-0.5
10 20 30 40 50
[ms]

FO .s/ IOREF
IO "I

IOREF
 2
[A]

0
IOREF
-2
10 20 30 40 50
[ms]
2
[A]

0 IO
-2
10 20 30 40 50
[ms]
0.5
εI
[A]

0
-0.5
10 20 30 40 50
[ms]

IOREF IO "I
XO
 +VDC
IO transduced External
variable input

LS RS Signal XO
VOC Conditioning
IO +
ES

−VDC

Digital Current IS
O
PWM Controller −
+

IOREF
XS
O
External
Controller +
−

XOREF
Microcontroller or DSP

XO XO
(s)
IO
Signal
Signal
conditioning
sampling
IO IOREF XS
O
Current External
Controller Controller +

XOREF

IO .s/ 1
WI .s/ D Š G0 ;
IOREF .s/ 1 C s!C C

!C C
 ! "
IO .z/ 1
WI .z/ D Š Z G0 ;
IOREF .z/ 1 C s!CC

XO .s/ =IO .s/

G0

!CC
1
!CC D ;
2"fCL
fCL

IO .s/ 1 " sTS

D G0 ;
IOREF .s/ 1 C sTS

IO .s/ 1 " sTS =4

D G0 :
IOREF .s/ 1 C sTS =4

IO .z/ G0
D 2;
IOREF.z/ z

IO .z/ G0
.z/ D ;
IOREF z
 TS =2 TS

+VDC
IO transduced

LS Signal VO
VOC Conditioning
+
IO +
VO
CS ILOAD
VDC

Digital Current IS
O
PWM Controller -
+

IOREF S
VO
Voltage
Controller -
+

VOREF
Microcontroller or DSP
Rated output power, PO 1500 (VA)

Phase inductance, LS 1.2 (mH)

Output capacitor, CS 85 (µF)

Output voltage, VO 120 (VRMS )

Output frequency, fO 60 (Hz)

DC link voltage, VDC 250 (V)

Switching frequency, fS 20 (kHz)

Current transducer gain, GTI 0.1 (VA 1)

Voltage transducer gain, GTV 0.02 (VV 1)

IO

.'/
 |GOL(ω)|
40

20
[dB] 0

-20

-40

102 103 104 105 106

! GOL(ω) 40

-40
[deg]
-80

-120

-160

102 103 104 105 106

ω [rad/s]

d
x.t / D A x.t / C B1 V OC .t/ C B2 ILOAD .t/;
dt
# $T
x.t/ D V O .t/ INO .t/ V OC
ILOAD
! " ! " ! "
0 1=Cs 0 "1=Cs
AD B1 D B2 D :
"1=Ls 0 1=Ls 0
 V OC
ILOAD

x.k C 1/ D ˚ x.k/ C #V V OC .k/ C #I ILOAD .k/;

2 1 3 2 Ts 3
.!o Ts / !o Ts 1
6 !o CS 7 6 CS 7
˚ D e ATs D 4 1 5 #4 Ts 5;
" ! o Ts !o Ts " 1
!o LS LS
2 3 2 3
% & 1" .!o Ts / 0
#V D e ATs " I2 A!1 B1 D 4 1 5 # 4 Ts 5 ;
.!o Ts /
!o LS LS
2 3 2 3
1 Ts
% & !1 " .! T / "
#I D e ATs " I2 A B2 D 4 !o CS o s 5
# 4 CS 5 :
1" .! o Ts / 0

I2 2$2 TS !o

!o TS % 1

TS # $
INO .k C 1/ D INO .k/ C V OC .k/ " V O .k/ ;
LS

ES VO

!o TS % 1
 IO 1 1 " sTS
.s/ D ;
IOREF GT I 1 C sTS

VO 1
.s/ D :
IO sCS

VOREF + εV 1 1− s TS IO + 1 VO
K P + KsI GTI 1+ s TS sCS
- -

VO S I LOAD

GTV

KP KI
 200
VO
VOREF 150
"V
100

50
"V
[V] 0

-50

-100

-150

-200
20 25 30 35 40 45 50 55 60 65 t
[ms]

VO
180 VO
VOREF
"V
140 VOREF

100
[V]

60

20
"V
0

-20
35 36 37 38 39 40 t
[ms]

ARMS

CF D 2
 40 1:04

T T

21 - > 1- >
2

Ch1: 10 A/div 10 ms/div 18/02/15 17:19:21 Ch1: 10 A/div 5 ms/div 18/02/15 17:20:56
Ch2: 50 V/div 10 ms/div Ch2: 50 V/div 5 ms/div

fO D 50

fCL

fCL

fCL

' (
GTV 1 " sTS 1 KI
GOLV .s/ D KP C :
GTI 1 C sTS sCS s
 KP KI
q
GTV KI2 C .!CL KP /2
2
D 1;
GTI !CL CS
!CL D 2"fCL
phm
ı

' (
ı ı !1 !1 KP
" 180 C phm D "180 " 2 .!CL TS / C !CL :
KI

fCL D
!1
KP D 1:92; KI D 6:84 $ 102

)
KI dig D KI TS
KP dig D KP :
LS
 A
Feed-forward of
capacitive current ILOAD
TS
VOREF ^
+ Voltage ∆IC_REF Current reference IC+ IOREF Current IO - VO
control
ZCS(z)
- control interpolation + + + IC
2TS B
^I Load current
LOAD estimator

ZCS .z/

TS V # $
V O .h C 1/ D V O .h/ C INO .h/ " ILOAD .h/ ;
CS

h TS V

TS V TS

CS # $
IOREF .h C 1/ D "IOREF .h/ C VOREF .h/ " V O .h/ C 2 ILOAD .h/ ;
TS V
 ILOAD .h C 1/ Š ILOAD .h/

TS V D 2TS

CS

CS
IOLOAD .k " 1/ D " ŒV O .k/ " V O .k " 1/$ C INO .k " 1/;
TS

CS
% IC .h/ D ŒVOREF .h/ " V O .h/$ " % IC .h " 1/;
2 Ts
IO REF
%IC REF
 TS

x.k C 1/ D ˚ x.k/ C #V K x .k/ D ˚F x .k/ ;

h i
V OC K x K D KV O KINO

˚F D ˚ C #V K
KV O KINO

1"2 .!o Ts / 1C2 .!o Ts /

kV O D kINO D "!o LS ;
2"2 .!o Ts / 2 .!o Ts /

V OC
 VO 200

VOREF 150
"V
100

50
"V
[V] 0

-50

-100

-150

-200
20 25 30 35 40 45 50 55 60 65 t
[ms]

VO VOREF
180
VOREF
"V
140
VO

100
[V]

60

20
"V
0

-20
35 36 37 38 39 40 t
[ms]

V OC

VO
!o TS % 1
VO 200

VOREF 150
"V
100

50
"V
[V] 0

-50

-100

-150

-200
20 25 30 35 40 45 50 55 60 65 t
[ms]

VO
180
VOREF
VOREF
"V
140

VO
100
[V]

60

"V
20

-20
35 36 37 38 39 40 t
[ms]
 x.k C 1/ D ˚ x.k/ C #V V OC .k/ C #I ILOAD .k/;

x.k/ D ŒV O .k/ INO .k/$T

2 1 3 2 3
.!0 Ts / .!0 Ts / 1" .!0 Ts /
6 7
˚ D4 1
!0 CS 5; #V D 4 1 5;
" .!0 Ts / .!0 Ts / .!0 Ts /
!0 LS !0 LS
2 3
1
" .! T /
#I D 4 !0 CS 0 s 5
:
1" .!0 Ts /

V OC

V OC .k C 1/ D ŒK1 K2 $ .xREF .k/ " x.k// C K3 V OC .k/;

K1 ; K 2 K3 xREF .k/ D ŒV OREF .k/ INOREF .k/$T

2 3
˚11 ˚12 #V 11
˚A D 4 ˚21 ˚22 #V 21 5 :
"K1 "K2 K3

K1 ; K 2 K3
˚A
 1C2 .!0 TS / " 4 2 .!0 TS /
K1 D " ;
2Œ1 " .!0 TS /$
! 0 LS 2
K2 D " Œ1 " 2 .!0 TS / " 4 .!0 TS /$;
2 .!0 TS /

K3 D "2 .!0 TS /;
 Z

"V

M TS
 εV IOREF
K REP
+ +

z–M

IOREF
εV z –M+L F2(z) K REP
+ +

z–M F1(z)

εV IOREF
z–M+L K REP
+ +

z–L F1(z)

F1 .z/
F2 .z/

M "L
L
 F2 .z/ D 1

M L
KREP F1 .z/
M
M

M D 332
 KP

εV + IOREF
Proportional controller
+

z–M+L K REP
+ +

z–L F1(z)

Repetitive controller

KP
VOREF eV + IOREF 1 1 IO VO
Z CS (z )
+ - + G TI z 2 + -
REP(z)
VO_S ILOAD

G TV
 z !M CL
REP.z/ D KREP :
1 " z !M F1 .z/

ZCS .z/

F1 .z/
KREP

Mc

Mc D 4 M

F1 .z/

Mc
 60
Proportional +
Repetitive
40
Magnitude [dB]
20

Proportional
0

-20

-45
Phase [deg]

-90

-135

-180
102 103 104
! [rad/s]

Mc

t D 0:1
 200 80

VO IO
150 60

εV IOREF
100 40

50 20

[V] 0 [A] 0

-50 -20

-100 -40

-150 -60

-200 -80
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55

[s] t [s] t
a)
a) b)
b)

VO 150
IO 60

εV IOREF
100 40

50 20

[V] 0
[A] 0

-50 -20

-100
-40

-150
-60

0.085 0.09 0.095 0.1 0.105 0.11 0.115 0.07 0.075 0.08 0.085 0.09 0.095 0.1

[s] t [s] t
c) d)

FDFT .z/
 VO IO
150 60

εV IOREF
100 40

50 20

[V] 0 [A] 0

-50
-20

-100
-40

-150
-60

0.57 0.575 0.58 0.585 0.59 0.595 0.57 0.575 0.58 0.585 0.59 0.595

[s] t [s] t

FDFT .z/

F1 .z/

0 1
X
M !1 X ! "
2 @ 2"
F DFT .z/ D h .i C Na / A z !i ;
M M
iD0 h2Nh

Nh Na

M
Nh

Na
Na
F DFT .z/ z !Na
 KP

εv 2K I + IOREF
s + ω O2
2
+ +

Rotating reference
frame PI controller

FDFT (z) KF
+ +

z –Na

DFT filter based controller

Na

M D 330
 Mc
M
10 .Mc D 10; M D 33/

Mc
Mc

80
Rotating PI +
60
DFT-based
Magnitude [dB]

40

20

0 Rotating PI

-20
90
45
Phase [deg]

0
-45
-90
-135
-180
102 103 104
ω [rad/s]

KF
Nh
 200 80
VO IO
150 60

εV IOREF
100 40

50 20

[V] 0 [A] 0

-50 -20

-100 -40

-150 -60

-200 -80
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55

[s] t [s] t
a) b)

VO 150
IO
60

εV IOREF
100
40

50
20

[V] 0 [A] 0

-50 -20

-100 -40

-150 -60

0.07 0.075 0.08 0.085 0.09 0.07 0.075 0.08 0.085 0.09 0.095

[s] t [s] t
c) d)
VO IO
150 60

εV IOREF
100 40

50 20

[V] 0 [A] 0

-50 -20

-100 -40

-150 -60

0.57 0.575 0.58 0.585 0.59 0.595 0.6 0.57 0.575 0.58 0.585 0.59 0.595

[s] t [s] t

LAC LS + V
DC
RDC
IAC IO
RF CF2 -
+
EAC ILOAD VSI Rectifier dc load
CF1

Input filter

ILOAD
RDC
 IAC EAC
VDC

d
EC D PAC " Ploss " PLOAD :
dt DC
ECDC D 12 CDC VDC
2
Ploss
2
PLOAD D VDC =RDC PAC

2
PAC D GEQ EAC RMS
;
 GEQ

EAC

1 d 2 V2
CDC VDC 2
D GEQ EAC " Ploss " DC ;
2 dt RMS
RDC
VDC GEQ

2
VDC

2
VDC
VDC
VDC

EACRMS Ploss

VDC D V DC C vdc ; GEQ D G EQ C geq

2
vdc RDC EAC RMS
1
.s/ D ;
geq 2V DC 1 C sCDC R2DC

ILOAD

RDC
 IAC
VDC

"
IOREF D "IAC C ILOAD D "GEQ EAC C ILOAD ;
GEQ

ILOAD

ILOAD
Sample=
P
Q
 Electronic Power Processor

DER/ES Interface Grid Interface

DER/ES DC-DC DC-AC

+ +
Fuel Cell
−

PV Generator

FPGA
Internal communication bus
DER supervision
Battery GPP with RTOS

(a)
Micro-grid communication bus

− +

DC-AC Grid

(b)
Grid Interface

P Q
Subsystem Functionality Scope Target
PWM Local
PLL Local
FPGA
Current loop Local
Inverter Fault detection Local
P loop Local
Q loop Local/Distributed
Grid voltage control Local/Distributed
RT GPP
Grid characterization Local/Distributed
Global optimization Distributed
PWM Local
FPGA
DC/DC Input V/I control Local
Source/storage optimization Local/Remote RT GPP

ı
2
Feature Parameter Value
Model PowerPC
Processor
Processor Speed 400 MHz
Nonvolatile 512 MB
Memory
System 256 MB
Model Xilinx Spartan-6 LX45
FPGA
# Slices 6822
# DSP48s 58
Network Network interface IEEE 802.3 Ethernet
RS-232, RS-485
Communication Port
CAN, USB
16 AI, 12-bit, ±10 V, 100 kHz
Peripherals Channel
14 ch., 500 kHz gate drivers (1)

˛
90ı

f0
!

VGRID
 communication
interface cos

PREF
Digital PWM
Monitoring LP filter Gate signals
& Synch. sampling
datalog Q REF PI regulation

LP filter
sin
RT PC
GPP

LP filter Sat.
estimator v dq transform vd f0
vGRID
PI
reg.
v vq 0

System supervisor
Alarm generator

FPGA

PREF QREF
Parameter Symbol Value
Nominal input voltage VDC 400 V
Switching frequency fs 18 kHz
Filter inductance LP H 1.2 mH
Series inductor resistance rs,P H 50 mΩ
Output filter capacitance CP H 10 µF
Output filter inductance LF 45 µH
Current sense gain GT I 375 mV/A
Voltage sense gain GT E 17.25 mV/V
Nominal power So 3 kVA
Crossover frequency fCR 2 kHz
Phase margin ΦM 60 ◦

Carrier amplitude ±Ar ±2777

A/D conversion delay ∆tAD 10 µs
PI calculation delay ∆tcalc 0.1 µs
10 =

=
 Feature Parameter Value
Model Intel Core i7-660UE
Processor
Processor Speed 1.33 to 2.4 GHz
Nonvolatile 32 GB (min.)
Memory
System 2 GB (min.)
Model Spartan-6 LX150
FPGA
# Slices 23038
# DSP48s 180
Network Network interface IEEE 802.3 Ethernet
RS-232, RS-485/422, USB
Communication Port
VGA, CAN, MXI-Express
4 AO, 16-bit, ±10 V, 100 kHz
Peripherals Channel
8 Digital Input/Output (1)

0 2

d q
 Parameter Symbol Value
Branch resistance RLIN E 1 Ω
Branch inductance LLIN E 150 µH
Branch length lb 260 m
Nominal grid voltage VP CC 230 Vrms
Nominal grid frequency f0 50 Hz

Œ0:22 0:23 0:20 0:25 0:84 1:07"

 400 20

Injected current i LINE (A)

P = 0 W!
Grid voltage vGRID (V)
vGRID
Q = 0 VAR
200 10

0 i LINE 0

− 200 P = 2 kW! P = 0 W! −10

Q = 0 VAR Q = 2 kVAR
− 400 −20
0.02 0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Time (s)

400 20

Injected current i LINE (A)

Grid voltage vGRID (V)

vGRID
200 10

0 i LINE 0

200 10

400 20
0.02 0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Time (s)

400 20

Injected current i LINE (A)

vGRID
Grid voltage vGRID (V)

200 10

0 i LINE 0

200 10

400 20
0.02 0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Time (s)

P Q
 cRIO-9082

Grid
Digital Analog
+
Input Output
VSI hardware

GPIC
iPH(t)
Gate signals VSI
Local Control
vGRID(t)

Development PC
Ethernet network Development,
supervision,
datalog

x.k C 1/ D x.k/ C ˛ u.k/;

 x ˛
!T
L L
u

50
Tsi m D 100

16

100 =

100 =
 100

fCR 180 fCR

#$ D !% D 180 ;
fDAC % fDAC
fCR fDAC

10
ı
3:6

VDC GT I
Ar
e !s !tct rl
Ti 0 .s/ D 1
;
s LPH C s CPH
== .s LGRID C RGRID /

#tct rl #tAD
#tcalc #tP W M

TS
2

ı
2:5

!Iphavg
Iphpk

1 #Iphpk2pk #Iphavg 1 #Iphpk2pk

" " ;
3 Iphpk Iphpk 2 Iphpk
!Iphpk2pk
Iphpk
16
 −50

Magnitude (dB)
−100

−150

−200
0 1 2 3 4 5
10 10 10 10 10 10
0

−100
Phase (deg)

−200

−300

−400
0 1 2 3 4 5
10 10 10 10 10 10
Frequency (Hz)

.DA/
Ti 0 Ti0

fCR =fDAC 0:05

2 =

Tsi m D 100

nblost D 2 .fclock Tsi m /

fclock
 Tsi m fclk " 1

LPH

100

144

3
 04
RT simulation
Partitioned model RT
03 Ideal

02

01

−0 1
−2 −2000 −1000 0 1000 2000 2
Modulating signal m
 400 20

Injected current i LINE (A)

Grid voltage vGRID (V)
vGRID
200 10

0 i LINE 0

200 10

400 20
0.02 0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Time (s)

400 20

Injected current i LINE (A)

Grid voltage vGRID (V)

vGRID
200 10

0 i LINE 0

200 10

400 20
0.02 0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Time (s)