Mcxnx4X: 32-Bit Arm Cortex-M33 at 150 MHZ (N94X and N54X)

MCXNx4x
32-bit Arm Cortex-M33 @ 150 MHz (N94x and N54x)

Rev. 4 — 01/2024 Data Sheet: Technical Data
MCXN54x
MCXN94x
® ®
32-bit Arm Dual Cortex-M33 TrustZone microcontroller for Industrial and
Consumer IoT Applications with USB HS and FS, CAN FD, LP Flexcomm
Interface, SDIO, 32-bit counter/timers, SCTimer/PWM, FlexPWM, 4x 16-bit
2.0 Msamples/sec ADC, Comparator, Temperature Sensor, PKC, AES,
PUF, SHA, CRC, RNG
• Highly secure: TrustZone for Armv8-M, secure boot/update ROM, NXP's 184VFBGA
EdgeLock® secure subsystem (ELS) S50 black-box secure enclave 100HLQFP
with key storage and crypto algorithms protected from side-channel 9 x 9 x 0.86 mm,
14 x 14 x 1.4 mm,
attacks as well as internal/external tamper events, flash encryption, 0.5 mm
0.5 mm
external memory interface with on-the-fly PRINCE decryption, options
for hardware Physically Unclonable Function (PUF) and Factory Root of NOTE
Trust programming All information
on the HLQFP
• Industrial Strength: Industrial communication protocol support, 15-year
package is
longevity, high-resolution mixed signal analog, CAN-FD, BLDC/PMSM preliminary and
Motor Control support, integrated sensor interfaces (MIPI-I3C, I2C, SPI) pending
• Power-efficient: < 70 μA/MHz active current, < 10 μA Power down mode qualification.
with RTC enabled and 8 KB SRAM retention, < 2.5 μA Deep Power-
down mode with RTC active and 8 KB SRAM
Target Applications Advanced Security

• Industrial and Consumer IoT • ELS S50
• Industrial Communications — AES-256, SHA-2, RNG
• Smart Metering — ECC-256 (ECDSA, ECDH)
• Motor Control • PKC (Asymmetric Crypto accelerator)
• Automation & Control • SRAM PUF for RoT Key
• Sensors • PRINCE OTF Encrypt/Decrypt for internal and external
Flash
CPU Core Platform
• Protected Flash Region (PFR)
• Primary CPU: Cortex-M33
• DICE and UID and Debug authentication
— TrustZone, MPU, FPU, SIMD, ETM, CTI
• 2x Code Watchdog
• Secondary CPU: Cortex-M33 Barebone
• Tamper Detect
• DSP Accelerator (PowerQUAD, w CP intf)
— Eight tamper pins
• SmartDMA
— Active and passive tamper pin detect
• N1-16 Neural Processing Unit (NPU)
— Voltage tamper detect
• Coolflux BSP32
• Secure Multilayer Bus Matrix
Table continues on the next page...
NXP reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products.
NXP Semiconductors
• Two asynchronous DMA modules (16-channels each) — Temperature tamper detect

— Clock tamper detect
Memories and memory expansion
• OTP Fuses
• Dual-bank Flash supporting Flash Swap and Read While
— Can permanently configure boot and security
Write: Up to 2x 1024 KB FLASH instances with ECC
options
(support one bit correction and two bits detection).
— 4 KB fuse area
• Cache Engine with 16 KB RAM
— Up to 384 b fuse area for storing key hashes
• Up to 512KB RAM (up to 416KB with configurable ECC
that supports single correction, double bit detection) — Key revocation capability
• Up to 4x 8 KB ECC RAM can be retained down to VBAT • Digital Glitch Detect
mode
Analog modules
• FlexSPI with 16 KB cache supporting XIP, Octal/Quad
• 2x 16-bit ADC
SPI flash, HyperFlash, HyperRAM, Xccela memory types
— Each ADC can be used as two single end input
• 256 KB ROM
ADC, or one differential input ADC
Low-Power Performance
— Up to 2 Msps in 16-bit mode, and 3.15 Msps in
• Active 12-bit mode
— 75 µA/MHz (3.3 V, @25 C) in OD Active Mode — Up to 75 ADC Input channels (depending on the
(While(1) executing from flash, DC/DC enabled) package)
• Deep Sleep — One integrated temperature sensor per ADC.
— 270 µA, (full 512 KB SRAM retention, 3.3 V @25 C) • Three High-speed Comparators with 17 input pins and
8-bit DAC as internal reference
• Power Down
• 2x CMP is functional down to DPD mode
— 4.2 µA, (full 512 KB SRAM retention, 3.3 V, @25 C)
• Two 12-bit DAC with sample rates of up to 1.0 MSample/
• Deep Power Down
sec.
— < 2.0 µA, 5.3 ms wake-up (RTC enabled 8 KB RAM
• One 14-bit DAC with sample rates of up to 5 MSample/
and Reset pin enabled, @25 C)
sec.
Flexible System and Clocks
• Three OpAmps can be configured to:
• 144 MHz free-running oscillator (FRO-144M)
— Programmable Gain Amplifier
• 12 MHz free-running oscillator (FRO-12M)
— Differential Amplifier
• 16 kHz free-running oscillator (FRO-16k)
— Instrument Amplifier
• 32 kHz low-power crystal oscillator
— Transconductance Amplifier
• Up to 50 MHz low-power crystal oscillator
• Highly accurate VREF ±0.2 % and 15 ppm/deg C drift
• 2 x phase-locked loop
Timers
• Hardware and Software Watchdogs
• Five 32-bit standard general-purpose asynchronous
Communication interfaces timers/counters, which support up to four capture inputs
• USB High-speed (Host/Device) with on-chip HS PHY and four compare outputs, PWM mode, and external
count input. Specific timer events can be selected to
• USB Full-speed (Host/Device) with on-chip FS PHY, generate DMA requests.
USB Device
• SCTimer/PWM
• uSDHC
• LPTimer
32-bit Arm Cortex-M33 @ 150 MHz (N94x and N54x), Rev. 4, 01/2024
Data Sheet: Technical Data 2 / 139
NXP Semiconductors
• 10x LP Flexcomms each supports SPI, I2C, UART • Encoder

• 2x FlexCAN with FD, 2x I3Cs, 2x SAI • Frequency measurement timer
• 1x Ethernet with QoS • Multi-Rate Timer
• 1x FlexIO programmable as a variety of serial and • Windowed Watchdog Timer
parallel interfaces, including, but not limited to Display
• RTC with calendar
Driver and camera interface
• Micro Timer
• 2x EVM Smart Card Interfaces
• OS Event Timer
• Programmable Logic Unit (PLU)
HMI
Motor Control Subsys
• Digital PDM Microphone
• 2x FlexPWM each with 4 sub-modules, providing 12
PWM outputs (no Nanoedge module) — Allows connection of up to 4 MEMS microphones
with PDM output
• 2x Quadrature Encoder/Decoder (ENC)
• TSI (Capacitive Touch Sensor Interface)
• 1x Event Generator (AND/OR/INVERT) module support
up to 8 output trigger — Up to 25 self-cap channels, and up to 8 TX x 17 RX
mutual-cap channels
• SINC Filter Module (3rd order, 5ch, Break signals
connections to PWM) — Water proof under self-cap mode
Inputs Supply Voltage options: — Functions down to Power-Down Mode
• Integrated voltage regulator • Up to 124 GPIOs
— Buck DC-DC, Core LDO, other LDOs — 1.2 V support at reduced performance (available
only on Fast pads)
• Separate AON domain on VDD_BAT pin
— Five independent IO power rings
• Operating voltage: 1.71 V to 3.6 V
— 100 MHz IO on P2 and P3
• IOs: 1.71 V-3.6 V full-performance
— Up to 28-pin wake-up sources function down to
Operating Characteristics
deep power-down mode
• Temperature range: -40 °C to 125 °C
— Support 1.71 V~3.6 V IO supply range
Table 1. Ordering Information
Orderable Part Number1 Part Number 2 Embedded Features Package

Memory
Flash SRAM Tamper GPIOs SRAM Pin Type

(MB) (K) Pins (max) PUF Count
(max)
(P)MCXN547VNLT (P)MCXN547VNLT 2 512 2 74 Y 100 HLQFP
(P)MCXN547VDFT (P)MCXN547VDFT 2 512 8 124 Y 184 VFBGA
NXP Semiconductors
Table 1. Ordering Information (continued)
Orderable Part Number1 Part Number 2 Embedded Features Package

Memory
Flash SRAM Tamper GPIOs SRAM Pin Type

(MB) (K) Pins (max) PUF Count
(max)
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
2. As marked on package
NOTE
All information on the HLQFP package is preliminary and pending qualification
Table 2. Device Revision Number
Device Mask Set Number SYSCON[DIEID] 1 JTAG ID Register[PRN]
P02G 0x0052_09ax 0x0726_402B
1. 'x' in the DIED field is dependent on the minor revision of the silicon
Table 3. Related Resources
Type Description Resource
Fact Sheet The Fact Sheet gives overview of the product key features and its Fact Sheet
uses.
Reference The Reference Manual contains a comprehensive description of the MCXNx4xRM

Manual structure and function (operation) of a device.
Data Sheet The Data Sheet includes electrical characteristics and signal This document
connections.
Chip Errata The chip mask set Errata provides additional or corrective MCXNx4x_1P02G
information for a particular device mask set.
Package Package dimensions are provided in package drawings. • HLQFP 100-pin: 98ASA01897D
drawing
• BGA 184-pin: 98ASA01888D
Software MCUXpresso SDK. An open source software development kit http://www.nxp.com/mcuxpresso

development (SDK) built specifically for your processor and evaluation board
kit selections.
NOTE
The EdgeLock Secure Subsystem (ELS) is also known as EdgeLock Secure Enclave, Core Profile (ELE). This
document uses the ELS name, but other materials might refer to this module as EdgeLock Secure Enclave, Core
Profile or ELE.
NXP Semiconductors
TZ DSP FPU MPU Debug Clocks, PoR

Interface
Power control, LVD/HVD
Coprocessor interface
with math function DC-DC Converter,
Power 4x 4 KB 2x 2 KB LDOs, FRO
Arm Quad Private RAM PKC RAM system functions PLL
Cortex M33
System
Code
NPU
(N1-16) Smart
CoolFlux Micr- DMA DMA PKC ELS USB USB uSDHC
DMA ENET
LPCAC w/ 2 KB BSP32 CM33 0 1 FS HS
16 KB Cache
D O P X Y D I C
System
Flash
M0 M1 M11 M7 M8 M9 M10 M2 M3 M4 M5 M6 P0 M12 M13 M14 1 MB
FMC PRINCE FMU
Flash
1 MB
P1
ROM
P16 CACHE64 IPED Flex
(16 k) W/GCM SPI
P2 RAMX
96 KB
P3 RAMA
Multilayer 32 KB
AHB Matrix
P4 RAMB
32 KB
P5 RAMC
64 KB
P6 RAMD
64 KB
P7 RAME
64 KB
P8 RAMF
64 KB
P9 RAMG
64 KB
P10 RAMH
32 KB
P12
P13
P14
AIPS
P15
bridge 3 MAILBOX
AIPS USBFS IPC
bridge 4 RAM
P11
EWM
Debug
FlexSPI- Mailbox LPFlexcomm
APB
CMX_PERF 2-3 [1]
bridge 0 EMVSIM
SYSCON AIPS LPFlexcomm
(Clock, Reset, Wakeup) (0,1) LPCAC- 4-9 [1] LPFlexcomm
Peripheral input bridge 0 0-1
CMX_PERF
muxes [2] FlexIO
WWDT(0,1) FMU CDOG0
CMP2 MBC SCTIMER /
CTIMER 0 SAI (0,1) PWM
TSI SCG FlexSPI
UTICK Timer SINC Filter CDOG1 GPIO0
GPIO PINT PORT0
OSTIMER OTPC
CTIMER(1,2,3,4) uSDHC Power GPIO
MRT CMC CRC Quad 1,2,3,4
14-bit DAC ADC (0,1)
FREQME LPTMR 0,1 NPX
CACHE64_POLSEL PKC
PORT 12-bit DAC NPU
WUU RAM
(1,2,3,4) (0,1)
APB PWM(0,1)
SPC OPAMP AIPS
GDET(0,1) bridge 1 PKC RAM
(0,1,2) CAN(0,1) bridge 2
CMP(0,1) Interface
VREF ENC(0,1)
EIM eDMA 1
PKC 2x 13C (0,1) RTC [3] Ethernet EVTG
ERM eDMA 1 AIPS
TDET CH0~15 bridge 1
PUF PLU MICFIL USBFS
INTM
GPIO5 USBHS SEMA42
CoolFlux BSP32 SmartDMA USB FS DCD eDMA 0
ELS
PORT5 USB HS PHY
SM3 eDMA 0
TRNG and DCD
Accelerator CH0~15
VBAT
AHBSC
VBAT VSYS VDD_CORE_WAKE VDD_CORE_MAIN

Multiple Layer AHB Matrix 0
Domain Domain Domain Domain
Notes:
[1] : Each LP_FlexComm includes UART, SPI, I2C
[2] : Peripheral input muxes of peripherals in Wake Domain should be put to Wake Domain
[3] : RTC is partitioned to rtc_lp (vbat domain) and rtc_hp (lv domain)
Figure 1. Block Diagram
NOTE
Flash, FlexSPI and bus masters, including, PQ, NPU, BSP32, DMA, USBs, ENET, PKC, S50 have registers. The
registers can be accessed from APB or AIPS bridge.
Contents
1 Feature Comparison ..........................................8 4.3.1 Flash electrical specifications....................... 48

2 Ratings............................................................... 9 4.3.1.1 Timing specifications.....................................49
2.1 Thermal handling ratings................................ 9 4.3.1.2 Flash high voltage current behavior..............50
2.2 Moisture handling ratings..............................10 4.3.1.3 Flash reliability specifications........................50
2.3 ESD handling ratings.................................... 10 4.3.2 FlexSPI specifications...................................51
2.4 Voltage and current maximum ratings.......... 10 4.3.2.1 FlexSPI input/read timing..............................51
2.5 Required Power-On-Reset (POR) Sequencing 4.3.2.2 FlexSPI output/write timing........................... 55
...................................................................... 11 4.3.2.3 eFuse specifications..................................... 57
3 General.............................................................11 4.4 Analog...........................................................57
3.1 AC electrical characteristics.......................... 11 4.4.1 ADC electrical specifications.........................57
3.2 Nonswitching electrical specifications........... 12 4.4.1.1 ADC operating conditions............................. 57
3.2.1 Voltage and current operating requirements.12 4.4.1.2 ADC electrical characteristics....................... 59
3.2.2 HVD, LVD, and POR operating requirements 4.4.2 12-bit DAC electrical characteristics............. 62
...................................................................... 13 4.4.2.1 12-bit DAC operating requirements.............. 62
3.2.3 Voltage and current operating behaviors...... 15 4.4.2.2 12-bit DAC operating behaviors....................62
3.2.4 On-chip regulator electrical specifications.... 16 4.4.3 14-bit DAC electrical characteristics............. 65
3.2.4.1 DCDC converter specifications..................... 16 4.4.3.1 14-bit DAC operating requirements.............. 65
3.2.4.2 DCDC efficiency plots................................... 18 4.4.3.2 14-bit DAC operating behaviors....................66
3.2.4.3 LDO_SYS electrical specifications................ 19 4.4.4 CMP and 8-bit DAC electrical specifications.68
3.2.4.4 LDO_CORE electrical specifications.............20 4.4.5 Voltage reference electrical specifications.... 70
3.2.5 Power mode transition operating behaviors..21 4.4.6 Op-amp electrical specifications................... 72
3.2.6 Power consumption operating behaviors......22 4.4.7 PGA electrical specifications.........................73
3.2.6.1 Power Consumption Operating Behaviors ... 22 4.5 Timers........................................................... 73
3.2.7 EMC radiated emissions operating behaviors 4.5.1 SCTimer/PWM output timing........................ 73
...................................................................... 36 4.6 Communication interfaces............................ 73
3.2.8 Designing with radiated emissions in mind... 36 4.6.1 LPUART........................................................73
3.2.9 Capacitance attributes.................................. 36 4.6.2 LPSPI switching specifications..................... 73
3.3 Switching specifications................................ 36 4.6.3 Inter-Integrated Circuit Interface (I2C)
3.3.1 Device clock specifications........................... 36 specifications................................................ 78
3.3.2 General switching specifications...................37 4.6.4 Improved Inter-Integrated Circuit Interface
3.4 Thermal specifications.................................. 38 (MIPI-I3C) specifications............................... 80
3.4.1 Thermal operating requirements...................38 4.6.5 USB Full-speed device electrical specifications
3.4.2 Thermal attributes......................................... 39 ...................................................................... 83
4 Peripheral operating requirements and behaviors 4.6.6 USB Full Speed Transceiver andHigh-Speed
......................................................................... 39 PHY specifications........................................ 83
4.1 Core modules................................................39 4.6.7 Ultra High Speed SD/SDIO/MMC Host Interface
4.1.1 Debug trace timing specifications................. 39 (uSDHC) AC timing....................................... 84
4.1.2 JTAG electricals............................................40 4.6.7.1 SD/eMMC4.3 (single data rate) AC timing.... 84
4.1.3 SWD electricals ............................................42 4.6.7.2 eMMC4.4/4.41 (dual data rate) AC timing.... 85
4.2 Clock modules.............................................. 43 4.6.7.3 SDR50 AC timing..........................................85
4.2.1 Reference Oscillator Specification................ 43 4.6.8 CAN switching specifications........................ 86
4.2.2 32 kHz oscillator electrical specifications...... 45 4.6.9 SINC timing...................................................86
4.2.3 Free-running oscillator FRO-144M 4.6.10 I2S/SAI switching specifications................... 87
specifications................................................ 47 4.6.11 Flexible IO controller (FlexIO)....................... 90
4.2.4 Free-running oscillator FRO-12M 4.6.12 EMVSIM specifications................................. 90
specifications................................................ 47 4.6.12.1 EMVSIM Reset Sequences.......................... 91
4.2.5 Free-running oscillator FRO-16K specifications 4.6.12.2 EMVSIM Power-Down Sequence................. 92
...................................................................... 48 4.6.13 Ethernet Controller (ENET) AC Electrical
4.2.6 550 MHz PLL specifications..........................48 specifications................................................ 93
4.3 Memories and memory interfaces.................48 4.6.13.1 MII electrical specifications........................... 94
4.6.13.2 RMII.............................................................. 95 7.1 Determining valid orderable parts............... 131
4.6.13.3 MDIO.............................................................95 8 Part identification............................................131
4.7 Human Machine Interface (HMI) modules.... 96 8.1 Description.................................................. 132
4.7.1 Touch sensing input (TSI) electrical 8.2 Part number format..................................... 132
specifications................................................ 96 8.3 Example...................................................... 132
4.7.2 Microphone (MIC)......................................... 96 8.4 Package marking........................................ 132
4.7.3 General Purpose Input/Output (GPIO)..........97 8.4.1 Package marking information..................... 132
4.8 Security modules.......................................... 97 9 Terminology and guidelines........................... 133
4.8.1 Tamper..........................................................97 9.1 Definitions................................................... 133
5 Package dimensions........................................ 98 9.2 Examples.................................................... 134
5.1 Obtaining package dimensions.....................98 9.3 Typical-value conditions..............................134
6 Pinout............................................................... 98 9.4 Relationship between ratings and operating
6.1 MCXNx4x Signal Multiplexing and Pin requirements............................................... 135
Assignments................................................. 98 9.5 Guidelines for ratings and operating
6.2 MCXNx4x Pinout Diagrams........................ 129 requirements............................................... 135
6.3 Recommended connection for unused analog 10 Revision History............................................. 135
and digital pins............................................ 129 Chapter Legal information............................................136
7 Ordering parts................................................ 131
NXP Semiconductors
Feature Comparison
1 Feature Comparison
Table 4. Feature Comparison
Features MCXN947 MCXN946 MCXN546 MCXN547
Package VFBGA184, VFBGA184, VFBGA184, VFBGA184, HLQFP100

HLQFP100 HLQFP100 HLQFP100
CPU Core M33 @150 MHz 2 2 2 2

Platform
NPU Y Y Y Y
Flash 1 Flash ECC Upto 2 MB Upto 1 MB Upto 1 MB Upto 2 MB
Memory SRAM 1 Upto 480 K no ECC Upto 320 K no Upto 320 K no Upto 480 K no ECC
ECC ECC
SRAM ECC 32 K 32 K 32 K 32 K
External Memory FlexSPI with 16 1x, 2 ch 1x, 2 ch 1x, 2 ch 1x, 2 ch

K cache
uSDHC Y N Y Y
Smart Card EVSIM Y N Y Y
Security Secure Key PUF/UDF PUF/UDF PUF/UDF PUF/UDF

Management
Secure Y Y Y Y
Subsystem
Anti Tamper 8 8 8 8
Pin 2
Analog ADC 2 2 2 2
peripherals
DAC 12b, 1 2 2 1 1
MSPS
DAC 14b, 5 1 1 — —
MSPS
Comparator 3 3 2 2
Opamp 3 3 — —
Accurate Vref Y Y Y Y
Serial Interfaces I3C (I2C back 2 2 2 2

compatible)
USB HS Y3 Y3 Y Y
USB FS Y Y Y Y
Ethernet 1 1 1 1
Power Line Y Y — —
Communication
CAN w/wo FD 2 2 1 1
NXP Semiconductors
Ratings
Table 4. Feature Comparison (continued)
Features MCXN947 MCXN946 MCXN546 MCXN547
SAI Up to 4ch Up to 4ch Up to 4ch 4 ch
Flexcom 10 10 10 10
Smart Card 14 14 1 1
Interface
Human Machine Touch Sensor 25 ch 25 ch 25 ch

Interface Interface 5
FlexIO 1 1 1 1
DMIC 4 ch6,5 — 4ch 4 ch
Motor Control FlexPWM 2 2 1 1

Subsystem
Quad Encoder 2 2 1 1
SINC Filter (3rd 1 1 — —

order, 5ch)
Timers RTC 1 1 1 1
32b 5 5 5 5
SCT/PWM 1 1 1 1
MRT 24b 1 1 1 1
uTICK timer 1 1 1 1
WWDT 1 1 1 1
OS Timer 1 1 1 1
1. For more details, please refer to Ordering Information Table

2. Only 2 Anti Tamper Pins available on 100 HLQFP packages.
3. HS USB not available on N94x devices in 100 pin HLQFP package
4. Smart Card Interface not available on N94x devices in 100 pin HLQFP package
5. Only available on BGA package.
6. Please refer to Ordering Information Table for the exact part number that has 4 ch
2 Ratings
2.1 Thermal handling ratings

Table 5. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
NXP Semiconductors
Ratings
2.2 Moisture handling ratings

Table 6. Moisture handling ratings
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
2.3 ESD handling ratings

Table 7. ESD and Latch-up ratings
Description Rating Notes
Electrostatic discharge voltage, human body model +/-2000 V 1
Electrostatic discharge voltage, charged-device model +/-500 V 2
Electrostatic discharge voltage, charged device model +/-750 V

(corner pins)
Latch-up immunity level (Class II at 110 °C junction Immunity Level A 3
temperature)
1. Determined according to ANSI/ESDA/JEDEC Standard JS-001-2017, For Electrostatic Discharge Sensitivity Testing,
Human Body Model (HBM) - Component Level.
2. Determined according to ANSI/ESDA/JEDEC Standard JS-002-2018, For Electrostatic Discharge Sensitivity Testing,
Charged Device Model (CDM) - Device Level
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
2.4 Voltage and current maximum ratings

The table below shows the absolute minimum and maximum ratings for the device. If the values are violated, the device could
be damaged. See Voltage and current operating requirements for operating requirements, and Terminology and guidelines for
definitions of terms.
Table 8. Voltage and current maximum ratings
Symbol Description Min. Max. Unit
VDD_CORE Supply voltage for most digital domains –0.3 1.26 V
VDD_SYS Supply voltage for on-board regulators, LVD / HVDs, and –0.3 1.98 1 V
clock sources
VDD_DCDC Supply voltage for DCDC regulator –0.3 3.63 V
VDD_LDO_SYS Supply voltage for LDO_SYS regulator –0.3 3.63 V
VDD_LDO_CORE Supply voltage for LDO_CORE regulator –0.3 3.63 V
VDD Supply voltage for Port 0, Port 1, Flash arrays –0.3 3.63 V
VDD_P2 Supply voltage for Port 2 –0.3 3.63 V
VDD_BAT Supply voltage for VBAT domain and Port 5 –0.3 3.63 V
NXP Semiconductors
General
Table 8. Voltage and current maximum ratings (continued)
VDD_ANA Supply voltage for analog modules –0.3 3.63 V
VDD_USB Supply voltage for USB analog –0.3 3.63 V
VUSB1_VBUS USB1_VBUS input voltage –0.3 5.5 V
VUSB0_Dx USB0_DP and USB0_DM input voltage –0.3 3.63 V
VUSB1_Dx USB1_DP and USB1_DM input voltage –0.3 3.63 V
VDIO Digital input voltage –0.3 VDD_Px + V

0.3
VAIO Analog input voltage2 –0.3 VDD_ANA + V

0.3
IDD Digital supply current — 1003 mA
ID Maximum current single pin limit (digital output pins) –25 25 mA
1. The part will support 2.75 V for up to 20 s over lifetime to allow for fuse programming
2. Analog pins are defined as pins that do not have an associated general-purpose I/O port function.
3. This limit is per supply pin. This includes all power pins, including, VDD_CORE, VDD_SYS, VDD_LDO_SYS,
VDD_LDO_CORE, VDD, VDD_Px, VDD_ANA, VDD_USB, and VDD_BAT
2.5 Required Power-On-Reset (POR) Sequencing

• Secondary IO supplies (VDD_P2/VDD_P3/VDD_P4) must implement one of the following:
— Must be shorted with VDD (eg: single supply system), or
— Must ramp after VDD_SYS
• VDD_CORE must ramp after VDD
• VDD_P4 and VDD_ANA must be same voltage
• VDD_BAT must ramp before or with VDD_SYS
3 General
3.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured
at the 20% and 80% points, as shown in the following figure.
Low High
VIH
80%
Input Signal Midpoint1 50%
20%
VIL
Fall Time Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
NXP Semiconductors
General
3.2 Nonswitching electrical specifications
3.2.1 Voltage and current operating requirements

Table 9. Voltage and current operating requirements
Symbol Description Min. Typ Max. Unit Notes
VDD_CORE Supply voltage for most digital V 1
domains
• Mid voltage 0.95 1.0
1.05
• Normal voltage 1.045 1.1
1.155
• Overdrive voltage 1.14 1.2
1.26
VDD_SYS Supply voltage for on-board V

regulators, LVD / HVDs, and clock
sources
1.71 1.98
• Normal mode
2.25 2.75
• Fuse Programming
VDD_DCDC Supply voltage DCDC regulator 1.71 3.6 V 2
VDD_LDO_S Supply voltage for LDO_SYS regulator 1.86 3.6 V

YS
VDD_LDO_C Supply voltage for LDO_CORE 1.71 3.6 V

ORE regulator
VDD Supply Voltage for Port 0, Port 1, 1.71 3.6 V

Flash, and CMPx
VDD_P2 Supply voltage for Port 2 V 3,4

1.14 1.32
1.71 3.6
VDD_P3 Supply voltage for Port 3 V 3,5,4

1.14 1.32
1.71 3.6
VDD_P4 Supply voltage for Port 4 1.71 3.6 V 6,4
VDD_BAT Supply voltage for VBAT domain 1.71 3.6 V
VDD_ANA Supply voltage for analog modules VDD_P4 VDD_P4 V 7
VSS - VSS-to-VSS_ANA differential voltage -0.1 0.1 V

VSS_ANA
VDD_USB Supply voltage for USB analog 3.0 3.6 V 8
VIH 3
Input high voltage
• 1.71 V ≤ VDD_Px ≤ 3.6 V 0.7 × VDD_Px — V
• 1.14 V ≤ VDD_Px ≤ 1.32 V 0.7 × VDD_Px

—
VIL 3
Input low voltage
— 0.3 × VDD_Px V
NXP Semiconductors
General
Table 9. Voltage and current operating requirements (continued)
Symbol Description Min. Typ Max. Unit Notes
• 1.71 V ≤ VDD_Px ≤ 3.6 V

— 0.3 x VDD_Px
• 1.14 V ≤ VDD_Px ≤ 1.32 V
VHYS Input hysteresis V

• Slow I/O —
0.1 × VDD_Px
• Medium I/O 0.1 × VDD_Px
• Fast I/O 0.04 × VDD_Px
IICIO 9
IO pin DC injection current — per pin
mA
• VIN < VSS-0.3 V (negative —
current injection) -3
• VIN > VDD+0.3 V (positive +3

—
current injection)
IICcont Contiguous pin DC injection current —

regional limit, includes sum of negative mA
injection currents of 16 contiguous pins
• Negative current injection -25 —
Positive current injection — +25
VODPU Open drain pullup voltage level VDD_Px VDD_Px V 10
1. To avoid triggering the glitch detect modules on this device, it is important that the VDD_CORE voltage matches the
configuration of the GDET modules. See the GDET chapter in the Security Reference Manual for details.
2. If DCDC is unused, then input supply should be tied to GND through a 10 kΩ resistor.
3. Operation at 1.2 V is allowed on Port P2/P3 pins only with the following restrictions:
• VDD_CORE must be less than or equal to the VDD_Px voltage
• VDD_SYS must be powered on before VDD_Px is powered and VDD_SYS must not be powered off before powering
off VDD_Px.
4. If this voltage rail is not tied to VDD, it must ramp after VDD_SYS
5. If none of the Port 3 pins are being used, then the VDD_P3 can be left floating.
6. VDD_P4 should be powered up with VDD_ANA and to the same voltage level as VDD_ANA
7. VDD_ANA may deviate from VDD_P4 by ± 0.1 V provided it is still within range of 1.71 V - 3.6 V
8. USB HS is not supported when VDD_CORE < 1.1 V
9. All I/O pins are internally clamped to VSS and VDD_Px through an ESD protection diode. If VIN is greater than
VDD_Px_MIN(=VSS-0.3 V) or is less than VDD_Px_MAX(=VDD_Px + 0.3 V), then there is no need to provide current limiting
resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R = (-0.3 - VIN)/(-IICIOmin). The positive injection current limiting resistor is
calculated as R=(VIN-VDD_Px_MAX)/IICIOmax. The actual resistor should be an order of magnitude higher to tolerate transient
voltages.
10. Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD_Px as appropriate.
3.2.2 HVD, LVD, and POR operating requirements

The device includes low-voltage detection (LVD) and high-voltage detection (HVD) power supervisor circuits for following
power supplies:
• VDD
• VDD_CORE
NXP Semiconductors
General
• VDD_SYS
For VDD_SYS, it has Power-on-reset (POR) power supervisor circuits.
Table 10. VDD supply HVD, LVD, and POR Operating Requirements
Symbol Description Min. Typ. Max. Unit Notes
VHVDH_VDD VDD Rising high-voltage detect threshold 3.730 3.810 3.890 V

(HVD assertion)
VHVDH_HYS_VDD VDD High-voltage inhibit reset/recover — 38 — mV

hysteresis
VLVDH_VDD VDD Falling low-voltage detect threshold 2.567 2.619 2.673 V

(LVD assertion) - high range
VLVDH_HYS_VDD VDD Low-voltage inhibit reset/recover — 27 — mV

hysteresis - high range
VLVDL_VDD VDD Falling low-voltage detect threshold 1.618 1.651 1.684 V

(LVD assertion) - low range
VLVDV_HYS_VDD VDD Low-voltage inhibit reset/recover — 16 — mV

hysteresis - low range
Table 11. VDD_CORE supply HVD and LVD Operating Requirements
VHVD_CORE VDD_CORE Rising high-voltage detect V 1
threshold (HVD assertion)

Target VDD_CORE = 1.0 V
Target VDD_CORE = 1.1 V 1.230 1.257 1.285
VHVD_HYS_CORE VDD_CORE High-voltage inhibit reset/recover mV 1
hysteresis
— 13 —
VLVD_CORE VDD_CORE Falling low-voltage detect V

threshold (LVD assertion)
Target VDD_CORE = 1.0 V 0.899 0.917 0.936
Target VDD_CORE = 1.1 V 0.989 1.009 1.029
Target VDD_CORE = 1.2 V 1.043 1.064 1.086
VLVD_HYS_CORE VDD_CORE Low-voltage inhibit reset/ mV

recover hysteresis
Target VDD_CORE = 1.0 V — 9 —
NXP Semiconductors
General
1. Same value applies to all conditions.
Table 12. VDD_SYS supply HVD and LVD Operating Requirements
VHVD_SYS V 1
VDD_SYS Rising high-voltage detect
threshold (HVD assertion)
Target VDD_SYS = 1.8 V 2.035 2.077 2.120
VHVD_HYS_SYS VDD_SYS High-voltage inhibit reset/recover — 20 — mV

hysteresis
VPOR_SYS Falling VDD_SYS POR detect voltage (POR 0.8 1.0 1.5 V
assertion)
VLVD_SYS VDD_SYS Falling low-voltage detect V

threshold (LVD assertion)
Target VDD_SYS = 1.8 V 1.616 1.649 1.683
VLVD_HYS_SYS VDD_SYS Low-voltage inhibit reset/recover — 17 — mV

hysteresis
1. When fuses are being programmed VDD_SYS is raised to 2.5V nominal. This is outside the HVD bounds, so HVD
detection for VDD_SYS must be disabled when programming fuses
3.2.3 Voltage and current operating behaviors

Table 13. Voltage and current operating behaviors
VOH 1
Output high voltage — Normal drive strength
VDD_Px – 0.5 — — V
• 2.7 V ≤ VDD_Px ≤ 3.6 V, IOH = 4 mA
• 1.71 V ≤ VDD_Px < 2.7 V, IOH = 2.5 mA VDD_Px – 0.5 — — V
• 1.14 V ≤ VDD_Px < 1.32 V, IOH = 0.5 mA

VDD_Px – 0.5 — — V
VOH 2,1
Output high voltage — High drive strength
VDD_Px – 0.5 — — V
• 2.7 V ≤ VDD_Px ≤ 3.6 V, IOH = 6 mA
• 1.71 V ≤ VDD_Px < 2.7 V, IOH = 3.75 mA VDD_Px – 0.5 — — V
• 1.14 V ≤ VDD_Px < 1.32 V, IOH = 0.75 mA

VDD_Px – 0.5 — — V
IOHT Output high current total for all ports — — 100 mA
VOL 3,1
Output low voltage — Normal drive strength
— — 0.5 V
• 2.7 V ≤ VDD_Px ≤ 3.6 V, IOL = 4 mA
• 1.71 V ≤ VDD_Px < 2.7 V, IOL = 2.5 mA — — 0.5 V
• 1.14 V ≤ VDD_Px < 1.32 V, IOH = 0.5 mA

— — 0.5 V
NXP Semiconductors
General
Table 13. Voltage and current operating behaviors (continued)
VOL 1,3
Output low voltage — High drive strength
— — 0.5 V
• 2.7 V ≤ VDD_Px ≤ 3.6 V, IOL = 6 mA
• 1.71 V ≤ VDD_Px < 2.7 V, IOL = 3.75 mA — — 0.5 V
• 1.14 V ≤ VDD_Px < 1.32 V, IOH = 0.75 mA

— — 0.5 V
IOLT Output low current total for all ports — — 100 mA
IIN Input leakage current (per pin) for full — — 1 μA 4
temperature range
IIN Input leakage current (per pin) at 25 °C — — 0.025 μA 4
IOZ Hi-Z (off-state) leakage current (per pin) — — 1 μA
RPU Internal pullup resistors 33 50 75 kΩ
RPU (I3C) Internal pullup resistors 1.11 1.2 2.83 kΩ 5
RPD Internal pulldown resistors 33 50 75 kΩ
RHPU High-resistance pullup option (PCRx[PV] = 1) 0.67 1.0 1.5 MΩ 6
RHPD High-resistance pulldown option (PCRx[PV] = 0.67 1.0 1.5 MΩ 6
1)
VBG Bandgap voltage reference voltage 0.98 1.0 1.02 V
1. The 1.14 V – 1.32 V range only applies to port P2 / P3 pins.

2. AON and RESET_B pins are always configured in high drive mode
3. Open drain outputs must be pulled to VDD_Px.
4. Measured at VDD_Px = 3.6 V.
5. Only pins with +I3C add-on support this option
6. Only AON pins and RESET_B pin support this option.
3.2.4 On-chip regulator electrical specifications
3.2.4.1 DCDC converter specifications
Table 14. DCDC Converter Specifications
VDD_DCDC DCDC input voltage 1.71 — 3.6 V 1
VDCDC_LX 1, 2
DCDC output voltage
1.2 V range 0.85 — 1.21 V
ILOAD 3
DCDC load current
• Normal drive strength — — 105 mA
• FREQ_CNTRL_ON=1 — — 45 mA
• Low drive strength — — 15 mA
NXP Semiconductors
General
Table 14. DCDC Converter Specifications (continued)
LX DCDC inductor value 0.47 1 2.2 µH 4
ESR External inductor equivalent series resistance — 110 — mΩ 5
COUT DCDC capacitance value 6 22 30 µF 6
VRIPPLE DCDC voltage ripple

— 1 — %
• In normal drive strength
• In low drive strength — 25 — mV
T_startup DCDC startup time — 100 — µs
fburst DCDC switching frequency 3 5 8 MHz 7
fburst_acc DCDC burst frequency accuracy — 10 — % 8
1. The VDD_DCDC input supply to the system DCDC must be at least 500 mV higher than the desired output at DCDC_LX to
achieve the stated efficiency. VDD_DCDC can be as low as 300 mV above the desired output voltage but the efficiency will
be reduced.
2. The system DCDC converter generates 1.2 V at DCDC_LX by default. The DCDC is used to power VDD_CORE.
3. The maximum load current during boot up shall not exceed 60 mA.
4. Recommended inductor value is 1 µH to 1.5 µH. If the inductor is < 1 µH, the DCDC efficiency is not guaranteed.
5. The maximum recommended ESR is 250 mΩ (not a hard limit).
6. The variation in capacitance of the capacitor at DCDC_LX due to aging, temperature, and voltage degradation must not
exceed the Min./Max. values.
7. FREQ_CNTRL_ON = 1. This range is for 1 µH inductor. DCDC converter specifications
8. FREQ_CNTRL_ON = 1.
NXP Semiconductors
General
3.2.4.2 DCDC efficiency plots
Figure 3. Low drive strength
NXP Semiconductors
General
Figure 4. Normal drive strength
3.2.4.3 LDO_SYS electrical specifications
Table 15. LDO_SYS electrical specifications
VDD_LDO_SYS LDO_SYS input supply voltage — V 1,2

1.95 3.6
• Normal Drive mode
• Passthrough mode 1.86 1.98
• Fuse Programming 2.75 3.6
VOUT_SYS V 3,4,2
LDO_SYS regulator output voltage
1.71 1.8 1.98
Normal drive strength mode
2.25 2.5 2.75
Fuse programming mode
NXP Semiconductors
General
Table 15. LDO_SYS electrical specifications (continued)
LDO_SYS_DROPO mV 1, 2
LDO_SYS dropout voltage
UT
• Normal drive strength mode — — 150
• Fuse programming mode 5 — — 500
• Pass through mode 6 — — 60
ILOAD LDO_SYS maximum load current

• Normal drive strength mode — — 50
• Low drive strength mode — — 2
• Fuse programming mode — — 40 mA
IDD 7
LDO_SYS power consumption
• Normal drive strength mode — 100 — μA
• Low drive strength mode — 70 — nA
COUT External output capacitor 1.4 2.2 4.0 μF
ESR External output capacitor equivalent series — 30 — mΩ

resistance
IINRUSH LDO_SYS inrush current — — 1008 mA
1. Regulator will automatically switch to passthrough mode with the supply is below 1.95 V.
2. VDD_LDO_SYS must be at least 150 mV higher than the desired VOUT_SYS.
3. The LDO_SYS converter generates 1.8 V by default at VOUT_SYS. VOUT_SYS can be used to power VDD_SYS,
VDD_Px, VDD_ANA, and external components as long as the max ILOAD is not exceeded.
4. VOUT_SYS and VDD_SYS are connected together within the package
5. Maximum current load in fuse programming mode is 40 mA
6. Maximum current load during pass through mode = 50 mA
7. In normal mode, LDO_SYS draws ~100 μA for every 20 mA of load current.
8. This value is for a 1.5 μF external output capacitor. This value would increase with higher load capacitor.
3.2.4.4 LDO_CORE electrical specifications
Table 16. LDO_CORE electrical specifications
VDD_LDO_C LDO_CORE input supply voltage 1.71 — 3.6 V 1
ORE
VOUT_CORE LDO_CORE regulator output voltage V 2
• Normal drive strength

— Mid drive
0.95 1 1.05
— Normal drive
1.045 1.1 1.155
— Over drive
1.14 1.2 1.26
• Low drive strength
NXP Semiconductors
General
Table 16. LDO_CORE electrical specifications (continued)
— Mid drive
0.95 1 1.05
— Normal drive
1.045 1.1 1.155
ILOAD LDO_CORE max load current

• Normal drive strength
— Tj = -40 °C
— — 90
— Tj = 27 °C
— — 100
— Tj = 113 °C
— — 115
• Low drive strength
— -40 °C <Tj < 113°C — — 28 mA
IINRUSH LDO_CORE inrush current — — 500 mA 3
1. To bypass LDO_CORE, tie VDD_LDO_CORE to VDD_CORE

2. VOUT_CORE and VDD_CORE are connected together in package
3. This value is for 4.7 µF external output capacitor. This value would increase with higher load capacitor
Table 17. LDO_CORE external device electrical specifications
COUT External output capacitor 3.7 4.7 10 μF
CDEC External output decoupling capacitor — 0.1 — μF
ESR External output capacitor equivalent series — 10 — mΩ

resistance
3.2.5 Power mode transition operating behaviors

All specifications in the following table assume this clock configuration:
• CPU clock = 48 MHz
• AHB clock = 48 MHz
• Clock source = FIRC
All specifications in the following table were measured fron the initiation of an external pin event to the execution code (unless
otherwise stated)
All specifications in the following table assume this SPC configuration:
• SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x00 and the Core voltage level is configured for the same level in
active and low power mode (SPC->ACTIVE_CFG[DCDC_VDD_LVL] = SPC->ACTIVE_CFG[CORELDO_VDD_LVL] =
SPC->LP_CFG[DCDC_VDD_LVL] = SPC->LP_CFG[CORELDO_VDD_LVL]).
NXP Semiconductors
General
Table 18. Power mode transition operating behaviors
tPOR After a POR event, amount of time to execution — 6.5 — ms 1, 2, 3
of the first instruction (measured from the point

where VDD and VDD_SYS reach 1.8V) across
the operating temperature range of the chip.
tSLEEP SLEEP → ACTIVE — 0.22 — μs 3, 4
tDSLEEP DEEP SLEEP → ACTIVE — 8.7 — μs 3, 4
tPWDN POWER DOWN → ACTIVE — 9.8 — μs 3, 4
tDPWDN Deep Power DOWN → ACTIVE — 5.3 — ms 1, 4, 2, 3
1. Boot configuration 144 MHz

2. Measured using ROM version v4.0
3. Based on characterization of typical units. Not tested in production
4. WFE used for low-power mode entry
3.2.6 Power consumption operating behaviors

The MCXNx4x device has multiple power supplies that can be connected in different configurations, where the total current
consumption of the device is the accumulative result of each individual power supply's current consumption. The Core domain is
provided by the noted source (either DCDC or LDO), the voltage for the System domain is provided by the LDO-SYS (except for
LDO @ 1.8V), voltage for the I/O rails is provided by the same external source powering the Core domain regulator and System
domain regulator, and the VBAT domain is also provided by the same external source.
When calculating the total MCU current consumption the following considerations should be made:
• Specifications below only include power for the MCU itself
• VDD_USB current draw are not included
• On top of the device’s IDD current consumption, external loads applied to pins of the device need to be considered
• Efficiency of regulators (on-chip or off-chip) used to generate supply voltages should be considered
3.2.6.1 Power Consumption Operating Behaviors

Appendix A: Active IDD
NOTE
Refer to Thermal specifications for formula to calculate Ta from Tj
Table 19. DCDC @ 3.3 V
Single Core, Flash, LPCAC cases
Symbol Description Temperature, Typ Units Notes

Tj (°C)
IDD_ACT_OD_1 While(1) executing on CPU0 from Flash; Cache Enabled, Core 25 11.17 mA 1
voltage at 1.2V; Clocked from PLL0 at 150 MHz; All peripheral

113 21.61
clocks disabled
IDD_ACT_SD_1 While(1) executing on CPU0 from Flash; Cache Enabled, Core 25 7.19 mA 1

113 15.14
clocks disabled
125 23.81
NXP Semiconductors
General
Table 19. DCDC @ 3.3 V (continued)

Tj (°C)
IDD_ACT_MD_1 While(1) executing on CPU0 from Flash; Cache Enabled, 25 3.28 mA 1
Core voltage at 1.0V; Clocked from the FIRC at 48 MHz; All

113 9.37
peripheral clocks disabled
125 15.85
IDD_ACT_LP_1 While(1) executing on CPU0 from Flash; Cache Enabled, 25 0.97 mA 1
Core voltage at 1.0V; Clocked from the SIRC at 12 MHz; All

113 7.32
125 10.0
IDD_CM_OD_1 CoreMark executing on CPU0 from Flash; Cache Enabled, 25 12.47 mA 1
Core voltage at 1.2V; Clocked from PLL0 at 150 MHz; All

113 23.38
IDD_CM_SD_1 CoreMark executing on CPU0 from Flash; Cache Enabled, 25 7.92 mA 1

113 16.26
125 24.91
IDD_CM_MD_1 CoreMark executing on CPU0 from Flash; Cache Enabled, 25 3.52 mA 1

113 9.77
125 16.37
IDD_CM_LP_1 CoreMark executing on CPU0 from Flash; Cache Enabled, 25 1.01 mA 1

113 7.30
125 9.71
IDD_ACT_OD_2 While(1) executing on CPU0 from Flash; Cache Enabled, Core 25 31.61 mA 1

113 42.87
clocks enabled
IDD_ACT_SD_2 While(1) executing on CPU0 from Flash; Cache Enabled, Core 25 18.52 mA 1
113 26.99
clocks enabled
125 35.82

113 14.08
peripheral clocks enabled
125 20.82

113 8.36
125 10.85

113 43.98
NXP Semiconductors
General

Tj (°C)

113 27.61
125 37.52

113 14.28
125 21.48

113 8.42
125 10.67
NOTE
Table 20. LDO @ 1.8 V

Tj (°C)
IDD_ACT_OD_1 While(1) executing on CPU0 from Flash; Cache Enabled, 25 21.84 mA 1

113 46.50
IDD_ACT_SD_1 While(1) executing on CPU0 from Flash; Cache Enabled, 25 14.16 mA 1

113 34.12
125 45.69

113 22.93
125 32.56

113 17.99
125 27.41

113 50.94
NXP Semiconductors
General
Table 20. LDO @ 1.8 V (continued)

Tj (°C)

113 36.79
125 48.64

113 23.97
125 33.80

113 18.24
125 27.69

113 94.91

113 62.99
125 73.41

113 35.29
125 44.44

113 21.0
125 30.35

113 96.97

113 64.41
125 76.28

113 35.83
125 45.56

113 21.16
NXP Semiconductors
General

Tj (°C)
125 30.59
Dual Core, Flash, LPCAC cases
IDD_ACT_OD_3 While(1) executing on CPU0 from Flash; While(1) executing 25 30.57 mA 1
on CPU1 from RAM; Cache Enabled, Core voltage at

113 55.62
1.2V; Clocked from PLL0 at 150 MHz; All peripheral clocks
disabled
IDD_ACT_SD_3 While(1) executing on CPU0 from Flash; While(1) executing 25 19.46 mA 1
on CPU1 from RAM; Cache Enabled, Core voltage at

113 39.57
1.1V; Clocked from PLL0 at 100 MHz; All peripheral clocks
disabled 125 51.16
IDD_ACT_MD_3 While(1) executing on CPU0 from Flash; While(1) executing 25 9.08 mA 1
on CPU1 from RAM; Cache Enabled, Core voltage at 1.0V;

113 25.25
Clocked from the FIRC at 48 MHz; All peripheral clocks
disabled 125 34.92
IDD_ACT_LP_3 While(1) executing on CPU0 from Flash; While(1) executing 25 2.73 mA 1
on CPU1 from RAM; Cache Enabled, Core voltage at 1.0V;

113 18.57
Clocked from the SIRC at 12 MHz; All peripheral clocks
disabled 125 27.99
IDD_CM_OD_3 CoreMark executing on CPU0 from Flash; CoreMark 25 38.22 mA 1
executing on CPU1 from RAM; Cache Enabled, Core

113 63.19
voltage at 1.2V; Clocked from PLL0 at 150 MHz; All
IDD_CM_SD_3 CoreMark executing on CPU0 from Flash; CoreMark 25 23.95 mA 1

113 44.14
peripheral clocks disabled 125 56.06
IDD_CM_MD_3 CoreMark executing on CPU0 from Flash; CoreMark 25 10.82 mA 1

113 27.12
voltage at 1.0V; Clocked from the FIRC at 48 MHz; All
IDD_CM_LP_3 CoreMark executing on CPU0 from Flash; CoreMark 25 3.15 mA 1

113 19.03
voltage at 1.0V; Clocked from the SIRC at 12 MHz; All
Single Core, RAM w Cache cases
IDD_CM_OD_5 While(1) executing on CPU0 from RAM; Cache Enabled; 25 28.34 mA 1

113 52.41
NXP Semiconductors
General

Tj (°C)
IDD_CM_SD_5 While(1) executing on CPU0 from RAM; Cache Enabled; 25 18.18 mA 1

113 37.87
125 49.81
IDD_CM_MD_5 While(1) executing on CPU0 from RAM; Cache Enabled; 25 8.45 mA 1

113 24.59
125 34.29
IDD_CM_LP_5 While(1) executing on CPU0 from RAM; Cache Enabled 25 2.57 mA 1
RAM Core voltage at 1.0V; Clocked from the SIRC at 12

113 18.39
MHz; All peripheral clocks disabled
125 27.84
NOTE
Table 21. LDO @ 3.3V
Symbol Description Temperature, Tj Typ Units Notes

(°C)

113 46.99

113 34.44
125 23.81
Core voltage at 1.0V; Clocked from the FIRC at 48 MHz;

113 23.15
All peripheral clocks disabled
125 38.56
Core voltage at 1.0V; Clocked from the SIRC at 12 MHz;

113 13.54
125 20.35
IDD_CM_OD_1 CoreMark executing on CPU0 from Flash; Cache 25 26.47 mA 1
Enabled, Core voltage at 1.2V; Clocked from PLL0 at 150

113 51.47
IDD_CM_SD_1 CoreMark executing on CPU0 from Flash; Cache 25 16.90 mA 1

113 37.13
NXP Semiconductors
General
Table 21. LDO @ 3.3V (continued)

(°C)
125 56.23
IDD_CM_MD_1 CoreMark executing on CPU0 from Flash; Cache 25 7.84 mA 1
Enabled, Core voltage at 1.0V; Clocked from the FIRC

113 24.20
at 48 MHz; All peripheral clocks disabled
125 39.59
IDD_CM_LP_1 CoreMark executing on CPU0 from Flash; Cache 25 2.12 mA 1
Enabled, Core voltage at 1.0V; Clocked from the SIRC

113 13.81
125 20.57

113 95.60

113 63.61
125 82.99

113 35.59
All peripheral clocks enabled
125 51.05
Core voltage at 1.0V; Clocked from the SIRC at 12 MHz;

113 16.61
All peripheral clocks enabled
125 23.37

113 97.84
MHz; All peripheral clocks enabled

113 64.97
MHz; All peripheral clocks enabled
125 82.66
Enabled, Core voltage at 1.0V; Clocked from the FIRC

113 36.12
at 48 MHz; All peripheral clocks enabled
125 52.08
IDD_CM_LP_2 CoreMark executing on CPU0 from Flash; Cache 25 5.06 mA 1
Enabled, Core voltage at 1.0V; Clocked from the SIRC

113 16.76
at 12 MHz; All peripheral clocks enabled
125 23.53
Dual Core, Flash, LPCAC cases
NXP Semiconductors
General

(°C)
IDD_ACT_OD_3 While(1) executing on CPU0 from Flash; While(1) 25 31.01 mA 1

113 56.16
IDD_ACT_SD_3 While(1) executing on CPU0 from Flash; While(1) 25 19.81 mA 1

113 39.92
IDD_ACT_MD_3 While(1) executing on CPU0 from Flash; While(1) 25 9.27 mA 1

113 25.46
voltage at 1.0V; Clocked from FIRC at 48 MHz; All
IDD_ACT_LP_3 While(1) executing on CPU0 from Flash; While(1) 25 2.41 mA 1

113 14.11
IDD_CM_OD_3 CoreMark executing on CPU0 from Flash; CoreMark 25 38.32 mA 1

113 63.84
IDD_CM_SD_3 CoreMark executing on CPU0 from Flash; CoreMark 25 24.07 mA 1

113 44.53
IDD_CM_MD_3 CoreMark executing on CPU0 from Flash; CoreMark 25 10.93 mA 1

113 27.35
voltage at 1.0V; Clocked from FIRC at 48 MHz; All
IDD_CM_LP_3 CoreMark executing on CPU0 from Flash; CoreMark 25 2.88 mA 1

113 14.61
Single Core, RAM w Cache cases
IDD_CM_OD_5 While(1) executing on CPU0 from RAM; Cache Enabled; 25 25.28 mA 1

113 52.94
IDD_CM_SD_5 While(1) executing on CPU0 from RAM; Cache Enabled; 25 16.33 mA 1

113 38.22
125 50.58
NXP Semiconductors
General

(°C)
IDD_CM_MD_5 While(1) executing on CPU0 from RAM; Cache Enabled; 25 7.71 mA 1

113 24.81
125 35.64
IDD_CM_LP_5 While(1) executing on CPU0 from RAM; Cache Enabled 25 2.35 mA 1
RAM Core voltage at 1.0V; Clocked from the SIRC at 12

113 13.98
125 20.75
Single Core, Flash w/o LPCAC cases
Disabled; Core voltage at 1.2V; Clocked from PLL0 at

113 52.91
150 MHz; All peripheral clocks disabled
Disabled; Core voltage at 1.1V; Clocked from PLL0 at

113 37.94
100 MHz; All peripheral clocks disabled
125 57.00
Disabled; Core voltage at 1.0V; Clocked from the FIRC

113 24.53
125 39.89
Appendix B: Static IDD
NOTE
Table 22. DCDC @ 3.3 V
Symbol Description Temperatur Typ Unit Notes

e, Tj (°C) s
IDD_SLEEP Core_Main in Sleep; Core_Wake in Sleep; IVS 25 2.21 mA 1
disabled; All RAM retained; Core voltage at 1.0V;

113 8.17
Core clocked at 48MHz by FIRC; All regulators in
Normal mode 125 15.19
IDD_SLEEP_LP Core_Main in Sleep; Core_Wake in Sleep; IVS 25 1.85 mA 1
disabled; All RAM retained; Core voltage at

113 7.94
1.0V; Core clocked at 48MHz by FIRC; Core
regulator in low power mode, System regulator 125 14.54
in Normal mode
IDD_DSLEEP_OD Core_Main in Deep Sleep; Core_Wake in Deep 25 1.18 mA 1
Sleep; IVS disabled; All HVD/LVD enabled; Core

113 10.65
NXP Semiconductors
General

e, Tj (°C) s
voltage at 1.2V; All RAM retained; All regulators in

Normal mode
IDD_DSLEEP_MD Core_Main in Deep Sleep; Core_Wake in Deep 25 0.82 mA 1

113 6.30
IDD_DSLEEP_IVS Core_Main in Deep Sleep; Core_Wake in Deep 25 0.82 mA 1
Sleep; IVS enabled; All HVD/LVD disabled; Core

113 6.26
IDD_DSLEEP_LP Core_Main in Deep Sleep; Core_Wake in Deep 25 0.27 mA 1
Sleep; IVS enabled; All HVD/LVD disabled; All

113 5.79
RAM retained; Core voltage at 1.0V; All Regulators
in low power mode 125 11.30
IDD_PDOWN_64K Core_Main in Power Down; Core_Wake in Power 25 2.78 µA 1
Down; IVS enabled; All HVD/LVD disabled; 64KB

113 53.88
RAM retained; Core voltage at 1.0V; All regulators

113 64.66
IDD_PDOWN_OD Core_Main in Power Down; Core_Wake in Power 25 556.53 µA 1
Down; IVS disabled; All HVD/LVD enabled; Core

113 649.47
voltage at 1.2V; No RAM retained; All regulators in
Normal mode
IDD_PDOWN_MD Core_Main in Power Down; Core_Wake in Power 25 549.71 µA 1

113 626.97
IDD_PDOWN_IVS Core_Main in Power Down; Core_Wake in Power 25 547.09 µA 1
Down; IVS enabled; All HVD/LVD enabled; Core

113 614.44
IDD_PDOWN_RET_0V7 Core_Main in Power Down; Core_Wake in Power 25 4.18 µA 1
Down; IVS disabled; All HVD/LVD disabled; Core

113 116.13
low power mode 125 197.77
IDD_DPDOWN_0 Core_Main in Deep Power Down; Core_Wake 25 131.73 µA 1
in Deep Power Down; IVS powered down; All

113 155.72
HVD/LVD enabled; No RAM retained; DCDC
NXP Semiconductors
General

e, Tj (°C) s
output disabled; Core regulator in low power 125 170.88

mode, System regulator in Normal mode
IDD_DPDOWN_LP Core_Main in Deep Power Down; Core_Wake 25 1.22 µA 1

113 20.09
output disabled; All regulators in low power mode 125 25.88
IDD_DPDOWN_OSC32K Core_Main in Deep Power Down; Core_Wake 25 1.63 µA 1

113 20.55
output disabled; All regulators in low power mode; 125 26.36
OSC32K enabled
IDD_DPDOWN_FRO16K Core_Main in Deep Power Down; Core_Wake 25 0.92 µA 1

in Deep Power Down; IVS powered down;
113 19.64
All HVD/LVD enabled; No RAM retained; All
regulators in low power mode; FRO16K enabled 125 33.52
IDD_DPDOWN_32K Core_Main in Deep Power Down; Core_Wake 25 1.80 µA 1
in Deep Power Down; IVS powered down;

113 38.16
All HVD/LVD enabled; No RAM retained; All
regulators in low power mode; 32KB VBAT 125 49.32
SRAM retained
IDD_VBAT_0 VBAT mode; DCDC output disabled 25 0.23 µA 1,2
113 4.82
125 6.15
IDD_VBAT_TAMPER VBAT mode; DCDC output disabled; TAMPER 25 0.34 µA 1,2
pins enabled
113 4.93
125 6.19
IDD_VBAT_32K VBAT mode; DCDC output disabled; 32KB VBAT 25 0.81 µA 1,2
SRAM retained
113 22.62
125 29.05
IDD_VBAT_8K VBAT mode; DCDC output disabled; 8KB VBAT 25 0.49 µA 1,2
SRAM retained
113 9.51
125 12.18
IDD_VBAT_OSC32K VBAT mode; DCDC output disabled; RTC enabled 25 0.62 µA 1,2
and clocked from OSC32K

113 5.24
125 6.57
NXP Semiconductors
General

e, Tj (°C) s
IDD_VBAT_FRO16K VBAT mode; DCDC output disabled; RTC enabled 25 0.59 µA 1,2
and clocked from FRO16K

113 5.19
125 8.43

2. Power measurements for IDD_VBATx symbols are attained after turning off external power supplies to all domains,
except VDD_BAT
NOTE
Symbol Description Temperature, Tj Typ Units Note

(°C) s

113 20.01

113 19.57
Core clocked at 48MHz by FIRC; Core regulator in
low power mode, System regulator in Normal mode 125 28.97

113 22.48
Normal mode

113 15.02
Sleep; IVS enabled; All HVD/LVD disabled; Core

113 14.91
Sleep; IVS enabled; All HVD/LVD disabled; All RAM

113 14.41
retained; Core voltage at 1.0V; All Regulators in low
power mode 125 22.66
IDD_PDOWN_LP Core_Main in Power Down; Core_Wake in Power 25 3.73 µA 1
Down; IVS enabled; All HVD/LVD disabled; No RAM

113 87.67
retained; Core voltage at 1.0V; All regulators in low
NXP Semiconductors
General
Symbol Description Temperature, Tj Typ Units Note

(°C) s
IDD_PDOWN_WK Core_Main in Power Down; Core_Wake in Deep 25 75.40 µA 1
Sleep; IVS enabled; All HVD/LVD disabled; No RAM

113 789.81

113 102.79
RAM retained; Core voltage at 1.0V; All regulators in

113 117.78

113 148.36

113 382.58
Normal mode

113 340.41

113 306.33
NOTE

Tj (°C)

113 20.17

113 15.31
Core clocked at 48MHz by FIRC; Core regulator in
low power mode, System regulator in Normal mode 125 22.08
NXP Semiconductors
General

Tj (°C)

113 22.65
Normal mode

113 15.15

113 15.02
retained;
125 27.40
Sleep; IVS enabled; All HVD/LVD disabled; All RAM

113 10.54
retained; Core voltage at 1.0V; All Regulators in low

113 491.77
Normal mode

113 449.50

113 415.05
IDD_PDOWN_LP Core_Main in Power Down; Core_Wake in Power 25 4.08 µA 1
Down; IVS enabled; All HVD/LVD disabled; No RAM

113 76.88
IDD_PDOWN_WK_DS Core_Main in Power Down; Core_Wake in Deep 25 58.22 µA 1

113 624.83

113 89.97

113 100.57
NXP Semiconductors
General

Tj (°C)
RAM retained; Core voltage at 1.0V; All regulators 125 193.27

in low power mode

113 122.43
3.2.7 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.
3.2.8 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions:
1. Go to nxp.com.
2. Perform a keyword search for “EMC design”.
3.2.9 Capacitance attributes

Table 25. Capacitance attributes
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
3.3 Switching specifications
3.3.1 Device clock specifications

Table 26. Device clock specifications
fLPTMR LPTMR clock — 25 MHz
Overdrive mode
fCPU CPU clock (CPU_CLK) — 150 MHz 1
fAHB AHB clock (AHB_CLK) — 150 MHz
fSLOW Slow clock (SLOW_CLK) — 37.5 MHz
Standard Drive mode
fCPU CPU clock (CPU_CLK) — 100 MHz
fSLOW Slow clock (SLOW_CLK) — 25 MHz
NXP Semiconductors
General
Table 26. Device clock specifications (continued)
Mid-Drive mode
fCPU CPU clock (CPU_CLK) — 50 MHz
fSLOW Slow clock (SLOW_CLK) — 12.5 MHz
1. The maximum value of system clock, core clock, AHB clock, and flash clock under normal run mode can be 3 % higher
than the specified maximum frequency when FRO-144M is used as the clock source.
3.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO, LPUART, LPTMR, TPM, CAN, LPI2C, LPI3C,
LPSPI, or FlexIO functions.
NOTE
Pad types are specified in the pinout spreadsheet attached to this document.
Table 27. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) — 1.5 — AHB clock 1
Synchronous path cycles
GPIO pin interrupt pulse width (digital glitch filter disabled, 150 — ns 2
analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter disabled, 50 — ns

analog filter disabled) — Asynchronous path
AON pins and RESET_B pin interrupt pulse width — 330 — ns 3
Asynchronous path
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 3
Port rise/fall time

4
Slow I/O pins ns
• 2.7 ≤ VDD_Px ≤ 3.6 V
— Fast slew rate (SRE = 0; DSE = 0) 2.5 7
— Slow slew rate (SRE = 1; DSE = 0) 4.6 15
• 1.71 ≤ VDD_Px < 2.7 V

— Fast slew rate (SRE = 0; DSE = 1) 1.6 7
— Slow slew rate (SRE = 1; DSE = 1) 4.3 20
7,8
Fast I/O pins
• 2.7 ≤ VDD_Px ≤ 3.6 V
0.8 2 ns
0.9 2.5
NXP Semiconductors
General
Table 27. General switching specifications (continued)
Description Min. Max. Unit Notes
— Fast slew rate (SRE = 0; DSE = 0)5

0.5 2
— Slow slew rate (SRE = 1; DSE = 0)5
0.6 2.5
• 1.71 ≤ VDD_Px < 2.7 V
2 7
2 8
• 1.14 ≤ VDD_Px < 1.32 V
4
Medium I/O pins
• 2.7 ≤ VDD_Px ≤ 3.6 V 1.500 3.322 ns
— Fast slew rate (SRE = 0; DSE = 0) 2.071 4.864
— Slow slew rate (SRE = 1; DSE = 0)
• 1.71 ≤ VDD_Px < 2.7 V
— Fast slew rate (SRE = 0; DSE = 1) 1.105 3.536
— Slow slew rate (SRE = 1; DSE = 1) 1.815 6.173
9
AON pins and RESET_B pin
ns
• 2.7 ≤ VDD_Px ≤ 3.6 V
3 8
• 1.71 ≤ VDD_Px < 2.7 V
3.6 20
1. The synchronous and asynchronous timing must be met.

2. This only applies to pins with the "+I2C" add-on
3. This is the shortest pulse that is guaranteed to be recognized.
4. Load is 25 pF. Drive strength and slew rate are configured using PORTx_PCRn[DSE] and PORTx_PCRn[SRE].
5. 15 pF lumped load.
6. 25 pF lumped load
7. These are Port 3 and Port 2 pins.
8. Uses default configuration for NCAL and PCAL in PORTS.
9. Load is 25 pF.
3.4 Thermal specifications
3.4.1 Thermal operating requirements

Table 28. Thermal operating requirements
Symbol Description Min. Typical Max. Unit Notes
TA Ambient temperature –40 25 125 °C 1
TJ Die junction temperature maximum – – 125 °C 2,3, 4,5
1. The device may operate at maximum TA rating as long as TJ maximum of 125 °C is not exceeded. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
2. The device operating specification is not guaranteed beyond 125 °C TJ.
NXP Semiconductors
Peripheral operating requirements and behaviors
3. The maximum operating requirement applies to all chapters unless otherwise specifically stated.
4. Operating at maximum conditions for extended periods may affect device reliability. Refer to Product Lifetime Usage
application note (AN14180)
5. Over-drive mode, at 1.2 V, is not supported above TJ 113 °C.
3.4.2 Thermal attributes

Table 29. Thermal attributes
Board type1 Symbol Description 100 184 BGA Unit Notes

HLQFP
2s2p RθJA Junction to Ambient Thermal resistance, 22.8 35 °C/W 2
1s RθJC Thermal resistance, junction to case 1.1 — °C/W 3
2s2p ΨJT Junction to top of package Thermal 0.4 0.2 °C/W 2
characterization parameter
1. Thermal test board meets JEDEC specification for respective package (JESD51-7 for the 100 HLQFP; JESD51-9 for the
184 BGA)
2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
3. Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the 100
HLQFP package bottom surface temperature.
4 Peripheral operating requirements and behaviors
4.1 Core modules
4.1.1 Debug trace timing specifications

Table 30. Debug trace operating behaviors
Frequency of operation MHz

• OD mode — 48
• SD mode — 36
• MD mode — 25
T1 Clock period ns
• OD mode 20.82 —
• SD mode 27.78 —
• MD mode 40 —
T2 Low pulse width 2 — ns
T3 High pulse width 2 — ns
T4 Clock and data rise time — 3 ns
T5 Clock and data fall time — 3 ns
NXP Semiconductors
Table 30. Debug trace operating behaviors (continued)
T6 Data setup 1.5 — ns
T7 Data hold 1.0 — ns
TRACE_CLK
T4 T5
T3 T2
T1
Figure 5. TRACE_CLKOUT specifications
TRACE_CLK
T6 T7
TRACE_DATA[3:0]
Figure 6. Trace data specifications
4.1.2 JTAG electricals

Table 31. JTAG timing (full voltage range)
Operating voltage 1.71 3.6 V
J1 TCLK frequency of operation

• Boundary Scan — 10 MHz
• JTAG-DP/TAP (OD and SD mode) — 25 MHz
• JTAG-DP/TAP (MD mode)
— 20 MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width

• Boundary Scan 50 — ns
• JTAG-DP/TAP 25 — ns
J4 TCLK rise and fall times — 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 2 — ns
NXP Semiconductors
Table 31. JTAG timing (full voltage range) (continued)
J7 TCLK low to boundary scan output data valid — 30 ns
J8 TCLK low to boundary scan output high-Z — 25 ns
J9 JTAG-DP/TAP TMS, TDI input data setup time to TCLK rise 8 — ns
J10 JTAG-DP/TAP TMS, TDI input data hold time after TCLK rise 1 — ns
J11 TCLK low to JTAG-DP/TAP TDO data valid — 19 ns
J12 TCLK low to JTAG-DP/TAP TDO high-Z — 17 ns
J2
J3 J3
JTAG_TCLK
J4 J4
Figure 7. Test clock input timing
JTAG_TCLK
J5 J6
JTAG_TDI/TMS Input data valid
J7
JTAG_TDO Output data valid
J8
JTAG_TDO
Figure 8. Boundary scan (JTAG) timing
NXP Semiconductors
JTAG_TCLK
J9 J10
JTAG_TDI/TMS Input data valid
J11
JTAG_TDO Output data valid
J12
JTAG_TDO
Figure 9. JTAG-DP/TAP timing
4.1.3 SWD electricals

Table 32. SWD timing
S1 SWD_CLK frequency of operation — 25 MHz
S2 SWD_CLK cycle period 1/S1 — ns
S3 SWD_CLK clock pulse width 20 — ns
S4 SWD_CLK rise and fall times — 3 ns
S5 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
S6 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
S7 SWD_CLK high to SWD_DIO data valid — 25 ns
S8 SWD_CLK high to SWD_DIO high-Z 5 — ns
S2
S3 S3
SWD_CLK
S4 S4
Figure 10. Serial wire clock input timing
NXP Semiconductors
SWD_CLK
S5 S6
SWD_DIO Input data valid
S7
SWD_DIO Output data valid
S8
SWD_DIO
Figure 11. Serial wire data timing
4.2 Clock modules
4.2.1 Reference Oscillator Specification
This chip is designed to meet targeted specifications with a ±40 ppm frequency error over the life of the part, which includes the
temperature, mechanical, and aging excursions.
The table below shows typical specifications for the Crystal Oscillator.
Table 33. System Crystal Oscillator Specification
Symbol Characteristic Min. Typ. Max. Unit Notes
fosc Crystal Frequency 16 — 50 MHz
Tol Frequency tolerance — ±10 ±40 ppm
Jitosc Jitter ps
— 70 —
• Period jitter (RMS)
Vpp Peak-to-peak amplitude of oscillation — 0.6 — V 1
fec Externally provided input clock frequency 0 — 50 MHz 2
tDC_EXTAL External clock duty cycle 40 50 60 %
Vec Externally provided input clock amplitude Refer to Table 9 for VIH and VILlevels 2
1. When a crystal is being used with the oscillator, the EXTAL and XTAL pins should only be connected to required oscillator
components and must not be connected to any other devices.
2. This specification is for an externally supplied clock driven to EXTAL and does not apply to any other clock input.
NXP Semiconductors
Table 34. System Oscillator Crystal Specifications. Refer to figure 10 for additional details of the crystal parameters
Freq Rm(ohms) Cp(pF) Cload(pF) Cm(pF) Lm(mH) Typical Typical Drive level (µW)
Crystal startup Current
min max
(MHz) (µs)1 consumpti
on (µA)1
16 80 2.00 8.00 0.008 12.37 215 168.3 16 22
16 200 1.00 8.00 0.008 12.37 186 200.4 31 46
24 80 0.80 8.00 0.008 5.50 61.4 219.2 43 59
25 60 3.00 11.0 0.008 5.07 224 245.6 70 93
25 60 2.00 10.0 0.008 5.07 128 232.5 61 80
25 100 1.00 8.00 0.008 5.07 73.6 232.7 62 82
32 60 3.00 9.00 0.008 3.09 233 269.6 71 95
32 60 2.00 8.00 0.008 3.09 116 253.2 59 80
32 100 1.00 8.00 0.008 3.09 52.4 289.3 91 123
40 50 2.00 8.00 0.008 1.98 80.4 296.9 73 99
40 60 3.00 9.00 0.008 1.98 162 333.2 99 135
48 50 2.00 8.00 0.008 1.37 73.1 359.6 104 140
48 60 3.00 9.00 0.008 1.37 155 407.9 138 188
1. This is based on simulation
NXP Semiconductors
Lm Cm Rm
Cp
Cload
Figure 12. Crystal Electrical Block Diagram
4.2.2 32 kHz oscillator electrical specifications

Table 35. 32 kHz oscillator electrical specifications
fosc_32k Crystal frequency — 32.768 — kHz
Tol Frequency tolerance ppm 1
• Normal/Start up mode — ±100 —
• Low power mode — ±150 —
Jitosc Jitter ps
• Period jitter (RMS) — 12000 —
• Accumulated jitter over 1 ms (RMS) — 8000 —
ESR Crystal equivalent series resistance kΩ

• Normal mode — — 100 K
• Low power mode — — 50 K
RF Internal feedback resistor — 100 — MΩ
Cpara Parasitic capacitance of EXTAL32 and XTAL32 — 2.5 — pF
tstart Crystal start-up time ms 2

— 1000
NXP Semiconductors
Table 35. 32 kHz oscillator electrical specifications (continued)
• Normal/Start up mode — 8000

• Low power mode
IOSC_32k Current consumption

• ON mode
— Normal mode — 220 —
— Low power mode — 110 —
• OFF mode — 0.5 — nA
Vpp Peak-to-peak amplitude of oscillation V 3
• Normal mode — 0.2 —
• Low power mode — 0.1 —
fec_extal32 Externally provided input clock frequency — 32.768 — kHz 4
tDC_EXTAL3 External clock duty cycle 40 50 60 kHz

2
vec_extal32 Externally provided input clock amplitude Refer to Voltage and current mV 4, 5
operating requirements for VIH and

VIL levels
Cextal/xtal On-chip EXTAL, XTAL Load Capacitance 0 — 30 pF 6,7
1. For Low power mode, use crystals with load cap (CL) 7 pF or less
2. Proper PC board layout procedures must be followed to achieve specifications.
3. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
4. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
5. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VDD_BAT.
6. These are the internally available oscillator load capacitors on each of the EXTAL32 and XTAL32 pins, selectable in 2 pF
steps. The effective load capacitance is the series equivalent of the selected capacitors.
7. The internally available load capacitors can be set to minimum of 0 on XTAL and 2 pF on EXTAL and external load
capacitors used instead.
Table 36. 32 kHz oscillation gain setting
Coarse_Amp_G Max ESR (kΩ) Max Cx (pF) 1 Notes

ain
00 (default) 50 14
01 70 22
10 80 22
11 100 20
1. Cx is the sum of all capacitance connected to both EXTAL32 and XTAL, including internal load capacitors, pad
capacitance and PCB
NXP Semiconductors
NOTE
It is recommended that the oscillator margin be measured on the actual application PCB with the target crystal.
4.2.3 Free-running oscillator FRO-144M specifications

Table 37. FRO-144M specifications
ffro144m FRO-144M frequency (nominal) 144 MHz
Δffro144m Frequency deviation

• Open loop
— — ±2 %
— -20 °C to 85 °C Tj
— — ±3 %
— -40 °C to 125 °C Tj
— — ±0.25 %
• Closed loop (using accurate clock source as
reference)
tstartup Start-up time

• Oscillation time with initial accuracy of -20 % — 2 — μs
to +2 % of enable signal assertion
— 20 — μs
• Oscillation time within +/- 2 % from enable
signal assertion
fos Frequency overshoot during startup — — 2 %
jitper • Period jitter RMS 1 — 200 — ps
• Accumulated jitter over 1 ms
jitcyc Cycle to cycle jitter — 200 — ps
Ifro144m_vdd Current consumption for vdd_sys — 70 — μA

_sys
Ifro144m_vdd Current consumption for vdd_core — 35 — μA

_core
1. Reference clock = 144 MHz.
4.2.4 Free-running oscillator FRO-12M specifications

Table 38. FRO-12M specifications
ffro12m FRO-12M frequency (nominal) — 12 — MHz
Δffro12m Frequency deviation

— — ±3 %
• open loop
— — ±0.6 %
• closed loop (using accurate clock source as
reference)
tstartup Start-up time — 5 — μs
NXP Semiconductors
Table 38. FRO-12M specifications (continued)
fos Frequency overshoot during startup — 10 20 %
Ifro12m Current consumption — 7 — μA
4.2.5 Free-running oscillator FRO-16K specifications

Table 39. FRO-16K specifications
ffro16k FRO-16K frequency (nominal) — 16.384 — kHz
Δffro16k Frequency deviation over –40 °C to 125 °C)

— — ±6 %
• open loop
TRIMstep Trimming step — 1.5 — %
tstartup Start-up time — 310 — μs
Ifro16k Current consumption — 50 — nA
4.2.6 550 MHz PLL specifications

Table 40. PLL specifications
Symbol Description Min Typ Max Units Notes
fcco CCO operating frequency 275 — 550 MHz
Ipll PLL operating current @ fcco = 550 — 484 — µA

MHz and fout = 55 MHz
fpll_ref PLL reference frequency range 5 — 150 MHz
Jpp_period Peak-Peak period jitter @ fref =12 — 110 — ps

MHz; fcco = 550 MHz
• fvco = 550 MHz
Jrms_int RMS interval jitter @fout = fcco = — 14 — ps

550 MHz, fref = 12 MHz
tpon Start-up time — — 500+300/ µs

fref
NOTE
The information in this table applies to both PLL0 (APLL) and PLL1 (SPLL).
4.3 Memories and memory interfaces
4.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.
NXP Semiconductors
4.3.1.1 Timing specifications

The following command times assume a flash bus clock frequency of 24 MHz. Command times will be increased by up to 10 µs
at 24 MHz if the module is exiting sleep mode when the command is launched. The time to abort a command is not included in
the following table.
Table 41. Flash command time specifications
Symbol Description Typ. Max. Unit Notes
trd1all Read 1s All execution time 256 KB — 1700 µs
512 KB — 3200
1024 KB — 6200
1536 KB — 9300
512 KB — 3200
1024 KB — 6200
trd1blk Read 1s Block execution time 256 KB — 1500 µs
512 KB — 3050
1024 KB — 6000
trd1scr Read 1s Sector execution time 8 KB — 50 µs 1
trd1pg Read 1s Page execution time 128 B — 4.4 µs 1
trd1pglv Read 1s Page at low voltage execution 128 B — 5.8 µs 1
time
trd1phr Read 1s Phrase execution time 16 B — 3.8 µs 1
trd1phrlv Read 1s Phrase at low voltage execution 16 B — 4.8 µs 1
time
trdmisr Read into MISR 8 KB — 50 µs 1
256 KB — 1500
512 KB — 3050
1024 KB — 6000
trd1iscr Read 1s IFR Sector execution time 8 KB — 50 µs 1
trd1ipg Read 1s IFR Page execution time 128 B — 4.4 µs 1
trd1ipglv Read 1s IFR Page at low voltage 128 B — 5.8 µs 1
execution time
trd1iphr Read 1s IFR Phrase execution time 16 B — 3.8 µs 1
trd1iphrlv Read 1s IFR Phrase at low voltage 16 B — 4.8 µs 1
execution time
trdimisr Read IFR into MISR execution time 8 KB — 50 µs 1
32 KB — 190
tpgmpg_initial Program Page execution time at <1k 128 B 450 600 2 µs 3
cycles
NXP Semiconductors
Table 41. Flash command time specifications (continued)
Symbol Description Typ. Max. Unit Notes
tpgmpg_lifetime Program Page execution time at >1k 128 B 450 750 2 µs 3
cycles
tpgmphr_initial Program Phrase execution time at <1k 16 B 135 180 2 µs 3
cycles
tpgmphr_lifetim Program Phrase execution time at >1k 16 B 135 225 2 µs 3
e cycles
tersall Erase All execution time 256 KB — 800 ms
512 KB — 1500
1024 KB — 2800
1536 KB — 4300
tersall Erase All execution time 256 KB — 800 ms
512 KB — 1500
1024 KB — 2800
tersscr Erase Sector execution time 8 KB 2 22 ms 3
tmasers Mass Erase execution time (via sideband) 256 KB — 800 ms
512 KB — 1500
1024 KB — 2800
1536 KB — 4300
1. Time to abort the command may significantly impact the time to execute the command.
2. Characterized but not tested in production
3. Measured from the time FSTAT[PERDY] is cleared.
4.3.1.2 Flash high voltage current behavior
Table 42. Flash high voltage current behavior
IDD_IO_PGM Average current adder to VDD_Px during flash — — 6 mA 1
programming operation
IDD_IO_ERS Average current adder to VDD_Px during flash — — 4 mA 1
erase operation
1. See the Power Management chapter in the reference manual for the specific VDD_Px voltage supply powering the flash
array.
4.3.1.3 Flash reliability specifications
Table 43. Flash reliability specifications
Symbol Description Min. Typ.1 Max. Unit Notes
Program Flash
NXP Semiconductors
Table 43. Flash reliability specifications (continued)
tnvmretp10k Data retention after up to 10 K cycles 10 50 — years
nnvmcycscr Sector cycling endurance 10 K 500 K — cycles 2
Tnvmretp1k Data retention after up to 1 K cycles 20 100 — years
Tnvmretp100 Data retention after up to 100 K cycles 5 50 — years

k
Nnvmcyc256 Sector cycling endurance for 256 KB 100 K 500 K — cycles 3
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile.
2. Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40°C ≤ Tj ≤ 125°C.
3. For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices
with two flash blocks, sectors must be located within the last 256 KB of each flash main memory but must not total more
than 256 KB per device.
4.3.2 FlexSPI specifications

Measurements are with a load of 15pf and an input slew rate of 1 V/ns.
4.3.2.1 FlexSPI input/read timing

There are three sources for the internal sample clock for FlexSPI read data:
• Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC]
= 0x1)
• SCK output generated by FlexSPI controller and loopbacked through the SCK pad (FlexSPIn_MCR0[RXCLKSRC] = 0x2)
• Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3)
The following sections describe input signal timing for each of these internal sample clock sources.
4.3.2.1.1 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1 or 0x2
Table 44. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol Parameter Min. Max. Unit
Frequency of operation — 40 MHz
TIS Setup time for incoming data 17 — ns
TIH Hold time for incoming data 0 — ns
Table 45. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 and FlexSPI input timing in SDR
mode where FlexSPIn_MCR0[RXCLKSRC] = 0x2
Frequency of operation — MHz

100
• OD mode
75
NXP Semiconductors
Table 45. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 and FlexSPI input timing in SDR
mode where FlexSPIn_MCR0[RXCLKSRC] = 0x2 (continued)
• SD mode 50
• MD mode
TIS Setup time for incoming data 2.4 — ns
Figure 13. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1 or 0x2
NOTE
Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller
sampling read data on the falling edge.
4.3.2.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in SDR mode:
• A1 - Memory generates both read data and read strobe on SCK rising edge (or falling edge)
• A2 - Memory generates read data on SCK falling edge and generates read strobe on SCK rising edge
Table 46. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)

100
• OD mode
75
• SD mode
50
• MD mode
TSCKD – Time delta between TSCKD and TSCKDQS -2 2 ns

TSCKDQS
NXP Semiconductors
Figure 14. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)
NOTE
Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI
controller samples read data on the DQS falling edge.
Table 47. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

100
• OD mode
75
• SD mode
50
• MD mode
TSCKD – Time delta between TSCKD and TSCKDQS -2 2 ns

TSCKDQS
Figure 15. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK falling edge and read strobe on the SCK
rising edge. The FlexSPI controller samples read data on a half-cycle delayed DQS falling edge.
4.3.2.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1 or 0x2
Table 48. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Frequency of operation — 20 MHz
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Table 48. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 (continued)
TIS Setup time for incoming data 17 — ns
Table 49. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 and FlexSPI input timing in DDR
mode where FlexSPIn_MCR0[RXCLKSRC] = 0x2
Symbol Parameter Min Max Unit

75
• OD mode
50
• SD mode
25
• MD mode
TIS Setup time for incoming data 2.27 — ns
Figure 16. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2
4.3.2.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in DDR mode:
• B1—Memory generates both read data and read strobe on SCK edges
• B2—Memory generates read data on SCK edges and generates read strobe on SCK2 edges
Table 50. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

75
• OD mode
50
• SD mode
25
• MD mode
TSCKD - Time delta between TSCKD and TSCKDQS -1 1 ns

TSCKDQS
NXP Semiconductors
SCK
TSCKD
SIO[0:7]
TSCKDQS
DQS
Figure 17. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
Table 51. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)

75
• OD mode
50
• SD mode
25
• MD mode
TSCKD - Time delta between TSCKD and TSCKDQS -1 1 ns

TSCKDQS
Figure 18. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (caseB2)
4.3.2.2 FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals and data outputs.
4.3.2.2.1 SDR mode
Table 52. FlexSPI output timing in SDR mode

100
• OD mode
75
• SD mode
50
• MD mode
1
TCK SCK clock period 6.0 — ns
NXP Semiconductors
Table 52. FlexSPI output timing in SDR mode (continued)
TDVO Output data valid time — 3 ns
TDHO Output data hold time 2 — ns
TCSS Chip select output setup time 3 x TCK - 1 — ns
TCSH Chip select output hold time 3 x TCK + 2 — ns
1. The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to
the FlexSPI SDR input timing specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the default values are shown above. Refer
to the Reference Manual for more details.
Figure 19. FlexSPI output timing in SDR mode
4.3.2.2.2 DDR mode
Table 53. FlexSPI output timing in DDR mode
Frequency of operation1 — MHz

75
• OD mode
50
• SD mode
25
• MD mode
TCK SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0) 6.0 — ns
TDVO Output data valid time — 1.7 ns
TDHO Output data hold time 0.8 — ns
TCSS Chip select output setup time 3 x TCK/2 - 0.7 — ns
TCSH Chip select output hold time 3 x TCK/2 + 0.8 — ns
1. The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to
the FlexSPI DDR input timing specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the default values are shown above. Refer
to the Reference Manual for more details.
NXP Semiconductors
Figure 20. FlexSPI output timing in DDR mode
4.3.2.3 eFuse specifications
Table 54. Fusebox electrical specifications
VSYS_PROG VDD_SYS Voltage for fuse programming 2.25 2.5 2.75 V 1
ISYS_PROG Fuse programming current — — 40 mA 2
TPROG Fuse programming time — 10 11 µs 3
1. VDD_SYS ramp-up slew rate MUST be slower than 2.5V/100 µs to avoid unintentional program
2. This is the current required to program just the fuse and is in addition to any other current being drawn by the device.
3. The maximum total accumulated time for elevated VDD_SYS (VDD_SYS > 1.98V) is 20 seconds over the lifetime of the
device.
4.4 Analog
4.4.1 ADC electrical specifications
4.4.1.1 ADC operating conditions
Table 55. ADC operating conditions
V_ANA Supply voltage 1.71 3.6 V
ΔVDD –0.1 0 0.1 mV 2
ΔVSS –0.1 0 0.1 mV 2
VREFH ADC reference voltage high 0.99 VDD_ANA V
VREFL ADC reference voltage low VSSA VSSA V 3
VADIN Input Voltage VREFL VREFH V 3,4,5
fADCK ADC Input clock frequency
Low-power mode (PWRSEL=00) 6 24 MHz
High-speed 16b mode (PWRSEL==10) 6 48 MHz
High-speed 12b mode (PWRSEL==10) 6 60 MHz
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Table 55. ADC operating conditions (continued)
CADIN Input Capacitance 3.7 4.63 pF
CP Parasitic Capacitance of pad/package 2 3 pF
RAS Analog source resistance (external) 5 kΩ 6
RADIN High-Speed Dedicated Input kΩ 7,8
VDDAD ≥ 1.71 V 0.95 1.7 kΩ
VDDAD ≥ 2.1 V 1.575 kΩ
VDDAD ≥ 2.5 V 1.4 kΩ
Standard Dedicated Input kΩ
VDDAD ≥ 1.71 V 1.35 3.25 kΩ
VDDAD ≥ 2.1 V 2.14 kΩ
VDDAD ≥ 2.5 V 1.75 kΩ
Standard Muxed Input kΩ
VDDAD ≥ 1.71 V 1.65 7.25 kΩ
VDDAD ≥ 2.1 V 3.05 kΩ
VDDAD ≥ 2.5 V 2.35 kΩ
1. Typical values assume VDD_ANA = 3.0 V, Temp = 25 °C, fADCK = 24 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference
3. For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally.
4. If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result in a
full-scale conversion result
5. ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected
muxed inputs may exceed VDD_ANA but must not exceed the IO supply associated with the inputs (VDD_Px) when a
conversion is in progress. If an ADC input may exceed these levels, then a minimum of 1 K series resistance must be used
between the source and the ADC input pin.
6. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible.
7. There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index
map in reference manual
8. If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel
type
NXP Semiconductors
Figure 21. ADC input impedance equivalency diagram
4.4.1.2 ADC electrical characteristics
Table 56. ADC electrical specifications
IDDA Supply current 2
PWREN=0, Conversions triggered at 1 kS/s 2.2 µA
PWREN=1, No Conversions 160 µA
Low-power, single-ended mode, 6 MHz 295 390 µA
Low-power, differential, or dual-SE mode, 6 410 550 µA

MHz
Low-power, single-ended mode, 24 MHz 380 520 µA
Low-power, differential, or dual-SE mode, 24 500 690 µA

MHz
High-speed, single-ended mode, 48 MHz 730 960 µA
High-speed, differential, or dual-SE mode, 48 1150 1490 µA

MHz
ITS Temp Sensor Current Adder 40 50 µA
CSMP ADC Sample cycles 3.5 131.5 cycles 3
NXP Semiconductors
Table 56. ADC electrical specifications (continued)
C_CONV ADC conversion cycles
16-bit 24 152 cycles
12-bit 19 147 cycles
C_RATE ADC conversion rate 4
Low-power mode 0.857 MS/s
High-speed 12b mode 3.15 MS/s
High-speed 16b mode 2.0 MS/s
T_SMP_REQ Required Sample Time See ns 5
equation
T_AZ_REQ Required Auto-Zero time 5
Low-power mode 291.7 ns
High-speed 12b mode 59.3 ns
High-speed 16b mode 72.9 ns
T_SMP External inputs See ns 5
equation
T_SMP_INT Internal inputs 1.5 µs 6
DNL Differential non-linearity ±1 LSB7 8
INL Integral non-linearity ±3 LSB7 8
Z_SE Zero-scale error (V_ADIN = V_REFL) ±2 LSB7 8
F_SE Full-scale error (V_ADIN = V_REFH) ±5 LSB7 8
TUE Total Unadjusted Error ±7 LSB7 8
ENOB Differential Effective number of bits 8, 9
1 MS/s (AVGS=001) 13.5 bits
2 MS/s 13.0 bits
3.16 MS/s (for 12-bit mode) 11.3 bits
Single-ended Effective number of bits
1 MS/s (AVGS=001) 13.0 bits
2 MS/s 12.5 bits
3.16 MS/s (for 12-bit mode) 11.0 bits
SINAD Differential Signal-to-noise plus distortion 8,9
1 MS/s (AVGS=001) 83 dB
2 MS/s 80 dB
3.16 MS/s (for 12-bit mode) 70 dB
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Table 56. ADC electrical specifications (continued)
Single-ended Signal-to-noise plus distortion
1 MS/s (AVGS=001) 80 dB
2 MS/s 77 dB
3.16 MS/s (for 12-bit mode) 68 dB
THD Total Harmonic distortion 95 dB 8,9
SFDR Spurious free dynamic range 96 dB 8,9
tADCSTUP ADC/VREF start-up time 5 µs 10
E_IL Input leakage error llkg mV 11.
E_TS Temperature sensor error 12
T=-40 to 105 ˚C 1 3 ˚C
T=-40 to 125 ˚C 1.5 4 ˚C
A Slope Factor Constant – 783 –
B Offset Constant – 297 –
α Bandgap constant – 9.63 –
1. Typical values assume VDD_ANA = 3.3 V, Temp = 25 °C, fADCK = 24 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. The ADC supply current depends on the ADC conversion clock speed, conversion rate, and power mode. Typical value
show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00.
3. Must meet minimum TSMP requirement
4. Maximum conversion rate for high-speed mode is with FADCK = 48 MHz. Maximum conversion rate for low-power mode is
FADCK = 24 MHz and 7.5 sample cycles (to meet the minimum auto-zero time requirement)
5. Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and desired
sample accuracy in bits(B). Calculate it with formula: T SMP_REQ = B*0.693*[RAS*(CAS+CP+CADIN)+ (RAS + R ADIN)* CADIN.
Required auto-zero time is for ADC comparator offset cancellation. The chosen sample time should be no less than
maximum of the two: TSMP = max(TSMP_REQ,TAZ_REQ)
6. Internal channel inputs are those that do not come from external source (temperature sensor, bandgap).
7. 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16- bit specifications, multiply by 4.
8. All accuracy numbers assume that the ADC is calibrated with VREFH=VDD_ANA and using a high- speed- dedicated input
channel.
9. Dynamic results assume Fin=1 kHz sinewave, no averaging.
10. Set the power-up delay (PUDLY) according to the ADC start-up time if PWREN=0.
11. Ilkg = leakage current (Refer to pin leakage specification in the voltage and current operating ratings of packaged device)
12. The temperature sensor can be calibrated to a +/- 0.5 % precision after board assembly by using a 3-temperature
calibration flow with accurate ± 0.15 % temperature chamber.
NXP Semiconductors
Figure 22. ENOB VS ADC clock graph
4.4.2 12-bit DAC electrical characteristics
4.4.2.1 12-bit DAC operating requirements
Table 57. 12-bit DAC operating requirements
VDD_ANA Supply voltage 1.71 — 3.6 V
VDACR Reference voltage 0.97 — VDD_ANA V 1
CL Output load capacitance — 50 100 pF 2
IL Output load current -1 — 1 mA 3
DAC_c_rat DAC conversion rate — — 1 MSPS

e
1. The DAC reference can be selected to be VDD_ANA or VREFH or VREFO PAD, keep VDD_ANA be the highest voltage.
2. A small load capacitance (50 pF) can improve the bandwidth performance of the DAC.
3. Sink or source current availability
4.4.2.2 12-bit DAC operating behaviors
Table 58. 12-bit DAC operating behaviors
IDD_DAC Supply current

• Normal mode — 300 500 μA
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Table 58. 12-bit DAC operating behaviors (continued)
• Low-power mode — 100 150 μA

• Disabled — 10 — nA
tDAC Full-scale settling time (0x100 to 0xF00) μs 1
• Normal mode — 2.5 3

• Low-power mode — 5 6
tCCDAC Code-to-code settling time (0xBF8 to — 0.7 1.0 μs 1
0xC08)
Vdacoutl DAC output voltage range low — high- — — 100 mV

speed mode, no load, DAC set to 0x000
Vdacouth DAC output voltage range high — high- VDACR−100 — VDACR mV

speed mode, no load, DAC set to 0xFFF
INL Integral non-linearity error — — ±3 LSB 2
DNL Differential non-linearity error — — ±1 LSB 3
EOFFSET Offset error — ±0.4 ±0.8 %FSR 4
EG Gain error %FSR 4

— ±0.3 ±0.6
• VDACR < 2.1 V
— ±0.1 ±0.3
• VDACR > 2.1 V
PSRR Power supply rejection ratio, VDD_ANA ≥ — 70 — dB

2.4 V
TCO Temperature coefficient offset voltage at — ±30 — μV/C 5
middle scale
TEO Temperature coefficient offset error — 30 — μV/C
TGE Temperature coefficient gain error — 10 — PPM/C
Rop Output resistance (load = 10 kΩ) — 200 — Ω
SR Slew rate 100 h ->F00 h or F00 h ->100 h V/μs
• Normal mode — 3.6 —

• Low-power mode — 0.5 —
CT DAC to DAC crosstalk — — –80 dB 6
TPU Power-up time — 2.5 — μs
1. Settling within ±1 LSB measured with a 47 pF load.

2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. Calculated by a best fit curve from VSS_ANA + 100 mV to VDACR − 100 mV
5. VDD_ANA = 3.0 V, reference select set for VDD_ANA (DACx_CO:DACRFS = 1), high- power mode (DACx_C0:LPEN = 0),
DAC set to 0x800, temperature range is across the full range of the device.
6. If two DACs are used and share same VREFH
NXP Semiconductors
2
DAC12 INL (LSB)
-2
-4
-6
-8
0 500 1000 1500 2000 2500 3000 3500 4000
Digital Code
Figure 23. Typical INL error vs. digital code
NXP Semiconductors
1.499
1.4985
1.498
DAC12 Mid Level Code Voltage
1.4975
1.497
1.4965
1.496
-40 25 55 85 105 125
Temperature °C
Figure 24. Offset at half scale vs. temperature
4.4.3 14-bit DAC electrical characteristics
4.4.3.1 14-bit DAC operating requirements
Table 59. 14-bit DAC operating requirements
VDD_ANA Supply voltage 1.71 — 3.6 V
VDACR Hook to VDD_ANA pad 1.71 — VDD_ANA V
TA Temperature -40 — 135 °C
CL Output load capacitance — 50 100 pF 1
IL Output load current -3.6 — 3.6 mA 2
1. A small load capacitance (50 pF) can improve the bandwidth performance of the DAC.
2. Sink or source current availability
NXP Semiconductors
4.4.3.2 14-bit DAC operating behaviors
Table 60. 14-bit DAC operating behaviors
IDDA_DIS Supply current

— 30 nA
• Disable mode
IDDA Supply current 1

— 2 2.8 mA
• Run mode
VDACOUTL DAC low level output voltage VSSA — 0.15 V
VDACOUT DAC high level output voltage VDD_ANA– 0.15 — VDD_A V

H NA
DNL Differential non-linearity error — ±0.5 ±4 LSB
INL Integral non-linearity error — ±4 ±8 LSB
EO Offset error — ±0.1 % of

FSR
TEO Offset error temperature coefficient — 30 — μV/C
EG Gain error — %FSR

±0.3
• VDACR < 2.1 V
±0.1
• VDACR > 2.1V
TEG Gain error temperature coefficient — 10 — PPM/C
TFS Full scale rising/falling setting time — 0.3 μs
Fclk Maximum output update rate/conversion rate — 5 — Msps
SR Slew rate V/μs
• Normal mode
— 15 —
PSRR Power supply rejection ratio — 70 — dB
Glitch Glitch energy — 30 nV/s
CT DAC to DAC crosstalk — — –80 dB 2
ROP Output resistance — 25 250 ohm
TPU Power-up time — 2.5 — μs 3
1. VDD_ANA and VREFH total current

2. If two DAC are used and share same VREFH
3. Buffered voltage mode, buffer be enabled and normal working time
NXP Semiconductors
Figure 25. 14-bit DAC DNL
Figure 26. 14-bit DAC INL
NXP Semiconductors
4.4.4 CMP and 8-bit DAC electrical specifications

Table 61. Comparator and 8-bit DAC electrical specifications
VDD Supply voltage 1.71 — 3.6 V
VREFH 8-bit DAC reference voltage high 0.97 — VDD V
IDD_CMP Supply current

• High speed mode (EN=1, HPMD=1) — 200 — μA
• Normal mode (EN=1, HPMD=0, NPMD=0) — 10 — μA
• Low-power mode (EN=1, HPMD=0, — 400 — nA

NPMD=1)
VAIN Analog input voltage VSS — VDD V
VAIO Analog input offset voltage

• High speed mode — — 20 mV
• Normal mode — — 20 mV
• Low-power mode — — 40 mV
VH Analog comparator hysteresis 1
• CR0[HYSTCTR] = 00 — 0 — mV
• CR0[HYSTCTR] = 01 — 10 — mV
• CR0[HYSTCTR] = 10 — 20 — mV
• CR0[HYSTCTR] = 11 — 30 — mV
VCMPOh Output high VDD - 0.2 — — V
VCMPOl Output low — — 0.2 V
tD 2
Propagation delay
• High speed mode, 100 mV overdrive, power — — 25 ns
> 1.71V
• High speed mode, 30 mV overdrive, power — — 50 ns
> 1.71V
• Normal mode, 30 mV overdrive, power > — — 600 ns
1.71V
— — 5 μs
• Low-power mode, 30 mV overdrive, power >
1.71V
tinit Analog comparator initialization delay — — 40 μs 3
IDAC8b 8-bit DAC current adder (enabled)

— 10 — μA
• High power mode (EN=1, PMODE=1)
— 1 — μA
• Low power mode (EN=1, PMODE=0)
INL 8-bit DAC integral non-linearity LSB 4
NXP Semiconductors
Table 61. Comparator and 8-bit DAC electrical specifications (continued)
• Low/High power mode, supply power > -1 — +1.0

1.71V
• Low power mode, supply power < 1.71V -2 — +2
DNL 8-bit DAC differential non-linearity LSB 4
• Low/High power mode, power > 1.71V -1 — +1.0
• Low power mode, power < 1.71V -1 — +1
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V.
2. Overdrive does not include input offset voltage or hysteresis
3. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL])
and the comparator output settling to a stable level.
4. 1 LSB = Vreference/256
Typical hysteresis
Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 1)
NXP Semiconductors
Figure 28. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 0)
Figure 29. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1)
4.4.5 Voltage reference electrical specifications
NXP Semiconductors
Table 62. VREF operating requirements
VDD_ANA Supply voltage 1.71 3.0 3.6 V 1
CL Output load capacitance — 220 — nF 2,3
1. VDD_ANA must be at least 600 mV greater than the selected VREFO output voltage.
2. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
3. The minimum CL capacitance must take into account the variation in capacitance of the chosen capacitor due to voltage,
temperature, and aging.
Table 63. VREF operating behaviors
1.0 V low-power reference voltage
Vvrefo_lpbg Voltage reference output 1.0 V - LP bandgap — 1.0 — V 1
Iq_lpbg Quiescent current - LP bandgap — 19 — μA
Iptat Output current reference (PTAT) - LP bandgap — 1 — μA

(room temp)
Iztc Output current reference (ZTC) - LP bandgap — 1 — μA
tst_lpbg Start-up time - LP bandgap — — 20 μs
ΔV/ Voltage variation - LP bandgap — ±5 — %

Vrefo_lpbg
High precision reference voltage
Vvrefo Voltage reference output 2.0 V 1.0 — 2.1 V 2,1
Vstep Fine trim step — 0.5 x — mV

(1/F)3
Iq Quiescent current — 750 — μA
Iout Drive strength ±1 — — mA
tst_hcbg Start-up time — — 400 μs
ΔVLOAD Load regulation — 100 200 µV/mA 4
Vacc Absolute voltage accuracy (room temp) — — ±6.5 mV
Vdev Voltage deviation over temperature — 15 — ppm/℃
1. See the Reference Manual of the chip for the appropriate settings of the VREF Status and Control register.
2. Vvrefo max is also ≤ VDD_ANA - 600 mV.
3. F is feedback factor, F = 1/Vvrefo
4. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load.
NXP Semiconductors
4.4.6 Op-amp electrical specifications

Table 64. Op-amp electrical specifications
Symbol Characteristic Min Typ Max Unit
VDD_ANA Operating Voltage 1.71 3 3.6 V
ISUPPLY1 Supply Current (IOUT=0 mA high- 450 μA

performance mode)
ISUPPLY2 Supply Current (IOUT=0 mA low-power 120 μA

mode)
VOS Input Offset Voltage mV

• High performance mode (CTRL[MODE] -5 - 5
= 0) -
-8 8
• Low power mode (CTRL[MODE] = 1)
αVOS Input Offset Voltage Temperature Coefficient 5 μV/C
VCML Input Common Mode Voltage Low 0 V
VCMH Input Common Mode Voltage High VDD_ANA V
PSRR Power Supply Rejection Ration @ DC 80 dB
SRh Slew Rate positive (ΔVIN=1 V, high- 6 V/μs

performance mode)
SRl Slew Rate positive (ΔVIN=1 V, low-power 1 V/μs

mode)
GBWh Unity Gain Bandwidth (high-performance 6 MHz

mode)
GBWl Unity Gain Bandwidth (low-power mode) 1 MHz
AV DC Open Loop Voltage Gain 110 dB
CL Load Capacitance Driving Capability 20 pF
RL Load resistance (low-power mode) 3K Ω
PM Phase Margin 60 deg
Vn Voltage noise density @1 kHz (high- 100 nv/sqrtHz

performance mode)
Vo Output swing 0.2 VDD_ANA - V

0.2
Tsettle Settling time (high-speed mode invert 1 μs

gain=4 input=10 mV with +/-730 μV settling
accuracy)
Cin Input Capacitance 5 pF
T_start Required sample time is dictated by external 5 μs

components
NXP Semiconductors
4.4.7 PGA electrical specifications

NOTE
Gain is PGA mode gain and gain is 2.4.8
Table 65. PGA electrical specifications
Characteristic Symbol Min Typ Max Unit
PGA gain accuracy Error gain ±1 %
PGA bandwidth (inverting mode, gain=1, 2, 6/(gain+1) MHz

4)
PGA bandwidth (inverting mode, gain=8, 16, 32/(gain+1) MHz

33, 64)
PGA bandwidth (non-inverting mode, 6/(gain+1) MHz

gain=1, 2, 4)
PGA bandwidth (non-inverting mode, 32/(gain+1)- MHz

gain=8, 16, 33, 64)
4.5 Timers
See General switching specifications.
4.5.1 SCTimer/PWM output timing

Simulated skew (over process, voltage, and temperature) of any two SCT fixed-pin output signals; sampled at the 50% level of
the rising or falling edge; values guaranteed by design.
Table 66. SCTimer/PWM output dynamic characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
tsk(o) Output skew time OD mode: 3.3 0 — 3.3 ns
SD mode:5 5
MD mode:10 10
4.6 Communication interfaces
4.6.1 LPUART
4.6.2 LPSPI switching specifications

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many
of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes.
Table 67. LPSPI master mode timing
LP1 Frequency of operation 1
NXP Semiconductors
Table 67. LPSPI master mode timing (continued)
• Master TX in OD mode
MHz
— LPSPI0–LPSPI2 — 25
• Master RX in OD mode
• Master TX in SD mode
• Master RX in SD mode
• Master TX in MD mode
— LPSPI0–LPSPI2 — 12.5
• Master RX in MD mode
LP2 SCK period 2 x tperiph 2048 x tperiph ns
LP3 Enable lead time 1/2 — tperiph 2
LP4 Enable lag time 1/2 — tperiph 2
LP5 Clock (SCK) high or low time tSCK/2 - 3 tSCK/2 ns —
LP6 Data setup time (inputs) — ns —

14.4
• LPSPI0–LPSPI2
7.2
• LPSPI3–LPSPI5
4.8
• LPSPI6–LPSPI9
LP7 Data hold time (inputs) 0 — ns —
NXP Semiconductors
Table 67. LPSPI master mode timing (continued)
LP8 Data valid (after SCK edge) ns —

14.4
• LPSPI0–LPSPI2 —
7.2
• LPSPI3–LPSPI5
4.8
• LPSPI6–LPSPI9
LP9 Data hold time (outputs) 1 — ns —
1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI
peripheral functional clock.
2. tperiph = 1/fperiph
PCS
(OUTPUT)
LP3 LP2 LP4

SCK LP5
(CPOL=0)
(OUTPUT) LP5
SCK
(CPOL=1)
(OUTPUT)
LP6 LP7
SIN
MSB IN2 BIT 6 . . . 1 LSB IN
(INPUT)
LP8 LP9
SOUT
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 30. LPSPI master mode timing (CPHA = 0)
NXP Semiconductors
PCS
(OUTPUT)
LP2
LP3 LP4
SCK
(CPOL=0)
(OUTPUT)
LP5 LP5
SCK
(CPOL=1)
(OUTPUT)
LP6 LP7
SIN
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
LP8 LP9
SOUT
(OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA
1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 31. LPSPI master mode timing (CPHA = 1)
Table 68. LPSPI slave mode timing
LP1 Frequency of operation 1
• Slave TX in OD mode
— LPSPI0–LPSPI2 MHz
— 12.5
— LPSPI3–LPSPI5
— 20
— LPSPI6–LPSPI9
— 30
• Slave RX in OD mode
— LPSPI0–LPSPI2
• Slave TX in SD mode — 75
— LPSPI0–LPSPI2
• Slave RX in SD mode — 25
— LPSPI0–LPSPI2
— LPSPI3–LPSPI5
— 12.5
— LPSPI6–LPSPI9
— 30
• Slave TX in MD mode — 50
38 <<CLASSIFICATION>>
<<NDA MESSAGE>>
NXP Semiconductors
Table 68. LPSPI slave mode timing (continued)
• Slave RX in MD mode
LP2 SPSCK period 4 x tperiph 2048 x ns

tperiph
LP3 Enable lead time 1 — tperiph 2
LP4 Enable lag time 1 — tperiph 2
LP5 Clock (SPSCK) high or low time tSPSCK/2 - 5 tSPSCK/2 ns —
LP6 Data setup time (inputs) — ns —

• LPSPI0~LPSPI2 14.4
• LPSPI3~LPSPI5 6
LP7 Data hold time (inputs) 0 — ns —
LP8 Slave access time — tperiph ns 2,3
LP9 Slave SDO disable time — tperiph ns 2,4
LP10 Data valid (after SPSCK edge) — ns —

• LPSPI3~LPSPI5 17
• LPSPI6~LPSPI9 13
LP11 Data hold time (outputs) 2 — ns —
1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI
peripheral functional clock.
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
NXP Semiconductors
PCS
(INPUT)
LP2 LP4
SCK
(CPOL=0)
(INPUT)
LP3 LP5 LP5
SCK
(CPOL=1)
(INPUT)
LP9
LP8 LP10 LP11 LP11
SOUT see SEE

note SLAVE MSB BIT 6 . . . 1 SLAVE LSB OUT
(OUTPUT) NOTE
LP6 LP7
SIN
MSB IN BIT 6 . . . 1 LSB IN
(INPUT)
NOTE: Not defined
Figure 32. LPSPI slave mode timing (CPHA = 0)
PCS
(INPUT)
LP2 LP4
LP3
SCK
(CPOL=0)
(INPUT)
LP5 LP5
SCK
(CPOL=1)
(INPUT)
LP10 LP11 LP9
SOUT see
SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT
(OUTPUT) note
LP8 LP6 LP7

SIN
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
NOTE: Not defined
Figure 33. LPSPI slave mode timing (CPHA = 1)
4.6.3 Inter-Integrated Circuit Interface (I2C) specifications

Table 69. I 2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Min. Max. Min. Max.
SCL Clock Frequency fSCL 0 100 0 400 kHz
NXP Semiconductors
Table 69. I 2C timing (continued)
Characteristic Symbol Standard Mode Fast Mode Unit
Min. Max. Min. Max.
Hold time (repeated) START condition. tHD; STA 4 — 0.6 — µs

After this period, the first clock pulse is
generated.
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START tSU; STA 4.7 — 0.6 — µs

condition
Data hold time for I2C bus devices tHD; DAT 01 3.452 03 0.91 µs
Data set-up time tSU; DAT 2504 — 1002,5 — ns
Rise time of SDA and SCL signals tr — 1000 20 +0.1Cb6 300 ns
Fall time of SDA and SCL signals tf — 300 20 +0.1Cb5 300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and tBUF 4.7 — 1.3 — µs

START condition
Pulse width of spikes that must be tSP N/A N/A 0 50 ns

suppressed by the input filter
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT =
1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
Table 70. I 2C 1 Mbps timing
Characteristic Symbol Min. Max. Unit
SCL Clock Frequency fSCL 0 1 MHz
Hold time (repeated) START condition. After this tHD; STA 0.26 — µs
period, the first clock pulse is generated.
LOW period of the SCL clock tLOW 0.5 — µs
HIGH period of the SCL clock tHIGH 0.26 — µs
Set-up time for a repeated START condition tSU; STA 0.26 — µs
Data hold time for I2C bus devices tHD; DAT 0 — µs
Data set-up time tSU; DAT 50 — ns

NXP Semiconductors 
Table 70. I 2C 1 Mbps timing (continued)
Characteristic Symbol Min. Max. Unit
Rise time of SDA and SCL signals tr 20 +0.1Cb 1 120 ns
Fall time of SDA and SCL signals tf 20 +0.1Cb1 120 ns
Set-up time for STOP condition tSU; STO 0.26 — µs
Bus free time between STOP and START condition tBUF 0.5 — µs
Pulse width of spikes that must be suppressed by tSP 0 50 ns

the input filter
SDA
tSU; DAT tf
tf tLOW tr tHD; STA tSP tr tBUF
SCL
HD; STA tSU; STA tSU; STO

S tHD; DAT tHIGH SR P S
Figure 34. Timing definition for devices on the I2C bus
4.6.4 Improved Inter-Integrated Circuit Interface (MIPI-I3C) specifications

Unless otherwise specified, MIPI-I3C specifications are timed to/from the VIH and/or VIL signal points.
Table 71. MIPI-I3C specifications when communicating with legacy I2C devices
Symbol Characteristic 400 kHz/Fast mode 1 MHz/ Fast+ mode Unit
Min. Max. Min. Max.
fSCL SCL Clock Frequency 0 0.4 0 1.0 MHz
tSU_STA Set-up time for a repeated START condition 600 — 260 — ns
Hold time tHD; STA 600 — 260 — ns

(repeated)
START
condition
tLOW LOW period of the SCL clock 1300 — 500 — ns
tHIGH HIGH period of the SCL clock 600 — 260 — ns
tSU_DAT Data set-up time 100 — 50 — ns
tHD_DAT Data hold time for I2C bus devices 0 — 0 — ns
tf Fall time of SDA and SCL signals 20 + 300 20 + 120 ns

0.1Cb1 0.1Cb1
NXP Semiconductors
Table 71. MIPI-I3C specifications when communicating with legacy I2C devices (continued)
Symbol Characteristic 400 kHz/Fast mode 1 MHz/ Fast+ mode Unit
Min. Max. Min. Max.
tr Rise time of SDA and SCL signals 20 + 300 20 + 120 ns

0.1Cb1 0.1Cb1
tSU_STO Set-up time for STOP condition 600 — 260 — ns
tBUF Bus free time between STOP and START 1.3 — 0.5 — µs
condition
tSP Pulse width of spikes that must be suppressed 0 50 0 50 ns

by the input filter
Table 72. MIPI-I3C open drain mode specifications
Symbol Characteristic Min. Max. Unit Notes
tLOW_OD LOW period of the SCL clock 200 — ns
tDIG_OD_L tLOW_OD + — ns
tfDA_OD
(min)
tHIGH HIGH period of the SCL clock tCF 12 ns
tfDA_OD Fall time of SDA signal 20 +0.1Cb 120 ns 1
tSU_OD Data set-up time during open drain mode 3 — ns
tCAS Clock after START (S) Condition

38.4 n 1μ s
• ENTAS0
38.4 n 100 μ s
• ENTAS1
38.4 n 2m s
• ENTAS2
38.4 n 50 m s
• ENTAS3
tCBP Clock before STOP (P) condition tCAS(min)/2 — ns
tMMOverlap Current master to secondary master overlap time tDIG_OD_L — ns

during handoff
tAVAL Bus available condition 1 — μs
tIDLE Bus idle condition 1 — ms
tMMLock Time internal where new master not driving SDA low tAVAL — μs
Table 73. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes
fSCL SCL Clock Frequency 0.01 12 12.5 MHz
tLOW LOW period of the SCL clock 24 — — ns
NXP Semiconductors
Table 73. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes (continued)
tDIG_L 32 — — ns
tHIGH_MIXE HIGH period of the SCL clock for a mixed bus 24 — — ns

D
tDIG_H_MIXE 32 — 45 ns 1
tHIGH HIGH period of the SCL clock 24 — — ns
tDIG_H 32 — — ns
tSCO Clock in to data out for a slave — — 122 ns
tCR SCL clock rise time — — 150 x 1/ ns

fSCL
(capped at
60)
tCF SCL clock fall time — — 150 x 1/ ns

fSCL 
(capped at
60) 
tHD_PP SDA signal data hold ns

tCR + 3 and — —
• Master mode tCF + 3
— —
• Slave mode 0
tSU_PP SDA signal setup 3 — — ns
tCASr Clock after repeated START (Sr) tCAS (min) — — ns
tCBSr Clock before repeated START (Sr) tCAS — — ns

(min)/2
Cb Capacitive load per bus line — — 50 pF
1. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make
sure that I2C devices do not interpret I3C signaling as valid I2C signaling.
2. It doesn't include output pad delay.
SDA
tSU; DAT tf
tf tLOW tr tHD; STA tSP tr tBUF
SCL
HD; STA tSU; STA tSU; STO

S tHD; DAT tHIGH SR P S
Figure 35. Timing definition for devices on the I2C bus
NXP Semiconductors
4.6.5 USB Full-speed device electrical specifications

This section describes the USB0 port Full Speed/Low Speed transceiver. The USB0 (FS/LS Transceiver) meets the electrical
compliance requirements defined in the Universal Serial Bus Revision 2.0 Specification with the amendments below.
• USB ENGINEERING CHANGE NOTICE
— Title: 5 V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
— Title: Pull-up/Pull-down resistors
— Title: Suspend Current Limit Changes
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 version 1.1a July 27, 2012
• Battery Charging Specification (available from USB-IF)
— Revision 1.2 (including errata and ECNs through March 15, 2012), March 15, 2012
This SoC does not have a dedicated pin to monitor the state of the USB VBUS signal. Please refer to the USBFS chapter in
the Reference Manual for methods which can be used for VBUS Session_Valid detection with either a P4-12/ALT1 pin using an
external resistive divider.
4.6.6 USB Full Speed Transceiver andHigh-Speed PHY specifications

This section describes High-Speed PHY parameters. The high-speed PHY is capable of full and low-speed signaling as well. The
USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 Specification with the
amendments below.
• Universal Serial Bus Specification, Revision 2.0, 2000, with amendments including the ones listed below:
• Errata for “USB Revision 2.0 April 27, 2000” as of 12/7/2000
• Errata for “USB Revision 2.0 April 27, 2000” as of May 28, 2002
• Pull-up / Pull-down Resistors (USB Engineering Change Notice)
• Suspend Current Limit Changes (USB Engineering Change Notice)
• Device Capacitance (USB Engineering Change Notice)
• USB 2.0 Connect Timing Update (USB Engineering Change Notice as of April 4, 2013)
• USB 2.0 VBUS Max Limit (USB Engineering Change Notice)
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification, Revision 2.0 version 1.1a, July 27, 2012
• Maximum VBUS Voltage (USB OTGEH Engineering Change Notice)
• Universal Serial Bus Micro-USB Cables and Connectors Specification, Revision 1.01, 2007
USB1_VBUS pin is a detector function which is 5V tolerant and complies with the above specifications without needing any
external voltage division components.
NOTE
The USB HS PHY does not support operation when VDD_CORE is configured to 1.0V level
NXP Semiconductors
4.6.7 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single Data Rate) timing,
eMMC4.4/4.41/4.5 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.6.7.1 SD/eMMC4.3 (single data rate) AC timing

Figure 36depicts the timing of SD/eMMC4.3, and Table 74 lists the SD/eMMC4.3 timing characteristics.
Figure 36. SD/eMMC4.3 timing
Table 74. SD/eMMC4.3 interface timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency (Low Speed) fPP1 0 400 kHz
Clock Frequency (SD/SDIO Full Speed/High Speed) fPP2 0 25/50 MHz
Clock Frequency (MMC Full Speed/High Speed) fPP3 0 20/52 MHz
Clock Frequency (Identification Mode) fOD 100 400 kHz
SD2 Clock Low Time tWL 7 — ns
SD3 Clock High Time tWH 7 — ns
SD4 Clock Rise Time tTLH — 3 ns
SD5 Clock Fall Time tTHL — 3 ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6 uSDHC Output Delay tOD –6.6 3.6 ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD7 uSDHC Input Setup Time tISU 2.5 — ns
SD8 uSDHC Input Hold Time4 tIH 1.5 — ns
1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
NXP Semiconductors
3. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode,
clock frequency can be any value between 0–52 MHz.
4. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4.6.7.2 eMMC4.4/4.41 (dual data rate) AC timing

Figure 37depicts the timing of eMMC4.4/4.41.Table 75lists the eMMC4.4/4.41 timing characteristics. Be aware that only DATA is
sampled on both edges of the clock (not applicable to CMD).
Figure 37. eMMC4.4/4.41 timing
Table 75. eMMC4.4/4.41 interface timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency (eMMC4.4/4.41 DDR) fPP 0 MHz

52
• OD mode
50
• SD mode
40
• MD mode
SD1 Clock Frequency (SD3.0 DDR) fPP 0 MHz

50
• OD mode
50
• SD mode
40
• MD mode
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2 uSDHC Output Delay tOD 2.5 7.1 ns
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD4 uSDHC Input Hold Time tIH 1.5 — ns
4.6.7.3 SDR50 AC timing

Figure 38 depicts the timing of SDR50, and Table 76lists the SDR50 timing characteristics.
NXP Semiconductors
Figure 38. SDR50 timing
Table 76. SDR50 interface timing specification
ID Parameter Symbol Min Max Unit
Card Input Clock
SD1 Clock Frequency Period tCLK — ns

10.0
• OD mode
19.23
• SD mode
19.23
• MD mode
SD2 Clock Low Time tCL 0.46 x tCLK 0.54 x tCLK ns
SD3 Clock High Time tCH 0.46 x tCLK 0.54 x tCLK ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4 uSDHC Output Delay tOD –3 1 ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD7 uSDHC Input Hold Time tIH 1.5 — ns
4.6.8 CAN switching specifications

4.6.9 SINC timing

Table 77. SINC timing
Symbol Description Min Typ Max Unit Condition Spec

Number
MCLK External modulator clock 0.02 — 40 MHz — —

frequency
MMCLK Manchester modulator clock — — 15 MHz Clock recovered internally —

frequency using External Modulator
bit
NXP Semiconductors
Table 77. SINC timing (continued)
Symbol Description Min Typ Max Unit Condition Spec

Number
TS1 Setup time from data valid to 2 — — ns — —

clock high
TH1 Hold time from clock high to 2 — — ns — —

data valid

clock low
TH2 Hold time from clock low to data 2 — — ns — —

valid

clock high
TH3 Hold time from clock high to 2 — — ns — —

data valid

clock low
TH4 Hold time from clock low to data 2 — — ns — —

valid
Figure 39. SINC timing
4.6.10 I2S/SAI switching specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input).
All timing is given for non-inverted serial clock polarity (TCR2[BCP] = 0 and RCR2[BCP] = 0) and a non-inverted frame sync
(TCR4[FSP] = 0 and RCR4[FSP] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains
valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures.
All timing shown is also with respect to input signal transitions of 3 ns and a 50 pF maximum load.
NXP Semiconductors
Table 78. I2S/SAI master mode timing
Num. Characteristic Min. Max. Unit
S1 I2S_MCLK cycle time — ns

20
• OD mode
25
• SD mode
28.6
• MD mode
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 40 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 8.4 ns

I2S_RX_FS output valid
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 1 — ns
I2S_RX_FS output invalid
S7 I2S_TX_BCLK to I2S_TXD valid — 10 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 1 — ns
S9 I2S_RXD/I2S_RX_FS input setup before 14 — ns

I2S_RX_BCLK
15.6
• P2 and P3
• P1
S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns
S1 S2 S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/ S4
I2S_RX_BCLK (output) S4
S5 S6
I2S_TX_FS/
I2S_RX_FS (output)
S9 S10
I2S_TX_FS/
S7
I2S_RX_FS (input)
S7 S8
S8
I2S_TXD
S9 S10
I2S_RXD
Figure 40. I2S/SAI timing — master modes
NXP Semiconductors
Table 79. I2S/SAI slave mode timing
Num. Characteristic Min. Max. Unit
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) — ns

40
• OD mode
50
• SD mode
50
• MD mode
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period

(input)
S13 I2S_TX_FS/I2S_RX_FS input setup before 6 — ns

I2S_TX_BCLK/I2S_RX_BCLK
S14 I2S_TX_FS/I2S_RX_FS input hold after 2 — ns

I2S_TX_BCLK/I2S_RX_BCLK
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 20 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid -1.5 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 6 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion for I2S_TXD output valid 1 — 25 ns
1. Applies to first in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/ S12
I2S_RX_BCLK (input)
S15 S16
I2S_TX_FS/
I2S_RX_FS (output) S13 S14
I2S_TX_FS/
I2S_RX_FS (input) S15
S19
S15 S16 S16
I2S_TXD
S17 S18
I2S_RXD
Figure 41. I2S/SAI timing — slave modes
NXP Semiconductors
4.6.11 Flexible IO controller (FlexIO)

Table 80. FlexIO Timing Specifications
Symbol Description Min Typ Max Unit Notes
tODS Output delay skew between any two FlexIO_Dx pins configured 0 8 ns 1
as outputs that toggle on same internal clock cycle
tIDS Input delay skew between any two FlexIO_Dx pins configured as 0 8 ns 1
inputs that are sampled on the same internal clock cycle
1. Assumes pins muxed on same VDD_Px domain with same load
4.6.12 EMVSIM specifications

Each EMV SIM module interface consists of a total of five pins.
The interface is designed to be used with synchronous Smart cards, meaning the EMV SIM module provides the clock used by
the Smart card. The clock frequency is typically 372 times the Tx/Rx data rate; however, the EMV SIM module can also work with
CLK frequencies of 16 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the EMV SIM module provides to the Smart card is
used by the Smart card to recover the clock from the data in the same manner as standard UART data exchanges. All five signals
of the EMV SIM module are asynchronous with each other.
The smart card is initiated by the interface device; the Smart card responds with Answer to Reset. Although the EMV SIM
interface has no defined requirements, the ISO/IEC 7816 defines reset and power-down sequences (for detailed information see
ISO/IEC 7816).
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
SI8
EMVSIMn_IO
SI9
EMVSIMn_VCCEN
Figure 42. EMV SIM Clock Timing Diagram
The following table defines the general timing requirements for the EMV SIM interface.
NXP Semiconductors
Table 81. Timing Specifications, High Drive Strength
ID Parameter Symbol Min Max Unit
SI1 EMV SIM clock frequency (EMVSIMn_CLK)1 Sfreq 1 5 MHz
SI2 EMV SIM clock rise time (EMVSIMn_CLK)2 Srise — 0.08 × (1/Sfreq) ns
SI3 EMV SIM clock fall time (EMVSIMn_CLK)2 Sfall — 0.08 × (1/Sfreq) ns
SI4 EMV SIM input transition time Stran 20 25 ns

(EMVSIMn_IO, EMVSIMn_PD)
Si5 EMV SIM I/O rise time / fall time (EMVSIMn_IO)3 Tr/Tf — 0.8 μs
Si6 EMV SIM RST rise time / fall time (EMVSIMn_RST)4 Tr/Tf — 0.8 μs
1. 50 % duty cycle clock,

2. With C = 50 pF
3. With Cin = 30 pF, Cout = 30 pF,
4. With Cin = 30 pF,
4.6.12.1 EMVSIM Reset Sequences

Smart cards may have internal reset, or active low reset. The following subset describes the reset sequences in these two cases.
4.6.12.1.1 Smart Cards with Internal Reset

Following figure shows the reset sequence for Smart cards with internal reset. The reset sequence comprises the following steps:
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• The card must send a response on EMVSIMn_IO acknowledging the reset between 400–40000 clock cycles after T0.
EMVSIMn_VCCEN
EMVSIMn_CLK
EMVSIMn_IO RESPONSE
T0
Figure 43. Internal Reset Card Reset Sequence
The following table defines the general timing requirements for the SIM interface.
Table 82. Timing Specifications, Internal Reset Card Reset Sequence
Ref Min Max Units
1 — 200 EMVSIMx_CLK clock cycles
2 400 40,000 EMVSIMx_CLK clock cycles
NXP Semiconductors
4.6.12.1.2 Smart Cards with Active Low Reset

Following figure shows the reset sequence for Smart cards with active low reset. The reset sequence comprises the
following steps:
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• EMVSIMn_RST must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those
40,000 clock cycles)
• EMVSIMn_RST is asserted (at time T1)
• EMVSIMn_RST must remain asserted for at least 40,000 clock cycles after T1, and a response must be received on
EMVSIMn_IO between 400 and 40,000 clock cycles after T1.
EMVSIMn_VCCEN
EMVSIMn_RST
EMVSIMn_CLK
EMVSIMn_IO RESPONSE
1 2
3 3
T0 T1
Figure 44. Active-Low-Reset Smart Card Reset Sequence
The following table defines the general timing requirements for the EMVSIM interface.
Table 83. Timing Specifications, Internal Reset Card Reset Sequence
Ref No Min Max Units
1 — 200 EMVSIMx_CLK clock cycles
2 400 40,000 EMVSIMx_CLK clock cycles
3 40,000 — EMVSIMx_CLK clock cycles
4.6.12.2 EMVSIM Power-Down Sequence

Following figure shows the EMVSIM interface power-down AC timing diagram. Timing Requirements for Power-down Sequence
table shows the timing requirements for parameters (SI7–SI10) shown in the figure. The power-down sequence for the EMV SIM
interface is as follows:
• EMVSIMn_SIMPD port detects the removal of the Smart Card
• EMVSIMn_RST is negated
• EMVSIMn_CLK is negated
• EMVSIM_IO is negated
• EMVSIMx_VCCENy is negated
NXP Semiconductors
Each of the above steps requires one OSC32KCLK period (usually 32 kHz, also known as rtcclk in below figure). Power-down
may be initiated by a Smart card removal detection; or it may be launched by the processor.
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
SI8
EMVSIMn_IO
SI9
EMVSIMn_VCCEN
Figure 45. Smart Card Interface Power Down AC Timing
Table 84. Timing Requirements for Power-down Sequence
Ref No Parameter Symbol Min Max Units
SI7 EMVSIM reset to SIM clock stop Srst2clk 0.9 × 1/ 1.1 × 1/Frtcclk μs
Frtcclk1
SI8 EMVSIM reset to SIM Tx data low Srst2dat 1.8 × 1/Frtcclk 2.2 × 1/Frtcclk μs
SI9 EMVSIM reset to SIM voltage Srst2ven 2.7 × 1/Frtcclk 3.3 × 1/Frtcclk μs
enable low
SI10 EMVSIM presence detect to SIM Spd2rst 0.9 × 1/Frtcclk 1.1 × 1/Frtcclk μs
reset low
1. Frtcclk is OSC32KCLK, and this clock must be enabled during the power down sequence.
NOTE
Same timing is also followed when auto power down is initiated. See Reference Manual for reference.
4.6.13 Ethernet Controller (ENET) AC Electrical specifications
NXP Semiconductors
4.6.13.1 MII electrical specifications
Table 85. MII electrical specifications
Symbol Description Min Typ Max Unit Condition
tCYC_RX RX_CLK period1 40 / 400 ns 10/100 Mbps
ΔtCYC_RX RX_CLK duty cycle (tPWH / tCYC) 45 55 %
tS Input setup time to RX_CLK2 5 ns 10/100 Mbps
tH Input hold time to RX_CLK2 5 ns 10/100 Mbps
tCYC_TX TX_CLK period 3,1 40/400 ns 10/100 Mbps,

SRE[2:0] = 100
ΔtCYC_TX TX_CLK duty cycle (tPWH / tCYC)3 45 55 % SRE[2:0] = 100
tD Output delay from TX_CLK3 2 25 ns 10/100 Mbps,

SRE[2:0] = 100
1. MII is only supported in OD and SD mode.

2. Input timing assumes an input signal slew rate of 3 ns (20 %/80 %).
3. Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 Ohms,
unterminated, 5 inch microstrip trace on standard FR4 (1.5 pF/inch), (25 pF total with margin). For best signal integrity, the
series resistance of the transmission line should be matched closely to the RDSON of the I/O pad output driver
Figure 46. MII Receive Timing
Figure 47. MII Transmit Timing
NXP Semiconductors
4.6.13.2 RMII
RMII interface is matching RMII v1.2 specification. In RMII mode, the reference clock can be generated internally and provided
to the PHY through RCLK50M_OUT, or it comes from an external 50 MHz clock generator which is connected to the PHY and to
SoC through RCLK50M_IN pin.
Figure 48. RMII timing diagram
Timings in table below are covering both cases: reference clock generated internally or externally.
Table 86. RMII timing
ID Parameter Min Typ Max Unit
t1 Reference clock1 — 50 — MHz
Reference clock accuracy — — 50 ppm
Reference clock duty cycle 35 — 65 %
t2 RMII_TXEN, RMII_TXD output delay 2 — 16 ns
t3 RMII_CRS_DV, RMII_RXD setup time 4 — — ns
t4 RMII_CRS_DV, RMII_RXD hold time 2 — — ns
1. RMII is supported in OD and SD mode.
4.6.13.3 MDIO
MDIO is the control link used to configure Ethernet PHY connected to SoC.
NXP Semiconductors
Figure 49. MDIO timing diagram
Table 87. MDIO timing
ID Parameter Min Typ Max Unit
MDC frequency — 2.5 — MHz
t1 MDC high / low pulse width 180 — — %
t2 MDIO output delay 0 — 20 ns
t3 MDIO setup time 10 — — ns
t4 MDIO hold time 10 — — ns
4.7 Human Machine Interface (HMI) modules
4.7.1 Touch sensing input (TSI) electrical specifications

Table 88. TSI electrical Specs
IDD_EN Power consumption in – 500 600 µA

operation mode
IDD_DIS Power consumption in – 20 355 nA

disable mode
VBG Internal bandgap – 1.21 – V

reference voltage
VPRE Internal bias voltage – 1.51 – V
CI Internal integration capacitance – 90 – pF
FCLK Internal main clock frequency – 16 – MHz
4.7.2 Microphone (MIC)

The PDM microphones must meet the setup and hold timing requirements shown in Table 89 and Figure 50.The "k" factor value
in Table 89 depends on the selected quality mode as shown in Table 90 .
NXP Semiconductors
Table 89. Timing Parameters
Parameter Value
trs, tfs <=[floor (KxCLKDIV) −1]/[functional clock rate]1
trh, tfh >=0
1. Depending on K value, the user must make sure floor(K x CLKDIV) > 1 to avoid timing problems
Table 90. K factor value
Quality mode K factor
High Quality 1/2
Medium Quality, Very 1

Low Quality 0
Low Quality, Very Low 2

Quality 1
Very Low Quality 2 4
Figure 50. Input/Output Timing Requirements
4.7.3 General Purpose Input/Output (GPIO)

4.8 Security modules
4.8.1 Tamper
Table 91. Tamper electrical specifications
Temperature Tamper Detect assertion

• low temperature detect -38 -50 -64 °C
• high temperature detect 128 135 143 °C
NXP Semiconductors
Package dimensions
Table 91. Tamper electrical specifications (continued)
Temperature Tamper No flag range –37 125 °C
Low Voltage Detect Threshold 1.613 1.656 1.698 V
High Voltage Detect Threshold 3.65 3.75 3.848 V
Voltage Tamper Detect operational

temperature -38 125 °C
• no false alarms -64 143 °C
• with possible false alarms
5 Package dimensions
5.1 Obtaining package dimensions

Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number:
If you want the drawing for this package Then use this document number
184-pin VFBGA 98ASA01888D
100-pin HLQFP 98ASA01897D
6 Pinout
6.1 MCXNx4x Signal Multiplexing and Pin Assignments

The signal multiplexing and pin assignments are provided in an Excel file attached to this document:
1. Click the paperclip symbol on the left side of the PDF window.
2. Double-click on the Excel file to open it.
3. Select the “Pinout” tab.
The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
However, pinout table is also given below:
Table 92. Pinmux Assignments
Pin Name 184BGA ALL 100HLQFP N94X 100HLQFP N54X Pinmux Assignment Pad Settings Alternate Functions
P1_8 A1 1 1 ALT0 - P1_8 IO Supply - VDD ISP - UART_RXD
ALT1 - TRACE_DATA0 Pad type - MED+I2C+I3C ANALOG -

TSI0_CH17/ADC1_A8
ALT2 - FC4_P0 Default - DIS
VDD SYS -
ALT3 - FC5_P4
WUU0_IN10/LPTMR1_ALT3
ALT4 - CT_INP8
NXP Semiconductors
Pinout
Table 92. Pinmux Assignments (continued)
ALT5 - SCT0_OUT2
ALT6 - FLEXIO0_D16
ALT7 - SmartDMA_PIO4
ALT8 - PLU_OUT0
ALT9 - ENET0_TXD2
ALT10 - I3C1_SDA
P1_9 B1 2 2 ALT0 - P1_9 IO Supply - VDD ISP - UART_TXD
ALT1 - TRACE_DATA1 Pad type - MED+I2C ANALOG -

TSI0_CH18/ADC1_A9
ALT3 - FC5_P5
ALT4 - CT_INP9
ALT5 - SCT0_OUT3
ALT6 - FLEXIO0_D17
ALT8 - PLU_OUT1
ALT9 - ENET0_TXD3
ALT10 - I3C1_SCL
P1_10 C3 3 3 ALT0 - P1_10 IO Supply - VDD ISP - CAN_TXD
ALT1 - TRACE_DATA2 Pad type - MED ANALOG -

TSI0_CH19/ADC1_A10
ALT3 - FC5_P6
ALT4 - CT2_MAT0
ALT5 - SCT0_IN2
ALT6 - FLEXIO0_D18
ALT8 - PLU_IN0
ALT9 - ENET0_TXER
ALT11 - CAN0_TXD
P1_11 D3 4 4 ALT0 - P1_11 IO Supply - VDD ISP - CAN_RXD
ALT1 - TRACE_DATA3 Pad type - MED ANALOG -

TSI0_CH20/ADC1_A11
VDD SYS - WUU0_IN11
ALT4 - CT2_MAT1
ALT5 - SCT0_IN3
ALT6 - FLEXIO0_D19
ALT8 - PLU_IN1
ALT9 - ENET0_RX_CLK
NXP Semiconductors
Pinout
ALT10 - I3C1_PUR
ALT11 - CAN0_RXD
P1_12 D2 5 5 ALT0 - P1_12 IO Supply - VDD ANALOG -

TSI0_CH21/ADC1_A12
ALT1 - TRACE_CLK Pad type - MED
VDD SYS - WUU0_IN12
ALT3 - FC3_P0
ALT4 - CT2_MAT2
ALT5 - SCT0_OUT4
ALT6 - FLEXIO0_D20
ALT8 - PLU_OUT2
ALT9 - ENET0_RXER
ALT11 - CAN1_RXD

TSI0_CH22/ADC1_A13
ALT1 - TRIG_IN3 Pad type - MED
ALT3 - FC3_P1
ALT4 - CT2_MAT3
ALT5 - SCT0_OUT5
ALT6 - FLEXIO0_D21
ALT8 - PLU_OUT3
ALT9 - ENET0_RXDV
ALT11 - CAN1_TXD

TSI0_CH23/ADC1_A14
ALT2 - FC4_P6 Pad type - MED
ALT4 - CT_INP10
ALT5 - SCT0_IN4
ALT6 - FLEXIO0_D22
ALT8 - PLU_IN2
ALT9 - ENET0_RXD0
P1_15 E4 8 8 ALT0 - P1_15 IO Supply - VDD ANALOG -

TSI0_CH24/ADC1_A15
VDD SYS - WUU0_IN13
ALT4 - CT_INP11 Default - DIS
ALT5 - SCT0_IN5
NXP Semiconductors
Pinout
ALT6 - FLEXIO0_D23
ALT8 - PLU_IN3
ALT9 - ENET0_RXD1
ALT10 - I3C1_PUR
VSS P14 -- -- IO Supply - VDD
Pad type - VSSIO
P1_16 F6 -- -- ALT0 - P1_16 IO Supply - VDD ANALOG - ADC1_A16
ALT2 - FC5_P0 Pad type - MED+I2C+I3C VDD SYS - WUU0_IN14
ALT4 - CT_INP12
ALT5 - SCT0_OUT6
ALT6 - FLEXIO0_D24
ALT8 - PLU_OUT4
ALT9 - ENET0_RXD2
ALT10 - I3C1_SDA
P1_17 F4 -- -- ALT0 - P1_17 IO Supply - VDD ANALOG - ADC1_A17
ALT2 - FC5_P1 Pad type - MED+I2C
ALT4 - CT_INP13
ALT5 - SCT0_OUT7
ALT6 - FLEXIO0_D25
ALT8 - PLU_OUT5
ALT9 - ENET0_RXD3
ALT10 - I3C1_SCL
P1_18 G4 -- -- ALT0 - P1_18 IO Supply - VDD ANALOG - ADC1_A18
ALT1 - FREQME_CLK_IN0 Pad type - MED
ALT3 - FC3_P6
ALT4 - CT3_MAT0
ALT5 - SCT0_IN6
ALT6 - FLEXIO0_D26
ALT8 - PLU_IN4
ALT9 - ENET0_COL
NXP Semiconductors
Pinout
ALT11 - CAN0_TXD
P1_19 G5 -- -- ALT0 - P1_19 IO Supply - VDD ANALOG - ADC1_A19
ALT1 - FREQME_CLK_IN1 Pad type - MED VDD SYS - WUU0_IN15
ALT4 - CT3_MAT1
ALT5 - SCT0_IN7
ALT6 - FLEXIO0_D27
ALT8 - PLU_IN5
ALT9 - ENET0_CRS
ALT11 - CAN0_RXD
P1_20 K5 -- -- ALT0 - P1_20 IO Supply - VDD ANALOG -

ADC1_A20/CMP1_IN3
ALT3 - FC4_P0
ALT4 - CT3_MAT2
ALT5 - SCT0_OUT8
ALT6 - FLEXIO0_D28
ALT8 - PLU_OUT6
ALT9 - ENET0_MDC
ALT11 - CAN1_TXD
P1_21 L5 -- -- ALT0 - P1_21 IO Supply - VDD ANALOG -

ADC1_A21/CMP2_IN3
ALT1 - TRIG_OUT2 Pad type - MED
ALT3 - FC4_P1
ALT4 - CT3_MAT3
ALT5 - SCT0_OUT9
ALT6 - FLEXIO0_D29
ALT8 - PLU_OUT7
ALT9 - ENET0_MDIO
ALT10 - SAI1_MCLK
ALT11 - CAN1_RXD
P1_22 L4 -- -- ALT0 - P1_22 IO Supply - VDD ANALOG - ADC1_A22
NXP Semiconductors
Pinout
ALT3 - FC4_P2
ALT4 - CT_INP14
ALT5 - SCT0_OUT4
ALT6 - FLEXIO0_D30
P1_23 M4 -- -- ALT0 - P1_23 IO Supply - VDD ANALOG - ADC1_A23
ALT5 - SCT0_OUT5
ALT6 - FLEXIO0_D31
RESET_B F3 9 9 IO Supply - VDD
Pad type - RST
Default - RESET_B
P1_30 F1 10 10 ALT0 - P1_30 IO Supply - VDD ANALOG - XTAL48M
ALT5 - SCT0_OUT8
ALT10 - SAI0_MCLK
P1_31 F2 11 11 ALT0 - P1_31 IO Supply - VDD ANALOG - EXTAL48M
ALT5 - SCT0_OUT9
VSS D6 -- -- IO Supply - VDD
Pad type - VSSIO
VDD_CORE K10 12 12 IO Supply - VDD
Pad type - VDDINT
VDD_LDO_CORE K6 13 13 IO Supply - VDD ANALOG

- VDD_LDO_CORE
Pad type - VDDINT_3V
VDD H8 13 13 IO Supply - VDD
Pad type - VDDIO
VDD_P2 K8 13 13 IO Supply - VDD_P2
Pad type - VDDIO
VSS E5 -- -- IO Supply - VDD_P2
Pad type - VSSIO
NXP Semiconductors
Pinout
P2_0 H2 14 14 ALT0 - P2_0 IO Supply - VDD_P2
ALT1 - TRIG_IN5 Pad type - FAST
ALT3 - uSDHC0_D5
ALT4 - SCT0_IN0
ALT5 - PWM1_A3
ALT6 - FLEXIO0_D8
ALT8 - FLEXSPI0_B_SS1_b
ALT10 - SAI0_RX_BCLK
ALT1 - TRACE_CLK Pad type - FAST
ALT3 - uSDHC0_D4 Default - DIS
ALT4 - SCT0_IN1
ALT5 - PWM1_B3
ALT6 - FLEXIO0_D9
ALT8 - FLEXSPI0_B_DQS
ALT9 - SINC0_MCLK_OUT0
ALT10 - SAI0_RX_FS
P2_2 H3 16 16 ALT0 - P2_2 IO Supply - VDD_P2 VDD SYS - WUU0_IN16
ALT1 - CLKOUT Pad type - FAST
ALT3 - uSDHC0_D1
ALT4 - SCT0_OUT0
ALT5 - PWM1_A2
ALT6 - FLEXIO0_D10
ALT8 - FLEXSPI0_B_SS0_b
ALT9 - SINC0_MCLK0
ALT10 - SAI0_TXD0
P2_3 J3 17 17 ALT0 - P2_3 IO Supply - VDD_P2
ALT2 - FC9_P1 Pad type - FAST
ALT4 - SCT0_OUT1
ALT5 - PWM1_B2
ALT6 - FLEXIO0_D11
NXP Semiconductors
Pinout
ALT8 - FLEXSPI0_B_SCLK
ALT9 - SINC0_MBIT0
ALT10 - SAI0_RXD0
P2_4 K3 18 18 ALT0 - P2_4 IO Supply - VDD_P2 VDD SYS - WUU0_IN17
ALT3 - uSDHC0_CLK Default - DIS
ALT4 - SCT0_OUT2
ALT5 - PWM1_A1
ALT6 - FLEXIO0_D12
ALT8 - FLEXSPI0_B_DATA0
ALT9 - SINC0_MCLK1
ALT10 - SAI0_RXD1
P2_5 K1 19 19 ALT0 - P2_5 IO Supply - VDD_P2
ALT1 - TRIG_OUT3 Pad type - FAST
ALT3 - uSDHC0_CMD
ALT4 - SCT0_OUT3
ALT5 - PWM1_B1
ALT6 - FLEXIO0_D13
ALT9 - SINC0_MBIT1
ALT10 - SAI0_TXD1
VSS H5 -- -- IO Supply - VDD_P2
Pad type - VSSIO
VDD_P2 L7 -- -- IO Supply - VDD_P2
Pad type - VDDIO
P2_6 K2 20 20 ALT0 - P2_6 IO Supply - VDD_P2
ALT3 - uSDHC0_D3
ALT4 - SCT0_OUT4
ALT5 - PWM1_A0
ALT6 - FLEXIO0_D14
NXP Semiconductors
Pinout
ALT9 - SINC0_MCLK2
ALT10 - SAI0_TX_BCLK
P2_7 L2 21 21 ALT0 - P2_7 IO Supply - VDD_P2
ALT3 - uSDHC0_D2
ALT4 - SCT0_OUT5
ALT5 - PWM1_B0
ALT6 - FLEXIO0_D15
ALT9 - SINC0_MBIT2
ALT10 - SAI0_TX_FS
P2_8 M2 -- -- ALT0 - P2_8 IO Supply - VDD_P2
ALT1 - TRACE_DATA0 Pad type - FAST
ALT4 - SCT0_IN2
ALT5 - PWM1_X0
ALT6 - FLEXIO0_D16
ALT9 - SINC0_MCLK3
ALT10 - SAI1_TXD0
ALT4 - SCT0_IN3
ALT5 - PWM1_X1
ALT6 - FLEXIO0_D17
ALT9 - SINC0_MBIT3
ALT10 - SAI1_RXD0
NXP Semiconductors
Pinout
ALT4 - SCT0_IN4 Default - DIS
ALT5 - PWM1_X2
ALT6 - FLEXIO0_D18
ALT9 - SINC0_MCLK4
ALT10 - SAI1_RXD1
P2_11 N4 -- -- ALT0 - P2_11 IO Supply - VDD_P2
ALT4 - SCT0_IN5 Default - DIS
ALT5 - PWM1_X3
ALT6 - FLEXIO0_D19
ALT9 - SINC0_MBIT4
ALT10 - SAI1_TXD1
Pad type - VSSIO
VDD_P2 -- -- -- IO Supply - VDD_P2
Pad type - VDDIO
VDD_P4 P4 -- -- IO Supply - VDD_P4
Pad type - VDDIO
VSS_P4 P7 -- -- IO Supply - VDD_P4
Pad type - VSSIO
P4_0 P1 -- -- ALT0 - P4_0 IO Supply - VDD_P4 VDD SYS - WUU0_IN18
ALT1 - TRIG_IN6 Pad type - SLOW
ALT4 - CT_INP16
ALT8 - PLU_IN0
ALT9 - SINC0_MCLK3
ANA_0 P3 -- -- IO Supply - VDD_P4 ANALOG - ADC0_A0
Pad type - ANA
P4_0/ANA_0 -- 22 22 ALT0 - P4_0 IO Supply - VDD_P4 ANALOG - ADC0_A0
ALT1 - TRIG_IN6 Pad type - SLOW VDD SYS - WUU0_IN18
NXP Semiconductors
Pinout
ALT4 - CT_INP16
ALT8 - PLU_IN0
ALT9 - SINC0_MCLK3
ANA_1 R3 -- -- IO Supply - VDD_P4 ANALOG - ADC0_B0
Pad type - ANA
P4_1 P2 -- -- ALT0 - P4_1 IO Supply - VDD_P4
ALT4 - CT_INP17
ALT8 - PLU_IN1
P4_1/ANA_1 -- 23 23 ALT0 - P4_1 IO Supply - VDD_P4 ANALOG - ADC0_B0
ALT4 - CT_INP17
ALT8 - PLU_IN1
P4_2 T1 24 24 ALT0 - P4_2 IO Supply - VDD_P4 ANALOG

- DAC0_OUT/ADC0_A4/
ADC1_A4/CMP0_IN4N/
CMP1_IN4N/CMP2_IN4N
ALT4 - CT_INP12
ALT8 - PLU_IN2
ALT9 - SINC0_MBIT3
P4_3 U1 25 25 ALT0 - P4_3 IO Supply - VDD_P4 ANALOG

- DAC1_OUT/ADC0_B4/
ADC1_B4/CMP0_IN5N/
CMP1_IN5N/CMP2_IN5N
ALT4 - CT_INP13
VDD SYS - WUU0_IN19
ALT8 - PLU_IN3
ALT2 - FC2_P4 Pad type - SLOW
ALT8 - PLU_IN4
NXP Semiconductors
Pinout
ALT9 - SINC0_MCLK4
ANA_4 T2 -- -- IO Supply - VDD_P4 ANALOG - ADC1_A0
Pad type - ANA
P4_4/ANA_4 -- 26 26 ALT0 - P4_4 IO Supply - VDD_P4 ANALOG - ADC1_A0
ALT8 - PLU_IN4
ALT9 - SINC0_MCLK4
ANA_5 T3 -- -- IO Supply - VDD_P4 ANALOG - ADC1_B0
Pad type - ANA
ALT8 - PLU_IN5
ALT9 - SINC0_MBIT4
P4_5/ANA_5 -- 27 27 ALT0 - P4_5 IO Supply - VDD_P4 ANALOG - ADC1_B0
ALT8 - PLU_IN5
ALT9 - SINC0_MBIT4
ANA_6 U2 -- -- IO Supply - VDD_P4 ANALOG - DAC2_OUT/

ADC0_A3/ADC1_A3
Pad type - ANA
ALT1 - TRIG_OUT4 Pad type - SLOW
ALT4 - CT_INP18
ALT8 - PLU_CLK
P4_6/ANA_6 -- 28 28 ALT0 - P4_6 IO Supply - VDD_P4 ANALOG - DAC2_OUT/

ADC0_A3/ADC1_A3
ALT4 - CT_INP18
NXP Semiconductors
Pinout
ALT8 - PLU_CLK
P4_7 T4 -- -- ALT0 - P4_7 IO Supply - VDD_P4
ALT4 - CT_INP19 Pad type - SLOW
ALT7 - SmartDMA_PIO31 Default - DIS
ANA_7 U4 -- -- IO Supply - VDD_P4 ANALOG - VREFI/VREFO/

ADC0_A7/ADC1_A7
Pad type - ANA
P4_7/ANA_7 -- 29 29 ALT0 - P4_7 IO Supply - VDD_P4 ANALOG - VREFI/VREFO/

ADC0_A7/ADC1_A7
ALT4 - CT_INP19 Pad type - SLOW
ALT7 - SmartDMA_PIO31 Default - DIS
VDD_ANA R4 30 30 IO Supply - VDD_P4
VREFH R5 31 31 IO Supply - VDD_P4 ANALOG - VREFH
Pad type - ANA
VREFL R6 32 32 IO Supply - VDD_P4 ANALOG - VREFL
Pad type - VSSINT
VSS_P4 P6 33 33 IO Supply - VDD_P4
Pad type - VSSIO
VDD_P4 N5 34 34 IO Supply - VDD_P4
Pad type - VDDIO
P4_12 T6 35 35 ALT0 - P4_12 IO Supply - VDD_P4 ISP - USB0_VBUS_DET
ALT1 - USB0_VBUS_DET Pad type - SLOW ANALOG - OPAMP0_INP0/

ADC0_A5/ADC1_A5
VDD SYS - WUU0_IN20
ALT4 - CT4_MAT0
ALT6 - FLEXIO0_D20
ALT8 - PLU_OUT0
ALT9 - SINC0_MCLK0
ALT11 - CAN0_RXD
P4_13 T7 -- -- ALT0 - P4_13 IO Supply - VDD_P4 ANALOG - OPAMP0_INP1/

ADC0_B5/ADC1_B5
ALT3 - USB1_OTGn_ID
ALT4 - CT4_MAT1
ALT6 - FLEXIO0_D21
ALT8 - PLU_OUT1
ALT9 - SINC0_MBIT0
NXP Semiconductors
Pinout
ALT11 - CAN0_TXD
ANA_14 U6 -- -- IO Supply - VDD_P4 ANALOG - OPAMP0_INN
Pad type - LOLK
P4_13/ANA_14 -- 36 36 ALT0 - P4_13 IO Supply - VDD_P4 ANALOG

- OPAMP0_INP1/ADC0_B5/
ADC1_B5/OPAMP0_INN
ALT3 - USB1_OTGn_ID
ALT4 - CT4_MAT1
ALT6 - FLEXIO0_D21
ALT8 - PLU_OUT1
ALT9 - SINC0_MBIT0
ALT11 - CAN0_TXD
ALT4 - CT4_MAT2 Pad type - SLOW
ALT6 - FLEXIO0_D22 Default - DIS
ALT8 - PLU_OUT2
P4_15 T8 37 37 ALT0 - P4_15 IO Supply - VDD_P4 ANALOG - OPAMP0_OUT/

ADC0_A1/CMP0_IN4P
VDD SYS - WUU0_IN21
ALT3 Default - DIS
- USB1_VBUSVALID_EXT
ALT4 - CT4_MAT3
ALT6 - FLEXIO0_D23
ALT8 - PLU_OUT3
ALT11 - CAN1_RXD
P4_16 R8 38 38 ALT0 - P4_16 IO Supply - VDD_P4 ANALOG -

OPAMP1_INP0/ADC0_A6
ALT3 - USB1_OTGn_PWR Default - DIS
ALT4 - CT3_MAT0
ALT6 - FLEXIO0_D24
ALT8 - PLU_OUT4
ALT9 - SINC0_MCLK1
ALT11 - CAN1_TXD
P4_17 R9 -- -- ALT0 - P4_17 IO Supply - VDD_P4 ANALOG -

OPAMP1_INP1/ADC0_B6
NXP Semiconductors
Pinout
ALT3 - USB1_OTGn_OC
ALT4 - CT3_MAT1
ALT6 - FLEXIO0_D25
ALT8 - PLU_OUT5
ALT9 - SINC0_MBIT1
Pad type - LOLK
P4_17/ANA_18 -- 39 39 ALT0 - P4_17 IO Supply - VDD_P4 ANALOG - OPAMP1_INP1/

ADC0_B6/OPAMP1_INN
ALT3 - USB1_OTGn_OC
ALT4 - CT3_MAT1
ALT6 - FLEXIO0_D25
ALT8 - PLU_OUT5
ALT9 - SINC0_MBIT1
ALT8 - PLU_OUT6
P4_19 R10 40 -- ALT0 - P4_19 IO Supply - VDD_P4 ANALOG - OPAMP1_OUT/

ADC0_B1/CMP1_IN4P
ALT4 - CT3_MAT3 Default - DIS
ALT6 - FLEXIO0_D27
ALT8 - PLU_OUT7
P4_20 T10 41 -- ALT0 - P4_20 IO Supply - VDD_P4 ANALOG -

OPAMP2_INP0/ADC1_A6
ALT4 - CT2_MAT0
ALT6 - FLEXIO0_D28
ALT9 - SINC0_MCLK2
P4_21 T11 -- -- ALT0 - P4_21 IO Supply - VDD_P4 ANALOG -

OPAMP2_INP1/ADC1_B6
ALT4 - CT2_MAT1
ALT6 - FLEXIO0_D29
NXP Semiconductors
Pinout
ALT9 - SINC0_MBIT2
Pad type - LOLK
-- 42 -- ALT0 - P4_21 IO Supply - VDD_P4 ANALOG - OPAMP2_INP1/

ADC1_B6/OPAMP2_INN
ALT4 - CT2_MAT1
ALT6 - FLEXIO0_D29
ALT9 - SINC0_MBIT2
P4_22 T12 -- -- ALT0 - P4_22 IO Supply - VDD_P4
P4_23 U12 43 -- ALT0 - P4_23 IO Supply - VDD_P4 ANALOG - OPAMP2_OUT/

ADC0_A2/ADC0_B2/
ADC1_B3/CMP2_IN4P
ALT4 - CT2_MAT3
ALT6 - FLEXIO0_D31
VSS_P4 P9 -- -- IO Supply - VDD_P4
Pad type - VSSIO
Pad type - VDDIO
VSS J4 -- -- IO Supply - VDD_USB
Pad type - VSSIO
USB1_DP R13 -- 40 IO Supply - VDD_USB ANALOG - USB1_DP
Pad type - ANA
USB1_DM R14 -- 41 IO Supply - VDD_USB ANALOG - USB1_DM
Pad type - ANA
USB1_ID P11 -- -- IO Supply - VDD_USB ANALOG - USB1_ID
Pad type - ANA
USB1_VBUS U14 -- 42 IO Supply - VDD_USB ANALOG - USB1_VBUS
VSS J8 -- 43 IO Supply - VDD_USB
Pad type - VSSIO
NXP Semiconductors
Pinout
VDD_USB R12 44 44 IO Supply - VDD_USB
Pad type - VDDIO
USB0_DM T14 45 45 IO Supply - VDD_USB ANALOG - USB0_DM
Pad type - ANA VDD SYS - WUU0_IN28
USB0_DP T15 46 46 IO Supply - VDD_USB ANALOG - USB0_DP
Pad type - ANA VDD SYS - WUU0_IN29
VSS T16 -- -- IO Supply - VDD_BAT
Pad type - VSSIO
VDD_BAT T17 47 47 IO Supply - VDD_BAT
Pad type - VDDIO
P5_0 U16 48 48 ALT0 - P5_0 IO Supply - VDD_BAT ANALOG -

EXTAL32K/ADC1_B8
ALT1 - TRIG_IN10 Pad type - AON
ALT2 - LPTMR0_ALT2 Default - DIS
P5_1 U17 49 49 ALT0 - P5_1 IO Supply - VDD_BAT ANALOG -

XTAL32K/ADC1_B9
ALT1 - TRIG_OUT6 Pad type - AON
P5_2 M10 50 50 ALT0 - P5_2 IO Supply - VDD_BAT ANALOG - ADC1_B10
ALT1 - VBAT_WAKEUP_b Pad type - RST
ALT2 - SPC_LPREQ Default - ALT1
ALT3 - TAMPER0
P5_3 N11 51 51 ALT0 - P5_3 IO Supply - VDD_BAT ANALOG - ADC1_B11
ALT2 - RTC_CLKOUT Default - DIS
ALT3 - TAMPER1
P5_4 M12 -- -- ALT0 - P5_4 IO Supply - VDD_BAT ANALOG - ADC1_B12
ALT2 - SPC_LPREQ Default - DIS
ALT3 - TAMPER2
P5_5 K12 -- -- ALT0 - P5_5 IO Supply - VDD_BAT ANALOG - ADC1_B13
ALT3 - TAMPER3
P5_6 K13 -- -- ALT0 - P5_6 IO Supply - VDD_BAT ANALOG - ADC1_B14
NXP Semiconductors
Pinout
ALT3 - TAMPER4
P5_7 L13 -- -- ALT0 - P5_7 IO Supply - VDD_BAT ANALOG - ADC1_B15
ALT3 - TAMPER5 Default - DIS
P5_8 L14 -- -- ALT0 - P5_8 IO Supply - VDD_BAT ANALOG - ADC1_B16
ALT3 - TAMPER6 Default - DIS
P5_9 M14 -- -- ALT0 - P5_9 IO Supply - VDD_BAT ANALOG - ADC1_B17
ALT3 - TAMPER7 Pad type - AON
Default - DIS
VSS E19 -- -- IO Supply - VDD_BAT
Pad type - VSSIO
VSS_DCDC P16 52 52 IO Supply - VDD_DCDC
Pad type - VSSIO
DCDC_LX P17 53 53 IO Supply - VDD_DCDC ANALOG - DCDC_LX
Pad type - ANA
VDD_DCDC R15 54 54 IO Supply - VDD_DCDC
Pad type - VDDIO
VDD_LDO_SYS P15 54 54 IO Supply - VDD_P3
Pad type - VDDIO
VDD_SYS N14 55 55 IO Supply - VDD_P3
Pad type - VDDINT
VSS J14 -- -- IO Supply - VDD_P3
Pad type - VSSIO
ALT5 - PWM1_X3
ALT6 - FLEXIO0_D31
ALT10 - SAI1_TXD1
ALT4 - CT_INP10
NXP Semiconductors
Pinout
ALT5 - PWM1_X2
ALT6 - FLEXIO0_D30
ALT9 - SIM0_VCCEN
ALT10 - SAI1_RXD1
P3_21 L16 56 56 ALT0 - P3_21 IO Supply - VDD_P3
ALT3 - FC6_P1
ALT4 - CT2_MAT3
ALT5 - PWM1_B3
ALT6 - FLEXIO0_D29
ALT9 - SIM0_RST
ALT10 - SAI1_RXD0
ALT11 - PF_SPI_CS1_DIS_n
P3_20 M17 57 57 ALT0 - P3_20 IO Supply - VDD_P3 VDD SYS - WUU0_IN27
ALT3 - FC6_P0
ALT4 - CT2_MAT2
ALT5 - PWM1_A3
ALT6 - FLEXIO0_D28
ALT9 - SIM0_PD
ALT10 - SAI1_TXD0
ALT11 - PF_SPI_CS0_DIS_n
P3_19 K17 -- -- ALT0 - P3_19 IO Supply - VDD_P3
ALT5 - PWM1_X1
ALT6 - FLEXIO0_D27
ALT10 - SAI1_RX_FS
VSS K9 -- -- IO Supply - VDD_P3
Pad type - VSSIO
NXP Semiconductors
Pinout
VDD_CORE L11 58 58 IO Supply - VDD_P3
Pad type - VDDINT
VDD_P3 G11 59 59 IO Supply - VDD_P3
Pad type - VDDIO
P3_18 K16 -- -- ALT0 - P3_18 IO Supply - VDD_P3
ALT5 - PWM1_X0
ALT6 - FLEXIO0_D26
P3_17 K15 60 60 ALT0 - P3_17 IO Supply - VDD_P3 VDD SYS - WUU0_IN26
ALT5 - PWM1_B2
ALT6 - FLEXIO0_D25
ALT9 - SIM0_IO
ALT10 - SAI1_TX_FS
P3_16 J15 61 61 ALT0 - P3_16 IO Supply - VDD_P3
ALT5 - PWM1_A2
ALT6 - FLEXIO0_D24
ALT9 - SIM0_CLK
ALT5 - PWM1_B1
ALT6 - FLEXIO0_D23
ALT8 - FLEXSPI0_A_DATA7
ALT10 - SAI0_RX_FS
ALT11 - PF_SPI_SCKIN
NXP Semiconductors
Pinout
P3_14 H17 63 63 ALT0 - P3_14 IO Supply - VDD_P3 VDD SYS - WUU0_IN25
ALT5 - PWM1_A1
ALT6 - FLEXIO0_D22
ALT11 - PF_SPI_DATA
ALT4 - CT1_MAT3
ALT5 - PWM1_B0
ALT6 - FLEXIO0_D21
ALT10 - SAI0_TXD1
ALT11 - PF_SPI_CS0_n
P3_12 G16 65 65 ALT0 - P3_12 IO Supply - VDD_P3
ALT4 - CT1_MAT2
ALT5 - PWM1_A0
ALT6 - FLEXIO0_D20
ALT10 - SAI0_RXD1
VSS N13 -- -- IO Supply - VDD_P3
Pad type - VSSIO
VDD_P3 H10 66 66 IO Supply - VDD_P3
Pad type - VDDIO
P3_11 F16 67 67 ALT0 - P3_11 IO Supply - VDD_P3 VDD SYS - WUU0_IN24
ALT4 - CT1_MAT1
NXP Semiconductors
Pinout
ALT5 - PWM0_B3
ALT6 - FLEXIO0_D19
ALT9 - SIM0_IO
ALT10 - SAI0_RXD0
ALT11 - PF_QSPI_DATA3
P3_10 F17 68 68 ALT0 - P3_10 IO Supply - VDD_P3
ALT4 - CT1_MAT0
ALT5 - PWM0_A3
ALT6 - FLEXIO0_D18
ALT9 - SIM0_CLK
ALT10 - SAI0_TXD0
P3_9 F15 69 69 ALT0 - P3_9 IO Supply - VDD_P3
ALT4 - CT_INP5
ALT5 - PWM0_B2
ALT6 - FLEXIO0_D17
ALT9 - SIM0_RST
ALT10 - SAI0_TX_FS
P3_8 E14 70 70 ALT0 - P3_8 IO Supply - VDD_P3 VDD SYS - WUU0_IN23
ALT4 - CT_INP4
ALT5 - PWM0_A2
ALT6 - FLEXIO0_D16
NXP Semiconductors
Pinout
ALT9 - SIM0_PD
P3_7 D14 71 71 ALT0 - P3_7 IO Supply - VDD_P3
ALT4 - CT4_MAT3
ALT5 - PWM0_B1
ALT6 - FLEXIO0_D15
ALT8 - FLEXSPI0_A_SCLK
ALT9 - SIM0_VCCEN
ALT10 - SAI0_MCLK
ALT11 - PF_QSPI_SCKIN
P3_6 D17 72 72 ALT0 - P3_6 IO Supply - VDD_P3
ALT1 - CLKOUT Pad type - FAST
ALT4 - CT4_MAT2
ALT5 - PWM0_A1
ALT6 - FLEXIO0_D14
ALT8 - FLEXSPI0_A_DQS
ALT9 - SIM1_VCCEN
ALT10 - SAI1_MCLK
ALT11 - PF_QSPI_CS_n
VSS P12 -- -- IO Supply - VDD_P3
Pad type - VSSIO
VDD_P3 H12 73 73 IO Supply - VDD_P3
Pad type - VDDIO
P3_5 G14 -- -- ALT0 - P3_5 IO Supply - VDD_P3
ALT5 - PWM0_X3
ALT6 - FLEXIO0_D13
ALT9 - SIM1_IO
NXP Semiconductors
Pinout
P3_4 F14 -- -- ALT0 - P3_4 IO Supply - VDD_P3
ALT5 - PWM0_X2
ALT6 - FLEXIO0_D12
ALT9 - SIM1_CLK
P3_3 D16 -- -- ALT0 - P3_3 IO Supply - VDD_P3
ALT5 - PWM0_X1
ALT6 - FLEXIO0_D11
ALT9 - SIM1_RST
P3_2 D15 -- -- ALT0 - P3_2 IO Supply - VDD_P3
ALT5 - PWM0_X0
ALT6 - FLEXIO0_D10
ALT9 - SIM1_PD
P3_1 C15 74 74 ALT0 - P3_1 IO Supply - VDD_P3
ALT3 - FC7_P6
ALT4 - CT_INP17
ALT5 - PWM0_B0
ALT6 - FLEXIO0_D9
ALT8 - FLEXSPI0_A_SS1_b
ALT11 - PF_QSPI_CS1_DIS
P3_0 B17 75 75 ALT0 - P3_0 IO Supply - VDD_P3 VDD SYS - WUU0_IN22
ALT4 - CT_INP16
ALT5 - PWM0_A0
ALT6 - FLEXIO0_D8
NXP Semiconductors
Pinout
ALT8 - FLEXSPI0_A_SS0_b
ALT11 - PF_QSPI_CS0_DIS
Pad type - VSSIO
Pad type - VDDIO
VDD -- -- -- IO Supply - VDD
Pad type - VDDIO
VSS J10 -- -- IO Supply - VDD
Pad type - VSSIO
P0_0 A17 76 76 ALT0 - P0_0 IO Supply - VDD
ALT1 - TMS/SWDIO Pad type - MED
ALT2 - FC1_P0 Default - ALT1
ALT4 - CT_INP0
P0_1 A16 77 77 ALT0 - P0_1 IO Supply - VDD
ALT1 - TCLK/SWCLK Pad type - MED
ALT4 - CT_INP1
P0_2 B16 78 78 ALT0 - P0_2 IO Supply - VDD
ALT1 - TDO/SWO Pad type - MED
ALT4 - CT0_MAT0
ALT5 - UTICK_CAP0
ALT10 - I3C0_PUR
P0_3 B15 79 79 ALT0 - P0_3 IO Supply - VDD ANALOG - CMP1_IN1
ALT1 - TDI Pad type - MED
ALT4 - CT0_MAT1
ALT5 - UTICK_CAP1
ALT8 - HSCMP0_OUT
P0_4 B14 80 80 ALT0 - P0_4 IO Supply - VDD ANALOG - TSI0_CH8
ALT1 - EWM0_IN Pad type - MED+I2C VDD SYS - WUU0_IN0
ALT3 - FC1_P4
NXP Semiconductors
Pinout
ALT4 - CT0_MAT2
ALT5 - UTICK_CAP2
ALT8 - HSCMP1_OUT
ALT9 - PDM0_CLK
P0_5 A14 81 81 ALT0 - P0_5 IO Supply - VDD ANALOG - TSI0_CH9
ALT1 - EWM0_OUT_b Pad type - MED+I2C
ALT3 - FC1_P5
ALT4 - CT0_MAT3
ALT5 - UTICK_CAP3
ALT9 - PDM0_DATA0
P0_6 C14 82 82 ALT0 - P0_6 IO Supply - VDD ISP - ISPMODE_N
ALT1 - ISPMODE_N Pad type - MED ANALOG - TSI0_CH10
ALT3 - FC1_P6
ALT4 - CT_INP2
ALT8 - HSCMP2_OUT
ALT9 - PDM0_DATA1
P0_7 C13 -- -- ALT0 - P0_7 IO Supply - VDD ANALOG - CMP2_IN1
ALT2 - FC0_P3 Pad type - MED VDD SYS - WUU0_IN1
P0_8 C12 -- -- ALT0 - P0_8 IO Supply - VDD ANALOG - ADC0_B8
ALT6 - FLEXIO0_D0
P0_9 A12 -- -- ALT0 - P0_9 IO Supply - VDD ANALOG - ADC0_B9
ALT6 - FLEXIO0_D1
P0_10 B12 -- -- ALT0 - P0_10 IO Supply - VDD ANALOG - ADC0_B10
ALT6 - FLEXIO0_D2
ALT4 - CT0_MAT1 Pad type - MED
NXP Semiconductors
Pinout
ALT8 - HSCMP2_OUT
VDD G7 83 83 IO Supply - VDD
Pad type - VDDIO
Pad type - VSSIO
P0_12 D11 -- -- ALT0 - P0_12 IO Supply - VDD ANALOG -

ADC0_B12/NVM_TM0
ALT4 - CT0_MAT2
ALT6 - FLEXIO0_D4
P0_13 F12 -- -- ALT0 - P0_13 IO Supply - VDD ANALOG -

ADC0_B13/NVM_TM1
ALT4 - CT0_MAT3
ALT6 - FLEXIO0_D5
P0_14 E11 -- -- ALT0 - P0_14 IO Supply - VDD ANALOG -

ADC0_B14/NVM_TM2
ALT4 - CT_INP2
ALT5 - UTICK_CAP0
ALT6 - FLEXIO0_D6
P0_15 G13 -- -- ALT0 - P0_15 IO Supply - VDD ANALOG -

ADC0_B15/NVM_TM3
ALT5 - UTICK_CAP1
ALT6 - FLEXIO0_D7
P0_16 B10 84 84 ALT0 - P0_16 IO Supply - VDD ISP - I2C_SDA
ALT2 - FC0_P0 Pad type - MED+I2C+I3C ANALOG -

TSI0_CH11/ADC0_A8
VDD SYS - WUU0_IN2
ALT5 - UTICK_CAP2
ALT6 - FLEXIO0_D0
ALT9 - PDM0_CLK
ALT10 - I3C0_SDA
P0_17 A10 85 85 ALT0 - P0_17 IO Supply - VDD ISP - I2C_SCL
ALT2 - FC0_P1 Pad type - MED+I2C ANALOG -

TSI0_CH12/ADC0_A9
NXP Semiconductors
Pinout
ALT5 - UTICK_CAP3
ALT6 - FLEXIO0_D1
ALT9 - PDM0_DATA0
ALT10 - I3C0_SCL
P0_18 C10 86 86 ALT0 - P0_18 IO Supply - VDD ANALOG -

TSI0_CH13/ADC0_A10
ALT1 - EWM0_IN Pad type - MED
ALT4 - CT0_MAT2
ALT6 - FLEXIO0_D2
ALT8 - HSCMP0_OUT
ALT9 - PDM0_DATA1

TSI0_CH14/ADC0_A11
ALT1 - EWM0_OUT_b Pad type - MED
VDD SYS - WUU0_IN3
ALT4 - CT0_MAT3
ALT6 - FLEXIO0_D3
ALT8 - HSCMP1_OUT

TSI0_CH15/ADC0_A12
ALT2 - FC0_P4 Pad type - MED+I2C+I3C
VDD SYS - WUU0_IN4
ALT4 - CT_INP0
ALT6 - FLEXIO0_D4
ALT10 - I3C0_SDA
P0_21 A8 89 89 ALT0 - P0_21 IO Supply - VDD ANALOG -

TSI0_CH16/ADC0_A13
ALT2 - FC0_P5 Pad type - MED+I2C
ALT4 - CT_INP1
ALT6 - FLEXIO0_D5
ALT10 - I3C0_SCL
P0_22 B8 90 90 ALT0 - P0_22 IO Supply - VDD ANALOG -

ADC0_A14/CMP1_IN2
ALT1 - EWM0_IN Pad type - MED
ALT3 - FC1_P2
ALT4 - CT_INP2
ALT6 - FLEXIO0_D6
ALT10 - I3C0_PUR
NXP Semiconductors
Pinout

ADC0_A15/CMP2_IN2
ALT1 - EWM0_OUT_b Pad type - MED
VDD SYS - WUU0_IN5
ALT4 - CT_INP3
ALT6 - FLEXIO0_D7
VSS H13 -- -- IO Supply - VDD
Pad type - VSSIO
P0_25 A6 -- -- ALT0 - P0_25 IO Supply - VDD ANALOG - ADC0_B17
P0_26 F10 -- -- ALT0 - P0_26 IO Supply - VDD ANALOG - ADC0_B18
P0_27 E10 -- -- ALT0 - P0_27 IO Supply - VDD ANALOG - ADC0_B19
ALT4 - CT_INP0
P0_29 F8 -- -- ALT0 - P0_29 IO Supply - VDD ANALOG - ADC0_B21
ALT4 - CT_INP1
ALT4 - CT_INP2
P0_31 D7 -- -- ALT0 - P0_31 IO Supply - VDD ANALOG - ADC0_B23
ALT4 - CT_INP3 Pad type - MED
Default - DIS
P1_0 C6 92 92 ALT0 - P1_0 IO Supply - VDD ISP - SPI_SDO
NXP Semiconductors
Pinout
ALT1 - TRIG_IN0 Pad type - MED+I2C ANALOG - TSI0_CH0/

ADC0_A16/CMP0_IN0
VDD SYS -
ALT3 - FC4_P4
WUU0_IN6/LPTMR0_ALT3
ALT4 - CT_INP4
ALT5 - SCT0_OUT6
ALT6 - FLEXIO0_D8
P1_1 C5 93 93 ALT0 - P1_1 IO Supply - VDD ISP - SPI_SCK
ALT1 - TRIG_IN1 Pad type - MED+I2C ANALOG - TSI0_CH1/

ADC0_A17/CMP1_IN0
ALT3 - FC4_P5
ALT4 - CT_INP5
ALT5 - SCT0_OUT7
ALT6 - FLEXIO0_D9
ALT10 - SAI1_TX_FS
P1_2 C4 94 94 ALT0 - P1_2 IO Supply - VDD ISP - SPI_SDI
ALT1 - TRIG_OUT0 Pad type - MED ANALOG - TSI0_CH2/

ADC0_A18/CMP2_IN0
ALT3 - FC4_P6
ALT4 - CT1_MAT0
ALT5 - SCT0_IN6
ALT6 - FLEXIO0_D10
ALT9 - ENET0_MDC
ALT10 - SAI1_TXD0
ALT11 - CAN0_TXD
P1_3 B4 95 95 ALT0 - P1_3 IO Supply - VDD ISP - SPI_PCS
ALT1 - TRIG_OUT1 Pad type - MED ANALOG - TSI0_CH3/

ADC0_A19/CMP0_IN1
VDD SYS - WUU0_IN7
ALT4 - CT1_MAT1
ALT5 - SCT0_IN7
ALT6 - FLEXIO0_D11
ALT9 - ENET0_MDIO
ALT10 - SAI1_RXD0
ALT11 - CAN0_RXD
VDD H6 96 96 IO Supply - VDD
Pad type - VDDIO
NXP Semiconductors
Pinout
Pad type - VSSIO
P1_4 A4 97 97 ALT0 - P1_4 IO Supply - VDD ANALOG - TSI0_CH4/

ADC0_A20/CMP0_IN2
VDD SYS - WUU0_IN8
ALT3 - FC5_P0
ALT4 - CT1_MAT2
ALT5 - SCT0_OUT0
ALT6 - FLEXIO0_D12
ALT9 - ENET0_TX_CLK
ALT10 - SAI0_TXD1
P1_5 B3 98 98 ALT0 - P1_5 IO Supply - VDD ANALOG - TSI0_CH5/

ADC0_A21/CMP0_IN3
ALT3 - FC5_P1
ALT4 - CT1_MAT3
ALT5 - SCT0_OUT1
ALT6 - FLEXIO0_D13
ALT9 - ENET0_TXEN
ALT10 - SAI0_RXD1

TSI0_CH6/ADC0_A22
ALT3 - FC5_P2
ALT4 - CT_INP6
ALT5 - SCT0_IN0
ALT6 - FLEXIO0_D14
ALT9 - ENET0_TXD0
ALT11 - CAN1_TXD
P1_7 A2 100 100 ALT0 - P1_7 IO Supply - VDD ANALOG -

TSI0_CH7/ADC0_A23
VDD SYS - WUU0_IN9
ALT4 - CT_INP7
NXP Semiconductors
Pinout
ALT5 - SCT0_IN1
ALT6 - FLEXIO0_D15
ALT8 - PLU_CLK
ALT9 - ENET0_TXD1
ALT10 - SAI1_RX_FS
ALT11 - CAN1_RXD
Note:
1. For BGA package, all balls with same name are shorted together on BGA package.
2. VSS_ANA and VSS_P4 are shorted together on package.
3. +I3C in Pad Type represents strong pull up resistor is implemented on the pin. PV bit is implemented in the Pin Control register
of the pin.
4. +I2C in Pad Type represents I2C filter is implemented on the pin. PFE bit is implemented in the Pin Control register of the pin
5. DIS in default column means the pin's input buffer is disabled by default
6. AON and RST pads support passive filter. PFE bit is implemented in the Pin Control register of the pin
7. PE, PS, SRE, ODE and DSE are supported in the Pin Control register of all types of IO
6.2 MCXNx4x Pinout Diagrams

The pinout diagrams are provided in an Excel file attached to this document:
1. Click the paperclip symbol on the left side of the PDF window.
2. Double-click on the Excel file to open it.
3. Select the respective package tab.
Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, refer to the "Pinout" tab
in the Excel file.
6.3 Recommended connection for unused analog and digital pins

Table 93 shows the recommended connections for pins if those pins are not used in the customer's application
Table 93. Recommended connection for unused interfaces
Pin Type Pin Name Recommendation Comments
Power VDD_LDO_CORE Connect to When the LDO_CORE is bypassed, the input

VDD_CORE VDD_LDO_CORE and output VOUT_CORE/
VDD_CORE should be connected together, and
tied to the output from DCDC_CORE. The
regulator should also be disabled in software.
Power VDD_CORE Connect to When the LDO_CORE is bypassed, the input

VDD_LDO_CORE VDD_LDO_CORE and output VOUT_CORE/
VDD_CORE should be connected together, and
NXP Semiconductors
Pinout
Table 93. Recommended connection for unused interfaces (continued)
tied to the output from DCDC_CORE. The

regulator should also be disabled in software.
Power VDD_LDO_SYS Connect to VDD_SYS When the LDO_SYS is bypassed, the input
VDD_LDO_SYS and output VOUT_SYS should
be connected together and tied to an external
supply. The regulator should also be disabled in
software.
Power VDD_DCDC Ground When the DCDC is not used, the input should be
tied to VSS through a 10 kΩ resistor.
Power DCDC_LX Float The input VDD_DCDC should be tied to VSS

with 10 Kohm
Power VDD_SYS/VOUT_SYS Must be powered VDD_SYS is used to power parts of the system
power controller (SPC) and must be powered
to use the chip. If LDO_SYS is not being
used, then tie VDD_LDO_SYS to VOUT_SYS/
VDD_SYS and supply power from an external
source. The regulator should also be disabled in
software.
Power VDD Must be powered VDD powers the mux logic for PORT 0, PORT 1,
and Flash. It must be powered during POR. The
recommendation is to keep it powered, but it can
be connected to the output of the Smart Power
Switch and be left floating in shelf storage mode.
Power VDD_ANA Float VDD_ANA is allowed to float ONLY if VDD_P4

is allowed to float. Otherwise, VDD_ANA MUST
be powered and all requirements for VDD_ANA
stated in this document apply.
Power VDD_USB Tie to ground through

a 10 kΩ resistor
if VDD_USB is an
independent pin in the
package version used
Power VREFH Always connect to Always connect to VDD_ANA potential

VDD_ANA potential
Power VREFL Always connect to VSS Always connect to VSS potential

potential
Power VSS_ANA Always connect to VSS Always connect to VSS potential

potential
Power VSS_DCDC Always connect to VSS Always connect to VSS potential

potential
Power VSS_USB Always connect to VSS Always connect to VSS potential

potential
Analog/non-GPIO ADCn_x Float
NXP Semiconductors
Ordering parts
Table 93. Recommended connection for unused interfaces (continued)
Analog/non-GPIO ADCn_x/DACn_OUT Float
Analog/non-GPIO VREF_OUT Float Analog output - Float
Analog/non-GPIO TAMPERx Float
Analog/non-GPIO VBAT_WAKEUP_b Float
Analog/non-GPIO RTC_CLKOUT Float
Analog/non-GPIO EXTAL32K Float
Analog/non-GPIO XTAL32K Float Analog output - Float
Analog/non-GPIO EXTAL_32M Float
Analog/non-GPIO XTAL_32M Float Analog output - Float
Analog/non-GPIO USB0_DP Float Float
Analog/non-GPIO USB1_DP Float Float
Analog/non-GPIO USB0_DM Float Float
Analog/non-GPIO USB1_DM Float Float
Analog/non-GPIO USB1_VBUS Float
Analog/non-GPIO USB1_ID Float
GPIO/Analog Px/ADCn_x Float Float (default is analog input)
GPIO/Analog Px/CMPn_INx Float Float (default is analog input)
GPIO/Digital P0_1/JTAG_TCLK Float Float (default is JTAG with pulldown)
GPIO/Digital P0_3/JTAG_TDI Float Float (default is JTAG with pullup)
GPIO/Digital P0_2/JTAG_TDO Float Float (default is JTAG with pullup)
GPIO/Digital P0_0/JTAG_TMS Float Float (default is JTAG with pullup)
GPIO/Digital Px Float Float (default is disabled)
7 Ordering parts
7.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com
and perform a part number search for the following device numbers:MCXN946VNLT
NOTE
For complete list of Orderable part numbers, please refer Table 1
8 Part identification
Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part.
NXP Semiconductors
Part identification
8.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific
part you have received.
8.2 Part number format

Part numbers for this device have the following format:
B PS F T PG PT
Table 94. Part number fields descriptions
Field Description Values
B Brand • MCX
PS Product series name • N
F Family • 5xx
• 9xx
T Ambient Temperature range (°C) • V = –40 to 105
PG Package • NL = 100 HLQFP (14 x 14 x 1 mm, 0.5mm

pitch)
• DF = 184 VFBGA (9 x 9 x 0.85 mm, 0.5mm
pitch)
PT Package Type • R = Tape and Reel

• T = Tray
8.3 Example
This is an example part number:
MCXN946VNLT
8.4 Package marking
8.4.1 Package marking information

VFBGA package has the following top-side marking:
• First line: NXP logo
• Second line: Part number, minus the package extension info (ex. part# = PMCXN947VDFT, marking = PMCXN947V)
• Third line: Lot Information: (assembly site + wafer/diffusion lot + assembly lot)
• Fourth line: Trace Code: (year + work week)
• Fifth line: Mask set
NXP Semiconductors
Terminology and guidelines
Table 95. Package marking
Identifier
(O)
PMCXNxxxV
AWLZ
YYWW
MMMMM
9 Terminology and guidelines
9.1 Definitions
Key terms are defined in the following table:
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent
chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE
The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation
if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE
Typical values are provided as design guidelines and are neither tested
nor guaranteed.
NXP Semiconductors
Terminology and guidelines
9.2 Examples
9.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified):
Symbol Description Value Unit
TA Ambient temperature 25 °C
VDD Supply voltage 3.3 V
NXP Semiconductors
Revision History
9.4 Relationship between ratings and operating requirements

in.
)
ax.)
(m (m
n.) nt nt x.)
mi rem
e
em
e ma
g( ui uir ng
(
a tin eq req rat
i
gr gr ng ing
tin tin rat
i
rat
era era e e
Op Op Op Op
Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range
Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure
- Possible decreased life - Correct operation - Possible decreased life
- Possible incorrect operation - Possible incorrect operation
–∞ ∞
Operating (power on)
n.) .)
i ax
(m (m
i ng ing
rat rat
ng lin
g
n dli nd
Ha Ha
Fatal range Handling range Fatal range
Expected permanent failure No permanent failure Expected permanent failure
–∞ ∞
Handling (power off)
9.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power
sequencing), limit the duration as much as possible.
10 Revision History
The following table provides a revision history for this document.
Table 96. Revision History
Rev. No. Date Substantial Changes
4 Jan 2024 Initial public release
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Date of release: 01/2024

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Mcxnx4X: 32-Bit Arm Cortex-M33 at 150 MHZ (N94X and N54X)

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MCXNx4x

32-bit Arm Cortex-M33 @ 150 MHz (N94x and N54x)

Target Applications Advanced Security

Table continues on the next page...

• Two asynchronous DMA modules (16-channels each) — Temperature tamper detect

Table continues on the next page...

• 10x LP Flexcomms each supports SPI, I2C, UART • Encoder

Inputs Supply Voltage options: — Functions down to Power-Down Mode

• Integrated voltage regulator • Up to 124 GPIOs

Table 1. Ordering Information

Orderable Part Number1 Part Number 2 Embedded Features Package

Flash SRAM Tamper GPIOs SRAM Pin Type

(P)MCXN547VNLT (P)MCXN547VNLT 2 512 2 74 Y 100 HLQFP

(P)MCXN546VNLT (P)MCXN546VNLT 1 352 2 74 Y 100 HLQFP

(P)MCXN547VDFT (P)MCXN547VDFT 2 512 8 124 Y 184 VFBGA

(P)MCXN546VDFT (P)MCXN546VDFT 1 352 8 124 Y 184 VFBGA

(P)MCXN947VDFT (P)MCXN947VDFT 2 512 8 124 Y 184 VFBGA

(P)MCXN947VNLT (P)MCXN947VNLT 2 512 2 78 Y 100 HLQFP

(P)MCXN946VNLT (P)MCXN946VNLT 1 352 2 78 Y 100 HLQFP

Table continues on the next page...

Table 1. Ordering Information (continued)

Orderable Part Number1 Part Number 2 Embedded Features Package

Flash SRAM Tamper GPIOs SRAM Pin Type

(P)MCXN946VDFT (P)MCXN946VDFT 1 352 8 124 Y 184 VFBGA

Table 2. Device Revision Number

Device Mask Set Number SYSCON[DIEID] 1 JTAG ID Register[PRN]

P02G 0x0052_09ax 0x0726_402B

Table 3. Related Resources

Type Description Resource

Reference The Reference Manual contains a comprehensive description of the MCXNx4xRM

Software MCUXpresso SDK. An open source software development kit http://www.nxp.com/mcuxpresso

TZ DSP FPU MPU Debug Clocks, PoR

VBAT VSYS VDD_CORE_WAKE VDD_CORE_MAIN

Figure 1. Block Diagram

1 Feature Comparison ..........................................8 4.3.1 Flash electrical specifications....................... 48

Features MCXN947 MCXN946 MCXN546 MCXN547

Package VFBGA184, VFBGA184, VFBGA184, VFBGA184, HLQFP100

CPU Core M33 @150 MHz 2 2 2 2

Flash 1 Flash ECC Upto 2 MB Upto 1 MB Upto 1 MB Upto 2 MB

External Memory FlexSPI with 16 1x, 2 ch 1x, 2 ch 1x, 2 ch 1x, 2 ch

Smart Card EVSIM Y N Y Y

Security Secure Key PUF/UDF PUF/UDF PUF/UDF PUF/UDF

Serial Interfaces I3C (I2C back 2 2 2 2

Table continues on the next page...

Table 4. Feature Comparison (continued)

Features MCXN947 MCXN946 MCXN546 MCXN547

SAI Up to 4ch Up to 4ch Up to 4ch 4 ch

Human Machine Touch Sensor 25 ch 25 ch 25 ch

DMIC 4 ch6,5 — 4ch 4 ch

Motor Control FlexPWM 2 2 1 1

SINC Filter (3rd 1 1 — —

1. For more details, please refer to Ordering Information Table

2.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes

TSTG Storage temperature –55 150 °C 1

TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes