Chapter Four

THE 8086 CUP MODULE

4.1 8086 CPU READ AND WRITE BUS CYCLE

A microprocessor endlessly follows the sequence:

1. Fetch the next instruction in sequence from memory

2. Execute the instruction
3. Go to step-1

The fetch cycle is actually a memory read operation in which the byte or word “pointed
to” by the program counter (or instruction pointer) is transferred from memory to the
instruction register in the CPU. Execution of the instruction may require additional
memory or I/O read/write operation, or an internal CPU activity.

In all; there are five unique operations or bus cycles possible:

1. Memory read
2. Memory write
3. I/O read
4. I/O write
5. Bus idle (internal operation not requiring access to memory or I/O)

Note that three sets of wires (or buses) are dedicated to this transferring of data between
the CPU and the memory and I/O units.

4.1.1 BUS CYCLE TIMING

Figure below illustrates bus cycle timing for the four active bus cycle types. Each cycle
begins with the output of the memory or I/O port address during the T1 clock cycle. It
can be a 20-bit memory address, a 16-bit indirect input output port address, or an 8-bit
direct I/O address (using register DX), or an 8-bit direct I/O address.

Examining the address lines only, it is not possible to determine if this is a memory or an
input output address. Neither can tell the direction of the data flow. i.e., the CPU
performing a read or write cycle? For this reason a control bus is required. This bus
consists of the four active –low signals:

1. 
MEMR
2. 
MEMW
3. 
IOR
4. 
IOW

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 Figure 4.1 memory, I/O read/write bus cycle timing
During an active bus cycle the microprocessor may perform a memory read, memory
write, I/O read, or I/O write operation. The control and address buses are used to specify
the memory or I/O address and the direction of data flow on the data bus lines. One bus
cycle contains four CPU clock periods called T-states.

To see how the three buses shown work together. Consider the sequence of events that
occur during a memory read bus cycle.

T1. The processor out puts the 20-bit memory addresses. The data lines are open
circuited and all control lines disabled.
T2. The MEMR control line is driven low. The memory unit recognizes this bus cycle
as a memory read and prepares to place the addressed byte or word on to the data
lines.

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 T3. The microprocessor configures its data bus lines for input but takes no further
action. This state is provided primarily to give the memory time to “work up” the
data byte o r word.
T4. The microprocessor now expects the data to be on the data bus lines. It latches the
contents of these lines and releases the memory read control signal. This marks
the end of the bus cycle.

The microprocessor controls all the bus timing. The memory must be able to supply the
 goes high during the T4-state. If it cannot
selected data byte or word by the time MEMR
do so, the CPU will read random information on the data bus lines. This will lead to
unpredictable results.

Note that only one control signal can be active at a given time. The processor cannot read
from its memory at the same time it is outputting to an input output device.

Example 4.1

Describe the contents of the address, data, and control bus lines when the instruction

MOV [1000H], BX is executed. Assume DS = 09D3H and BX = 1234H

Solution

The instruction requires a memory write to location 1000H of the data segment.

During T1 the 20-bit address bus will hold 09D30H + 1000H = 0AD30H.

 will go low and the data bus will contain 1234H
During T2 the control bus signal MEMW
(BX).

 returns high.

During T4 the memory latches this data by the time MEMW

4.2 8086 CPU PIN DESIGN/DESCRIPTIONS

The 8086 has 40 –pin dual-in-line package (DIP).

It has 20-bit address bus

16-bit data bus
3-pin power and
17-pins devoted to miscellaneous control and timing functions.
Time multiplexing: is a design technique in which one circuit pin has more than one
function. For example the data pins (labeled AD0 – AD15) are address lines during the
T1 clock state, but become data lines during the T2 – T4 states.
A special “de-multiplexing “circuit is required to extract the separate data and address
lines.

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 Figure 4.2 8086 CPU pin design
Using time multiplexing the pin breakdown becomes

16 data and address pins

4 address (and status) pins
3 power pins
17 control and timing pins.

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Data bus (AD0 – AD15) these 16 pins form the CPU’s bidirectional data bus. These
lines are valid only during the T2 through T4 clock states. During T1 they hold the 16-
bits of the memory or I/O address.
Address bus (AD0 – AD15 and A16/S3 – A19/S6) these 20-pins correspond to the
CPU’s 20-bit address, data and status lines on AD0 – AD15 bus and allow the processor
to access 1,048,576 unique memory locations. They are active during T1 state, switching
to become the data and status lines during the T2-T4 clock states.

Address latch enable (ALE) the signal output on this pin can be used to de-multiplex
the address, data, and status lines on AD0 – AD15, A16/S3 – A19/S6, BHE /S7. Every
cycle begins with the output of ALE pulse during the T1 clock state. The 20-bit address is
guaranteed to be valid when ALE switches from high to low near the end of T1. This
signal can be used to strobe the address into latch.

Memory input output (M/) memory and I/O signal. The 8086 does not output
separate memory and I/O read and write signals. It is output early in the T1 state and
= 1) or I/O (M/IO
identifies the current bus cycle as a memory (M/IO = 0) operation.

Read () this active low output signal indicates that the direction of data flow on the
bus is from memory or I/O in to the processor. It can be combined with M/IO to form
 and 
MEMR IOR control signals. It is output during the T2 state and removed during the
T4 state. The memory or I/O device is assumed to have placed the addressed byte or
word on to the data lines by the time RD returns high.

Write () indicates that data is to flow from the CPU to memory or to an I/O device
during T2 state. This gives the memory or I/O plenty of time to latch the data byte or
word before WR is removed during T4. Figure below shows how  RD, 
WR, and M/IO  can
be combined to generate a conventional four-line control bus. Figure 4.3 indicates
generating the four memory and I/O control bus signals from the 8086  RD, 
WR, and
 outputs.
M/IO

Figure 4.3 the four control bus signals

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Clock (CLK) All events in the microprocessor are synchronized to the system clock
applied to the CLK pin. The maximum frequency for the 8086 is 10MHz. the 8284A is
used as a clock generator.

Status (A16/S3 – A19/S6 and  /S7) these five status signals are output during states
T2 – T4. They are intended primarily for diagnostic testing purposes, as their definitions
in the table below indicate. It is possible to decode S3 and S4 to provide four separate
1MB address spaces for the extra, data, code, and stack memory segments. This is shown
in figure 4.4. All memory read or write operations are intercepted by this circuit, causing
the appropriate physical memory block to be accessed.

Table 4.1 S3 – S7 status bit definitions

S4 S3 Bus cycle access is to

0 0 Extra segment
0 1 Stack segment
1 0 Code segment (or none)
1 1 Data segment

S5, IF (interrupts enabled flag)

S6, 0 (indicates 8086 is on the bus)

S7, spare status (not used).

Extra Stack Code Data

1 MB

74LS138 0 
E 
E  
E E
A
S3 1
1/2
B 2
S4
3

RD

WR 
E


M/IO

Figure 4.4 Decoding status signals S3 and S4

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Decoding status signals S3 and S4 allows the extra, stack, code, and data segments to be
located in physically separate 1MByte address space.

Bus high enable ( /S7) this signal is multiplexed with the S7 status indicator. It is
output during the T1 state. When BHE  is low, it indicates that AD8 – AD15 are involved
in the data transfer. This can occur for memory or I/O word accesses or when accessing a
data byte from an odd address. BHE  and A0 are typically used to select even or odd
memory banks or I/O ports.

Table 4.2 memory access encoding


BHE A0 Action

0 0 Access 16 – bit word

0 1 Access odd byte to D8- D15
1 0 Access even byte to D0- D7
1 1 No action

Data transmit/receive (DT/  ) this signal is intended to control the direction of data flow
through the buffers (if any) connected to the system data bus. When low it indicates a
read operation, and when high, a write operation.

Data enable (DEN) this signal intended to be used with DT/R  to enable a set of
bidirectional buffers connected to the system data bus. it prevents bus contention (two
circuits attempting to drive thw same bus line) by disabling the data bus buffer s until the
T2 state, when the address/data lines no longer hold the memory or I/O address.

Minimum/maximum mode (MN/ ) the 8086 can be operated in one of two modes
called the minimum and maximum modes. The function of pins 24 through 32 changes
=1
depending on the logic level applied to this pin. For minimum mode operation MN/MX

RESET: when pulsed high this input causes the 8086 to terminate its present activity and
perform a reset sequence. The status of the old job is lost. Reset is normally used when
first starting the system or after a system crash.
 This input is used together with the WAIT instruction. If the TEST
  input is high
when the WAIT instruction is encountered, execution of the program is suspended and
the CPU enters an idle mode. Only when TEST  returns low will execution resume.
Normally, this input is driven by the 8087. This prevents the CPU from accessing a
memory result before the other microprocessor has finished its calculations.

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READY the READY input is sampled on the rising edge of the T2 clock pulse. If this
line is found low (not ready) an extra T3 state is inserted by the processor. The cycle
repeats until the READY input is found high. The READY input is usually driven by a
slow–memory device that cannot supply data as fast as required with normal CPU timing.

Interrupts (INTR, NMI, and 

) INTR and NMI are hardware-initiated interrupt
requests that function exactly as software interrupts. NMI is rising-edge triggered and
INTR is an active high-level trigger. The INTR input can be masked by resetting the IF
processor status bit (CLI). NMI is a non maskable interrupt that will always be serviced.
As such it should be reserved for “catastrophic” events such as power failure or memory
errors.

When NMI is active, control automatically transfers to the address stored in locations
00008–0000BH. When INTR is active an interrupt-acknowledge cycle is performed. The
interrupting device is expected to place an 8-bit type number on to the low-order data
bus. Control then transfers to the address stored in locations type x 4 through type x 4 +
3.

Hold and hold acknowledge (HOLD and HLDA)

HOLD is an active high CPU input that causes the processor to open circuit all of its bus
lines. This effectively disconnecting the CPU from its memory and I/O, allowing a
second processor to access these devices. This is referred to as direct-memory-access
(DMA). HLDA acknowledges the DMA request to the DMA controller.

Power and ground (Vcc and GND) the 8086 requires a single +5v power source and
has two ground pins.

4.3 GENERATING THE 8086 SYSTEM CLOCK & RESET SIGNALS

The 8086 requires a clock signal with fast rise& fall time (< 10ns), logic 0 and 1 levels of
0.5 to 0.6v and 3.9 to 5.0v, respectively, and a duty cycle of 33%. The processor’s
RESET signal must be synchronized to the system clock and persist for at least 4T states.
The Intel 8284A clock generator meets all the requirements for the clock and RESET
signals.

The 8086 clock signal

All the activities of the 8086 are sequential and synchronized to a system clock signal.
During

T1 the memory or I/O address is output

T2 Control signals are activated.
T3 the memory and I/O are given time to respond
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T4 the data is in put or output.

Importance of clock signal

Without the clock signal to synchronize these events we would have disorder.

Internally, the microprocessor is designed with dynamic logic gates that require
periodic “refreshing” or they will lose their data. The clock signal provides this
refresh. For this reason the clock must never be stopped.

4.3.1 “COLD STARTING” THE 8086

When power is first applied to the 8086, all its internal registers RAM contain random
data. Because of this, the processor will fetch its first instruction from a random memory
location (containing a random instruction), leading to an unpredictable result.

The RESET input is provided for gaining control of the machine when it is first started.
When this pin is driven high, most of the 8086 CPU register are rest as shown in the
table.

Table 4.3 CPU state following RESET

CPU Contents

Flags Clear
Instruction pointer 0000H
CS register FFFFH
DS register 0000H
SS register 0000H
ES register 0000H
Queue Empty

Because, the CS register contains FFFFH, the CPU will fetch its first instruction from
physical address FFFFOH + 0000H = FFFF0H.

RESET thus solves the random start address problem associated with Cold starting the
processor. We must ensure that a useful program resides in memory beginning at the
reset start address FFFF0H. Note that RAM cannot be used at this address. ROM is
mapped in to this address space, because the content of ROM is not lost when power is

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removed. We can be sure that the 8086 will have a useful program to execute when it is
first started.

There are only 16 bytes between addresses FFFFOH and FFFFFH (the end of memory).
So the instruction at FFFF0H is normally a “jump” to some other location where a longer
program resides (again in ROM). This program could be a “boot strap” Loader program
that initializes the computer and then loads a more complex program from a disk drive
(usually the operating system) in to RAM.

4.4 MICRO COMPUTER BUS-TYPES AND BUFFERING

TECHNIQUES

There are three types of buses to be found in a micro computer system (not to be
confused with the address, data and control buses, which are dedicated to particular task)

Type 1:- one transmitter, several receives.

Example, the address bus.

Type 2:- one receiver, several transmitters.

Example, when the processor requires reading a status port-technique called

polling – determining the active device.

Type 3:- several transmitter and receivers.

Example, the bidirectional data bus.

Each of these bus types requires special buffering techniques to ensure reliable data
transmission. The purpose of the buffer will be to minimize the ac and dc loading effects
associated with multiple receivers and transmitters on a single bus line.

For example, each receiver requires a dc load current from the transmitter. The effect of
this load is to reduce the high-level output voltage (VOH). And increase the low-level
output voltage (VOL) this in turn reduces the noise immunity of the system.

In addition to a dc load, each receiver also presents as ac load, this is the receivers input
capacitance that must be charged and discharged each time the transmitter’s output
changes state.

The effect is to increase the propagation delay time for the transmitted signal. This
decreases the time available to the memory or I/O device for reading or writing data.

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 Input Data bus line = input
E

“0”

Input Data bus line = input

E

“1”

E I Data bus

0 0 0
0 1 1
1 X free

Figure 4.5 tri-state buffers and its truth table

Tri-state buffers (74Ls240/241/244) These contain eight buffers in one package and are
the most common types. In addition to the two logic states, these buffers out put a third
state called the tri-state, which is actually a high-impedance or open circuit.

Note that, as a general rule, a bus buffer should be used when even the bus loading
exceeds the drive capabilities of the microprocessor or when it is necessary to drive
receivers off the main CPU card (due to the capacitive loading associated with edge
connectors and backplane wiring in a multi card system .

It is not only advantageous to use a buffer for the transmitter, but by also buffering each
receiver input, the number of receivers that can be safely driven is increased. Two tri-
state gates are required for each bi-directional bus line with separate 
READ and 
WRITE
enables.

4.5 THE 8086 MINIMUM MODE CPU MODULE

When the 8086 MN/MX  pin is wired to +SV, the processor operates in the minimum
mode. In this mode the CPU provides all the control signals for the system. The
minimum mode is intended for simple single-processor systems on one printed circuit
board (PCB). The maximum mode is intended for more complex systems with separate
I/O and memory boards, it also supports co-processors. The 8086 minimum mode CPU
module is a hardware module providing all the signals required to interface memory and
I/O in a practical 8086- based micro computer system.

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