Maxim 8731
Maxim 8731
Maxim 8731
Features
0.5% Battery Voltage Accuracy 3% Input Current-Limit Accuracy 3% Charge-Current Accuracy SMBus 2-Wire Serial Interface Cycle-by-Cycle Current Limit Battery Short-Circuit Protection Fast Response for Pulse Charging Fast System-Load-Transient Response Dual-Remote-Sense Inputs Monitor Outputs for Adapter Current (4% Accuracy) AC Adapter Detection 11-Bit Battery Voltage Setting 6-Bit Charge-Current/Input-Current Setting 8A (max) Battery Charger Current 11A (max) Input Current +8V to +26V Input Voltage Range Charges Li+, NiMH, and NiCd Battery Chemistries
MAX8731
Ordering Information
PART TEMP RANGE PIN-PACKAGE 28 Thin QFN (5mm x 5mm) MAX8731ETI+ -40C to +85C +Indicates lead-free packaging.
Applications
Notebook Computers Tablet PCs Medical Devices Portable Equipment with Rechargeable Batteries
Pin Configuration
PGND FBSB FBSA CSIN CSIP LDO DLO
TOP VIEW
20
19
18
17
16
GND
SELECTOR FBSA BATSEL SCL SDA VDD GND IINP DAC CCS LDO VCC CCV CCI FBSB
BATSEL BATTERY A
MAX8731
11 10
*EXPOSED PADDLE
9 8
BATTERY B
2 ACIN
3 REF
4 CCS
5 CCI
6 CCV
7 DAC
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDCIN = VLX = VCSSP = VCSSN = 19V, VBST - VLX = 4.5V, VFBSA = VFBSB = VCSIP = VCSIN = 16.8V, BATSEL = GND = PGND = 0, CLDO = 1F, VCC = LDO, CREF = 1F, CDAC = 0.1F, VDD = 3.3V, ACIN = 2.5V; pins CCI, CCV, and CCS are compensated per Figure 1; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CHARGE-VOLTAGE REGULATION ChargingVoltage() = 0x41A0 ChargingVoltage() = 0x3130 Battery Full-Charge Voltage and Accuracy ChargingVoltage() = 0x20D0 ChargingVoltage() = 0x1060 Battery Undervoltage-Lockout Trip Point for Trickle Charge CHARGE-CURRENT REGULATION CSIP to CSIN Full-Scale CurrentSense Voltage RS2 (Figure 1) = 10m; ChargingCurrent() = 0x1f80 Charge Current and Accuracy RS2 (Figure 1) = 10m; ChargingCurrent() = 0x0f80 RS2 (Figure 1) = 10m; ChargingCurrent() = 0x0080 (128mA) Charge-Current Gain Error FBSA/FBSB/CSIP/CSIN Input Voltage Range Based on ChargeCurrent() = 128mA and 8.064A 78.22 7.822 -3 3.809 -4 64 -2 0 3.968 80.64 8.064 83.06 8.306 +3 4.126 +4 400 +2 19 mV A % A % mA % V 16.716 -0.5 12.491 -0.8 8.333 -0.8 4.15 -1.0 2.5 4.192 8.4 12.592 16.8 16.884 +0.5 12.693 +0.8 8.467 +0.8 4.234 +1.0 V % V % V % V % V CONDITIONS MIN TYP MAX UNITS
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MAX8731
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MAX8731
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MAX8731
Note 1: Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). Note 2: Specifications to -40C are guaranteed by design, not production tested.
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6 INPUT CURRENT-LIMIT ERROR (%) 4 MAXIMUM 2 TYPICAL 0 -2 -4 -6 0 2 4 6 8 10 INPUT CURRENT-LIMIT SETTING (A) MINIMUM
0.4 INPUT CURRENT-LIMIT ERROR (%) INPUT CURRENT LIMIT = 3.584A 0.2
1.0
0 INPUT CURRENT LIMIT = 4.096A -0.2 INPUT CURRENT LIMIT = 2.048A -0.4 0 1 2 3 SYSTEM CURRENT (A)
1.0 0.8 0.6 0.4 IINP ERROR (%) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 SYSTEM CURRENT (A) 3.5 INPUT CURRENT LIMIT = 4.096A OPERATING AT INPUT CURRENT LIMIT INPUT CURRENT LIMIT = 3.584A INPUT CURRENT LIMIT = 2.048A
10
2 0 -2 -4 TYPICAL MINIMUM
-6 -8 -10 0 1
10 CHARGE-CURRENT LIMIT ERROR (%) 8 6 4 2 0 -2 -4 -6 -8 -10 0 2 4 6 CHARGE-CURRENT SETTING (A) 8 TYPICAL MINIMUM MAXIMUM
3.072A
3.968A
0 8.064A -2
10
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MAX8731
0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 4 8 12 16 CHARGE-VOLTAGE SETTING (V)
2 CELLS
20
BATTERY REMOVAL
MAX8731 toc12
LOAD CURRENT ADAPTER CURRENT INDUCTOR CURRENT CCS VOLTAGE 500 mV/div CCI VOLTAGE 500 mV/div CCS CCI CCS 200s/div CCI
5A 0A 5A 0A 5A 0A 500mV/div 500mV/div
20s/div
20
40 60 ILDO (mA)
80
100
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0.20 NOT SWITCHING 0.15 0.10 REF ERROR (%) 0.05 0 -0.05 -0.10 -0.15 -0.20 0 0.2 0.4 0.6 IREF (mA) 0.8
1.0
-40
-20
0 20 40 TEMPERATURE (C)
60
80
SWITCHING FREQUENCY
MAX8731 toc19
BATTERY-CHARGE CURVE
5 2.8Ah x 3S3P BATTERY 4 CHARGE CURRENT (A) BATTERY VOLTAGE 12.5 12.0 3 11.5 2 11.0 1 CHARGE CURRENT 0 10.5 10.0 0 1 2 3 TIME (h) 4 5 6 BATTERY VOLTAGE (V)
MAX8731 toc20
450 400 FREQUENCY (kHz) 350 300 250 200 150 0 5 10 15 VADAPTER - VBATTERY (V)
13.0
20
3.0 SWITCHING, NO LOAD 2.5 ADAPTER CURRENT (mA) 2.0 ChargeVoltage( ) = 4.192V 1.5 1.0 0.5 0 0 5 10 15 20 ADAPTER VOLTAGE (V) 25 NOT SWITCHING
2.5
1.5
1.0
0.5
12
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MAX8731
14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29
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CSSP
CIN1 10F
INPUT VDD
KBC SCL
R6 10k SDA
BP C8 0.1F
BATTERY A
BATTERY B
Detailed Description
The typical operating circuit is shown in Figure 1. The MAX8731 includes all the functions necessary to charge Li+, NiMH, and NiCd smart batteries. A highefficiency, synchronous-rectified, step-down DC-DC converter is used to implement a precision constantcurrent, constant-voltage charger. The DC-DC converter drives a high-side n-channel MOSFET and provides synchronous rectification with a low-side n-channel MOSFET. The charge current and input current-sense
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amplifiers have low input-offset error (64V typ), allowing the use of small-valued sense resistors. The MAX8731 features a voltage-regulation loop (CCV) and two current-regulation loops (CCI and CCS). The loops operate independently of each other. The CCV voltage-regulation loop monitors either FBSA or FBSB to ensure that its voltage never exceeds the voltage set by the ChargeVoltage() command. The CCI battery current-regulation loop monitors current delivered to the selected battery to ensure that it never exceeds the current limit set by the ChargeCurrent() command. The
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MAX8731
MAX8731
CSSP POWER-FAIL ZCMD CSIN ACIN VCC ACOK LVC REF/2 GND OVP LOWEST VOLTAGE CLAMP CCV PGND CCMP LOWSIDE DRIVER DLO 100mV ENABLE IMIN DC-DC CONVERTER LEVEL SHIFT IMAX HIGHSIDE DRIVER DHI BST
LX LDO
CCI GMV
DCIN VCC
GMI
CCS CSI CSA: CURRENT-SENSE AMPLIFIER GMS 11-BIT DAC A = 1V/V CSS CSA 6-BIT DAC A = 20V/V GM CSA A = 20V/V 6-BIT DAC
CHARGE CURRENT ( )
SDA
INPUT CURRENT ( )
VDD
BATSEL
IINP
CSSN
CSSP
CSIP
CSIN
FBSB
FBSA
DAC
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MAX8731
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Remote Sense
The MAX8731 features dual remote sense, which allows the rejection of board resistance and selector resistance when used in either single- or dual-battery systems. To fully utilize remote sensing, connect FBS_ directly to the battery interface through an unshared battery sense trace in series with a 100 resistor, and 10nF capacitor (see Figure 1). In single-battery systems, connect BATSEL directly to GND and use only FBSA. Remote sensing cancels the effect of impedance in series with the battery. This impedance normally causes the battery charger to prematurely enter constantvoltage mode with reducing charge current. The result is that the last 20% of charging takes longer than necessary. When in constant-voltage mode, the remaining charge time is proportional to the total resistance in series with the battery. Remote sensing reduces charge time according to the following equation: t CVRS = t CV 0 RPack RPack + RBoard
Charger Timeout
The MAX8731 includes a timer to terminate charging if the charger does not receive a ChargeVoltage() or ChargeCurrent() command within 175s. If a timeout occurs, both ChargeVoltage() and ChargeCurrent() commands must be resent to reenable charging.
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VDD Supply The VDD input provides power to the SMBus interface. Connect VDD to LDO, or apply an external supply to VDD to keep the SMBus interface active while the supply to DCIN is removed. When VDD is biased the internal registers are maintained. Bypass VDD to GND with a 0.1F or greater ceramic capacitor. Operating Conditions
The MAX8731 has the following operating states: Adapter Present: When DCIN is greater than 7.5V, the adapter is considered to be present. In this condition, both the LDO and REF function properly and battery charging is allowed: a) Charging: The total MAX8731 quiescent current when charging is 1mA (max) plus the current required to drive the MOSFETs. b) Not Charging: To disable charging, set either ChargeCurrent() or ChargeVoltage() to zero. When the adapter is present and charging is disabled, the total adapter quiescent current is less than 1mA and the total battery quiescent current is less than 5A. Adapter Absent (Power Fail): When VCSSP is less than VCSIN + 10mV, the MAX8731 is in the power-fail state, since the DC-DC converter is in dropout. The charger does not attempt to charge in the power-fail state. Typically, this occurs when the adapter is absent. When the adapter is absent, the total MAX8731 quiescent battery current is less than 1A (max). VDD Undervoltage (POR): When VDD is less than 2.5V, the VDD supply is in an undervoltage state and the internal registers are in their POR state. The SMBus interface does not respond to commands. When VDD rises above 2.5V, the MAX8731 is in a power-on reset state. Charging does not occur until the ChargeVoltage() and ChargeCurrent() commands are sent. When V DD is greater than 2.5V, SMBus registers are preserved. The MAX8731 allows charging under the following conditions: 1) DCIN > 7.5V, LDO > 4V, REF > 3.1V 2) VCSSP > VCSIN + 210mV (15mV falling threshold) 3) VDD > 2.5V
MAX8731
LDO Regulator
An integrated low-dropout (LDO) linear regulator provides a 5.4V supply derived from DCIN, and delivers over 30mA of load current. The LDO powers the gate drivers of the n-channel MOSFETs. See the MOSFET Drivers section. LDO has a minimum current limit of 35mA. This allows the MAX8731 to work with 87nC of total gate charge (both high-side and low-side MOSFETs). Bypass LDO to PGND with a 1F or greater ceramic capacitor.
AC Adapter Detection
The MAX8731 includes a hysteretic comparator that detects the presence of an AC power adapter. When ACIN is greater than 2.048V, the open-drain ACOK output becomes high impedance. Connect 10k pullup resistance between LDO and ACOK. Use a resistive voltage-divider from the adapters output to the ACIN pin to set the appropriate detection threshold. Select the resistive voltage-divider not to exceed the 6V absolute maximum rating of ACIN.
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a) Write-Word Format S SLAVE W ADDRESS 7 BITS 1b MSB LSB 0 PRESET TO 0b0001001 ACK 1b 0 COMMAND BYTE 8 BITS MSB LSB ChargerMode() = 0x12 ChargeCurrent() = 0x14 ChargeVoltage() = 0x15 AlarmWarning() = 0x16 InputCurrent() = 0x3F ACK 1b 0 LOW DATA ACK BYTE 8 BITS 1b MSB LSB 0 D7 D0 HIGH DATA ACK P BYTE 8 BITS 1b MSB LSB 0 D15 D8
b) Read-Word Format S SLAVE W ADDRESS 7 BITS 1b MSB LSB 0 Preset to 0b0001001 ACK 1b 0
COMMAND ACK BYTE 8 BITS 1b MSB LSB 0 ChargerSpecInfo() = 0x11 ChargerStatus() = 0x13
R 1b 1
ACK 1b 0
LEGEND: S = START CONDITION OR REPEATED START CONDITION ACK = ACKNOWLEDGE (LOGIC-LOW) W = WRITE BIT (LOGIC-LOW) MASTER TO SLAVE SLAVE TO MASTER
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SMBCLK
SMBDATA
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tHD:DAT
tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION, DATA EXECUTED BY SLAVE M = NEW START CONDITION
A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW
A tLOW
B tHIGH
SMBCLK
SMBDATA
tSU:STA tHD:STA A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE
tSU:DAT
tHD:DAT E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER
tSU:DAT
tSU:STO
tBUF
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Battery-Charger Commands
The MAX8731 supports four battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 4. ManufacturerID() and DeviceID() can be used to identify the MAX8731. On the MAX8731, the ManufacturerID() command always returns 0x004D and the DeviceID() command always returns 0x0008.
DC-DC Converter
The MAX8731 employs a synchronous step-down DCDC converter with an n-channel high-side MOSFET switch and an n-channel low-side synchronous rectifier. The MAX8731 features a pseudo-fixed-frequency, current-mode control scheme with cycle-by-cycle current limit. The controllers constant off-time (tOFF) is calculated based on VCSSP, VCSIN, and a time constant with a minimum value of 300ns. The MAX8731 can also operate in discontinuous-conduction mode for improved light-load efficiency. The operation of the DC-DC controller is determined by the following four comparators as shown in the functional diagrams in Figures 2 and 6:
FBS_ ChargeVoltage ( ) +100mV CSI IMAX 2V R Q DH DRIVER OVP
The IMIN comparator triggers a pulse in discontinuous mode when the accumulated error is too high. IMIN compares the control signal (LVC) against 100mV (typ). When LVC is less than 100mV, DHI and DLO are both forced low. Indirectly, IMIN sets the peak inductor current in discontinuous mode. The CCMP comparator is used for current-mode regulation in continuous-conduction mode. CCMP compares LVC against the inductor current. The high-side MOSFET on-time is terminated when the CSI voltage is higher than LVC. The IMAX comparator provides a secondary cycle-bycycle current limit. IMAX compares CSI to 2V (corresponding to 10A when RS2 = 10m). The high-side MOSFET on-time is terminated when the current-sense signal exceeds 10A. A new cycle cannot start until the IMAX comparators output goes low. The ZCMP comparator provides zero-crossing detection during discontinuous conduction. ZCMP compares the current-sense feedback signal to 750mA (RS2 = 10m). When the inductor current is lower than the 750mA threshold, the comparator output is high and DLO is turned off. The OVP comparator is used to prevent overvoltage at the output due to battery removal. OVP compares FBS_ against the set voltage (ChargeVoltage()). When FBS_ is 100mV above the set value, the OVP comparator output goes high and the high-side MOSFET on-time is terminated. DHI and DLO remain off until the OVP condition is removed.
CCMP LVC
100mV
The MAX8731 controls input current (CCS control loop), charge current (CCI control loop), or charge voltage (CCV control loop), depending on the operating condition. The three control loopsCCV, CCI, and CCSare brought together internally at the lowest voltage-clamp (LVC) amplifier. The output of the LVC amplifier is the feedback control signal for the DC-DC controller. The minimum voltage at the CCV, CCI, or CCS appears at the output of the LVC amplifier and clamps the other control loops to within 0.3V above the control point.
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MAX8731
Continuous-Conduction Mode
With sufficient charge current, the MAX8731s inductor current never crosses zero, which is defined as continuous-conduction mode. The regulator switches at 400kHz (nominal) if VCSIN < 0.88 x VCSSP. The controller starts a new cycle by turning on the high-side MOSFET and turning off the low-side MOSFET. When the charge-current feedback signal (CSI) is greater than the control point (LVC), the CCMP comparator output goes high and the controller initiates the off-time by turning off the high-side MOSFET and turning on the low-side MOSFET. The operating frequency is governed by the off-time and is dependent upon VCSIN and VCSSP. The off-time is set by the following equation:
V V t OFF = 2.5s CSSP CSIN VCSSP
The on-time can be determined using the following equation: t ON = where: V t IRIPPLE = BATT OFF L The switching frequency can then be calculated: fSW = 1 t ON + t OFF L IRIPPLE VCSSN VBATT
Discontinuous Conduction
The MAX8731 can also operate in discontinuous-conduction mode to ensure that the inductor current is always positive. The MAX8731 enters discontinuousconduction mode when the output of the LVC control point falls below 100mV. This corresponds to peak inductor current = 500mA: 100mV ICHG = 1 = 250mA 2 20 RS2 charge current for RS2 = 10m. In discontinuous mode, a new cycle is not started until the LVC voltage rises above 100mV. Discontinuousmode operation can occur during conditioning charge of overdischarged battery packs, when the charge current has been reduced sufficiently by the CCS control loop, or when the charger is in constant-voltage mode with a nearly full battery pack.
These equations describe the controllers pseudofixed-frequency performance over the most common operating conditions. At the end of the fixed off-time, the controller initiates a new cycle if the control point (LVC) is greater than 100mV and the peak charge current is less than the cycle-by-cycle current limit. Restated another way,
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where ACSI = 20V/V, and RS2 = 10m in the typical application circuits, so GMOUT = 5A/V. The loop-transfer function is given by: LTF = GMOUT RL GMV ROGMV (1 + sCOUT RESR )(1 + sCCV RCV ) (1 + sCCV ROGMV )(1 + sCOUT RL ) The poles and zeros of the voltage loop-transfer function are listed from lowest frequency to highest frequency in Table 5. Near crossover CCV is much lower impedance than ROGMV. Since CCV is in parallel with ROGMV, CCV dominates the parallel impedance near crossover. Additionally, RCV is much higher impedance than CCV and dominates the series combination of RCV and CCV, so near crossover: ROGMV (1+ sCCV RCV ) RCV (1+ sCCV ROGMV )
CCV
f P _ CV =
1 2ROGMV CCV
CCV Zero
f Z _ CV =
1 2RCV CCV
Voltage-loop compensation zero. If this zero is at the same frequency or lower than the output pole fP_OUT, then the loop-transfer function approximates a single-pole response near the crossover frequency. Choose CCV to place this zero at least 1 decade below crossover to ensure adequate phase margin. Output pole formed with the effective load resistance RL and the output capacitance COUT. RL influences the DC gain but does not affect the stability of the system or the crossover frequency. Output ESR Zero. This zero can keep the loop from crossing unity gain if fZ_OUT is less than the desired crossover frequency; therefore, choose a capacitor with an ESR zero greater than the crossover frequency.
Output Pole
f P _ OUT =
Output Zero
f P _ OUT =
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MAX8731
For stability, choose a crossover frequency lower than 1/10 the switching frequency. For example, choose a crossover frequency of 50kHz and solve for RVC using the component values listed in Figure 1 to yield RCV = 10k: RCV = 2 COUT fCO _ CV GMV GMOUT 10k
GMV = 0.125A/mV
80 60 40 20 0 -20 -40 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) MAG PHASE
0
CSIP GMOUT RS2 CSIN
-45
PHASE (DEGREES)
MAGNITUDE (dB)
CSI
-90
CCI GMI
-135 1M
CCI
ROGMI ChargeCurrent( )
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This describes a single-pole system. Since: 1 GMOUT = A CSI RS2 the loop-transfer function simplifies to: LTF = GMI ROGMI 1+ sROGMI CCI
The crossover frequency is given by: GMI fCO _ CI = 2CCI For stability, choose a crossover frequency lower than 1/10 the switching frequency: CCI > 10 GMI / (2 fOSC) = 4nF, for a 400kHz switching frequency. Values for CCI greater than 10 times the minimum value can slow down the current-loop response. Choosing CCI = 10nF yields a crossover frequency of 15.9kHz. Figure 10 shows the Bode plot of the current-loop frequency response using the values calculated above.
GMIN =
1 A CSS RS2
the loop-transfer function simplifies to: LTF = GMS ROGMS 1 + SROGMS CCS
SYSTEM LOAD
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MAX8731
For stability, choose a crossover frequency lower than 1/10 the switching frequency: CCS = 5 GMS /(2fOSC ) Choosing a crossover frequency of 30kHz and using the component values listed in Figure 1 yields CCS > 5.4nF. Values for CCS greater than 10 times the minimum value may slow down the current-loop response excessively. Figure 12 shows the Bode plot of the input current-limit-loop frequency response using the values calculated above.
Design Procedure
MOSFET Selection
Choose the n-channel MOSFETs according to the maximum required charge current. The MOSFETs must be able to dissipate the resistive losses plus the switching losses at both VDCIN(MIN) and VDCIN(MAX). For the high-side MOSFET, the worst-case resistive power losses occur at the maximum battery voltage and minimum supply voltage: PDCONDUCTION(HighSide) = VFBS _ VCSSP ICHG2 RDS(ON)
MOSFET Drivers
The DHI and DLO outputs are optimized for driving moderate-sized power MOSFETs. The MOSFET drive capability is the same for both the low-side and highsides switches. This is consistent with the variable duty factor that occurs in the notebook computer environment where the battery voltage changes over a wide range. There must be a low-resistance, low-inductance path from the DLO driver to the MOSFET gate to prevent shoot-through. Otherwise, the sense circuitry in the MAX8731 interprets the MOSFET gate as off while there is still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares or less (1.25mm to 2.5mm wide if the MOSFET is 25mm from
100 80 MAGNITUDE (dB) 60 40 -45 20 0 -20 -40 0.1 10 1k FREQUENCY (Hz) 100k -90 10M MAG PHASE PHASE (DEGREES) 0
Generally a low-gate charge high-side MOSFET is preferred to minimize switching losses. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching (AC) losses equal the conduction (RDS(ON)) losses. Calculating the power dissipation in N1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides a rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on N1:
PDSWITCHING (High Side) = 1 t Trans VDCIN ICHG fSW 2
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These calculations provide an estimate and are not a substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on the MOSFET.
Inductor Selection
The charge current, ripple, and operating frequency (off-time) determine the inductor characteristics. For optimum efficiency, choose the inductance according to the following equation: V t L = BATT OFF 0.3 ICHG This sets the ripple current to 1/3 the charge current and results in a good balance between inductor size and efficiency. Higher inductor values decrease the ripple current. Smaller inductor values save cost but require higher saturation current capabilities and degrade efficiency. Inductor L1 must have a saturation current rating of at least the maximum charge current plus 1/2 the ripple current (IL): ISAT = ICHG + (1/2) IL The ripple current is determined by: IL = VBATT tOFF / L where: tOFF = 2.5s (VDCIN - VBATT) / VDCIN for VBATT < 0.88 VDCIN or during dropout: tOFF = 0.3s for VBATT > 0.88 VDCIN
IGATE is the peak gate-drive current. The following is the power dissipated due to the highside n-channel MOSFETs output capacitance (CRSS): PDCOSS (HighSide)
2 VDCIN CRSS fSW
The total high-side MOSFET power dissipation is: PDTOTAL (HighSide) PDCONDUCTION(HighSide) + PDSWITCHING (HighSide) + PDCOSS (HighSide) Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied. If the high-side MOSFET chosen for adequate RDS(ON) at low-battery voltages becomes hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (N2), the worst-case power dissipation always occurs at maximum input voltage: VFBS _ PDCONDUCTION(Low Side) = 1 VCSSP ICHG2 RDS(ON) The following additional loss occurs in the low-side MOSFET due to the reverse-recovery charge of the MOSFETs body diode and the body diode conduction losses:
PDQRR (Low Side) = QRR2 VDCIN fSW + (0.05 IPEAK 0.4V)
The total power low-side MOSFET dissipation is: PDTOTAL (Low Side) PDCONDUCTION(Low Side) + PDQRR (HighSide)
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MAX8731
MAX8731 SMART-BATTERY CHARGER/ POWER-SOURCE SELECTOR SMBus CONTROL SIGNALS FOR BATTERY
BATT-
configurations and chemistries. Microcontroller programs can perform frequent tests on the batterys state of charge and dynamically change the voltage and current applied to enhance safety. Multiple batteries can also be utilized with a selector that is programmable over the SMBus.
Applications Information
Smart-Battery System Background Information
Smart-battery systems have evolved since the conception of the smart-battery system (SBS) specifications. Originally, such systems consisted of a smart battery and smart-battery charger that were compatible with the SBS specifications and communicated directly with one another using SMBus protocols. Modern systems still employ the original commands and protocols, but often use a keyboard controller or similar digital intelligence to mediate the communication between the battery and the charger (Figure 13). This arrangement permits considerable freedom in the implementation of charging algorithms at the expense of standardization. Algorithms can vary from the simple detection of the battery with a fixed set of instructions for charging the battery to highly complex programs that can accommodate multiple battery
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29
MAX8731
not go through vias. The resulting top-layer subground plane is connected to the normal innerlayer ground plane at the paddle. Other high-current paths should also be minimized, but focusing primarily on short ground and currentsense connections eliminates approximately 90% of all PC board layout problems. 2) Place the IC and signal components. Keep the main switching node (LX node) away from sensitive analog components (current-sense traces and REF capacitor). Important: The IC must be no further than 10mm from the current-sense resistors. Quiet connections to REF, CCS, DAC, CCV, CCI, ACIN, and VCC should be returned to a separate ground (GND) island. The analog ground is separately worked from power ground in Figure 1. There is very little current flowing in these traces, so the ground island need not be very large. When placed on an inner layer, a sizable ground island can help simplify the layout because the low-current connections can be made through vias. The ground pad on the backside of the package should also be connected to this quiet ground island. 3) Keep the gate-drive traces (DHI and DLO) as short as possible (L < 20mm), and route them away from the current-sense lines and REF. These traces should also be relatively wide (W > 1.25mm). 4) Place ceramic bypass capacitors close to the IC. The bulk capacitors can be placed further away. Place the current-sense input filter capacitors under the part, connected directly to the GND pin. 5) Use a single-point star ground placed directly below the part at the PGND pin. Connect the power ground (ground plane) and the quiet ground island at this location.
g) Ideally, surface-mount power components are flush against one another with their ground terminals almost touching. These high-current grounds are then connected to each other with a wide, filled zone of top-layer copper, so they do
Chip Information
TRANSISTOR COUNT: 10,234 PROCESS: BiCMOS
30
______________________________________________________________________________________
MAX8731
D2 D D/2 MARKING k L
C L
b D2/2
0.10 M C A B
AAAAA
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
L1
C L
C L
e 0.10 C A 0.08 C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
1 2
______________________________________________________________________________________
31
QFN THIN.EPS
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
D2
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20
E2
exceptions
A A1 A3 b D E e k L
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.50 BSC.
- 0.25 - 0.25 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 - 0.30 0.40 0.50 16 40 N 20 28 32 ND 4 10 5 7 8 4 10 5 7 8 NE WHHB ----WHHC WHHD-1 WHHD-2 JEDEC
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** **
YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Inc.