EECS 247 Analog-Digital Interface Integrated Circuits © 2010

EECS 247
Analog-Digital Interface
Integrated Circuits
© 2010
Instructor: Haideh Khorramabadi
UC Berkeley
Department of Electrical Engineering and
Computer Sciences
Lecture 1: Introduction
EECS 247 Lecture 1: Introduction © 2010 H.K. Page 1
Instructor‟s Technical Background

• Ph.D., EECS department -UC Berkeley 1985, advisor Prof. P.R. Gray
– Thesis topic: Continuous-time CMOS high-frequency filters
• Industrial background
– 11 years at ATT & Bell Laboratories, N.J., in the R&D area as a circuit designer
• Circuits for wireline communications: CODECs, ISDN, and DSL including
ADCs (nyquist rate & over-sampled), DACs, filters, VCOs
• Circuits intended for wireless applications
• Fiber-optics circuits
– 3 years at Philips Semiconductors, Sunnyvale, CA
• Managed a group in the RF IC department- developed ICs for CDMA &
analog cell phones
– 3 years @ Broadcom Corp. – Director of Analog/RF ICs in San Jose, CA.
• Projects: Gigabit-Ethernet, TV tuners, and DSL circuitry
– Currently consultant for IC design
• Teaching experience
– Has taught/co-taught EE247 @ UCB since 2003
– Instructor for short courses offered by MEAD Electronics
– Adjunct Prof. @ Rutgers Univ., N.J. : Taught a graduate level IC design course

Administrative Issues
• Course web page:

http://inst.eecs.berkeley.edu/~EE247/fa10
– Course notes will be uploaded on the course
website prior to each class
– Announcements regarding the course will be
posted on the home page, please visit course
website often
– Homeworks & due dates are posted on the course
website
Office Hours & Grading
• Office hours:
– Tues./Thurs. 4 to 5pm @ TBD (unless otherwise
announced in the class)
– Extra office hours by appointment
– Feel free to discuss issues via email:
haidehk@eecs.berkeley.edu
• Course grading:
– Homework/project 50%
– Midterm 20% (tentative date: Oct. 28)
– Final 30%

Prerequisites & CAD Tools
• Prerequisites
– Basic course in signal processing (Laplace and z-
transform, discrete Fourier transform) i.e. EE120
– Fundamental circuit concepts i.e. EE105 and
EE140
• CAD Tools:
– Hspice or Spectre
– Matlab
Analog-Digital Interface Circuitry
Analog Output Analog Input

Analog World
Analog/Digital Digital Digital/Analog

Interface 001 Processor 1001 Interface
110 1010
010 0010
• Naturally occurring signals are analog

• To process signals in the digital domain
 Need Analog/Digital & Digital/Analog interface circuitry
Question: Why not perform the signal processing in the analog domain only
& thus eliminate need for A/D & D/A?

What is ft ?
ii
• ft  transition frequency io
gmvgs
• Freq. where short-circuit ii
vgs ~ Cgs io
M1
common-source current vin ~
gain AI ~1
Ac small signal model
• Significance of ft : For a
given technology single
device ftmax with io  ii  gm sC  iio  gm
gs i sCgs
minimum channel length io  1  2 f  gm
t C
is a measure of max. ii gs
Substituting for gm and Cgs :
achievable circuit speed: n VGS Vt 
example in a given ft  1.5
2 L*
technology maximum where *  2 for L  1 for L  1 2 *  1
achievable bandwidth for where L is channel length
ftmax  VGS Vt 
max
an opamp ~ ftmax /10 & Lmin
CMOS Technology Evolution versus Time

ft [GHz] 10n
65n
100 0.13u 45n
0.1u
0.25u
0.18u
0.35u
10 0.6u
0.8u
1u
1.5u
1 2u
3u
6u Year
75 80 85 90 95 ’00 ’05 ’10
ft for NMOS @ (VGS - Vth = 0.5V )
*Ref: Paul R. Gray UCB EE290 course „95
International Technology Roadmap for Semiconductors, http://public.itrs.net

CMOS Device Evolution
Progression from 1975 to 2005
• Minimum feature sizes ~X1/100

• Max. cut-off frequency ft ~X300
• Minimum size device area ~1/L2
• Number of interconnect layers ~X8
 In the past 35 years, evolution of CMOS technology has
resulted in drastic increase in circuit speed and density
Note: Moore‟s Law every 18months # of transistors per sq-inch

increases x2
Impact of CMOS Scaling on

Digital Signal Processing
Direct beneficiary of VLSI technology down scaling

– Digital circuits deal with “0” & “1” signal levels only
 Not sensitive to “analog” noise
– Si Area/function reduced drastically due to
• Shrinking of feature sizes
• Increase in # of metal levels for interconnections (currently
>8 metal level v.s. only 1 in the 1970s)
– Enhanced functionality & flexibility
– Amenable to automated design & test
– “Arbitrary” precision
– Provides inexpensive storage capability

Analog Signal Processing Characteristics
• Sensitive to “analog” noise
• Has not fully benefited from technology down scaling:
– Supply voltages scale down accordingly
 Reduced voltage swings  more challenging analog
design
– Reduced voltage swings requires lowering of the
circuit noise to keep a constant dynamic range
 Higher power dissipation and chip area
• Not amenable to automated design
• Extra precision comes at a high price
• Rapid progress in DSP has imposed higher demands
on analog/digital interface circuitry
Plenty of room for innovations!
Cost/Function Comparison
DSP & Analog
• Digital circuitry: Fully benefited from CMOS device scaling
– Cost/function decreases by ~29% each year
Cost/function X1/30 in 10 years*
• Analog circuitry: Not fully benefited from CMOS scaling
– Device scaling mandates drop in supply voltages
threaten analog feasibility
Cost/function for analog ckt almost constant or increase
 Rapid shift of function implementation from processing in

analog domain to digital & hence increased need for A/D &
D/A interface circuitry
*Ref: International Technology Roadmap for Semiconductors, http://public.itrs.net

Digitally Assisted Analog Circuitry
• Analog design has indeed benefited
from the availability of inexpensive on-
chip digital capabilities
• Examples:
– Compensating/calibrating ADC & DAC
inaccuracies
– Automatic frequency tuning of filters &
VCOs
– DC offset compensation
Analog Digital Interface Circuitry

Example: Digital Audio
Analog Input
• Goal-Lossless archival and
transmission of audio signals
Analog
• Circuit functions:
Preprocessing
– Preprocessing
• Amplification A/D
• Anti-alias filtering Conversion
– A/D Conversion
• Resolution16Bits DSP
– DSP
• Storage
• Processing (e.g. recognition) D/A
Conversion
– D/A Conversion
– Postprocessing Analog
• Smoothing filter Postprocessing
• Variable gain amplification
Analog Output

Example: Typical Dual Mode Cell Phone
Contains in integrated form the following interface circuitry:
• 4 RX filters
• 3 or 4 TX filters
Dual Standard, I/Q
• 4 RX ADCs
• 2 TX DACs
Audio, Tx/Rx power
• 3 Auxiliary ADCs
control, Battery charge
• 8 Auxiliary DACs control, display, ...
Total: Filters  8
ADCs  7
DACs  12
Areas Utilizing Analog/Digital Interface Circuitry

• Communications
– Wireline communications
• Telephone related (DSL, ISDN,
CODEC)
• Television circuitry (Cable
modems, TV tuners…)
• Ethernet (Gigabit,
10/100BaseT…)
– Wireless
• Cellular telephone (CDMA,
Analog, GSM….)
• Wireless LAN (Blue tooth,
802.11a/b/g…..)
• Radio (analog & digital),
Television
• Personal Data Assistants
• Computing & Control
– Storage media (disk drives, digital
tape)
– Imagers & displays

Areas Utilizing Analog/Digital Interface Circuitry
• Instrumentation
– Electronic test equipment
& manufacturing
environment ATEs
– Semiconductor test
equipment
– Physical sensors &
actuators
– Medical equipment
• Consumer Electronics
– Audio (CD, DAT, MP3)
– Automotive control,
appliances, toys
UCB Graduate Level Analog Courses

EECS 247 - 240 - 242
• EECS 240
– Transistor level, building blocks such as opamps, buffers, comparator….
– Device and circuit fundamentals
– CAD Tools  SPICE
• EECS 247
– Filters, ADCs, DACs, some system level
– Signal processing fundamentals
– Macro-models, large systems, some transistor level, constraints such as finite gain,
supply voltage, noise, dynamic range considered
– CAD Tools  Matlab, SPICE
• EECS 242
– RF amplification, mixing
– Oscillators
– Exotic technology devices
– Nonlinear circuits

Material Covered in EE247
• Filters
– Continuous-time filters
• Biquads & ladder type filters
• Opamp-RC, Opamp-MOSFET-C, gm-C filters
• Automatic frequency tuning techniques
– Switched capacitor (SC) filters
• Data Converters
– D/A converter architectures
– A/D converter
• Nyquist rate ADC- Flash, Pipeline ADCs,….
• Self-calibration techniques
• Oversampled converters
• Systems utilizing analog/digital interfaces
– Wireline communication systems- ISDN, XDSL…
– Wireless communication systems- Wireless LAN, Cellular
telephone,…
– Disk drive electronics
Books (on reserve @ Eng. Library)

(NOT required to be purchased)
• Filters
– A. Williams and F. Taylor, Electronic Filter Design Handbook, 3rd edition, McGraw-Hill,
1995.
– W. Heinlein & W. Holmes, “Active Filters for Integrated Circuits”, Prentice Hall Int., Inc.
Chap. 8, 1974. Good reference for signal flowgraph techniques
– A. Zverev, Handbook of Filter Synthesis, Wiley, 1967.
A classic; focus is on passive ladder filters. Tables for implementing ladder filters (replaces
a CAD tool).
• Data Converters
– R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd
edition, Kluwer, 2003.
– B. Razavi, Data Conversion System Design, IEEE Press, 1995.
– S. Norsworthy et al (eds), Delta-Sigma Data Converters, IEEE Press, 1997.
• General
– Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
– Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
 Note: List of relevant IEEE publications is posted on the course website under
“Reading Material”. Some will be noted as mandatory reading and the rest optional

Introduction to Filters
• Filtering  Provide frequency selectivity and/or phase shaping
– Oldest & most common type of signal processing
Signal Signal
Amplitude Amplitude
0 freq. 0 freq.
Lowpass
Filter Vout
Vin
Introduction to Filters
• Typical filter applications:

– Extraction of desired signal from many
(radio, TV, cell phone, ADSL…..)
– Separating signal and noise
– Anti-aliasing or smoothing
– Phase equalization
– Amplifier bandwidth limitations

Ideal versus Practical Filters
Example: Lowpass Filter
• Ideal filter • Practical filter

– Flat magnitude response in – Ripple in passband
the passband magnitude response
– Brick-wall transition – Limited rejection of out-of-
– Infinite level of rejection of band signals
out-of-band signals
H  jf  H  jf 
frequency
frequency
Ideal Lowpass Brick-Wall Filter More Practical Filter
Simplest Filter
First-Order Lowpass RC Filter
R
(Z=R) C
(Z=1/sC)
Steady-state frequency response:

Vout ( s ) 1 1
H( s )  sC 

Vin ( s ) R  1 1  RCs
sC
1 1
with o   H( s ) 
s
RC 1
o
S-Plane Poles and Zeros
1
s-plane (pzmap):
H (s)  j
s
1
o
p   o
Pole:
p=-o s
Zero: z  
1 1
H (s)  
 2
1 j 
o 1
2
o
Magnitude Response Characteristics
• Typically, magnitude response is plotted as a function of frequency and

in terms of decibel [dB]
1
 2 
20 log  H ( s )   20 log  10 log  1  
 2 

2
 o 
1
2

o
  o  20 log  H ( s )   3dB
• The frequency where magnitude response changes by 3dB is called the
corner or in the case of lowpass filter cut-off frequency

Simplest Filter
First-Order Lowpass RC Filter Example
R1=150 kOHM C1
10pF
Steady-state frequency response:
Vout ( s ) 1
H( s )  
s
Vin( s ) 1
o
1
with o   2 100kHz
RC
Filter Frequency Response

Bode Plot
H ( s  j )  0  1
0
Magnitude (dB)
H ( s  j )    1/ 2
-20
-40
0
-60
-100dB!
H ( s  j )    0 -80
-100
-120
0
Asymptotes:
Phase (deg)
-30
- 20dB/dec magnitude rolloff
- 90degrees phase shift per 2 decades -60
-90
1 2 3 4 5 6 7 8 9 10
10 10 10 10 10 10 10 10 10 10
Frequency [Hz]
Question:
can we really get 100dB attenuation at 10GHz?

First-Order Lowpass RC Filter
Including Parasitics
Cp=10fF
R1=150kOHM
C1
10pF
1 1
1  sRCP Pole : p 
R C  CP 
H ( s)  RC
1  sRC C P  Zero : z
1
RC P
Filter Frequency Response

0
Magnitude (dB)
-20
H ( j )  0  1 -40
CP
H ( j )  
-60
C  CP -80
0
CP
Phase (deg)

C -45
 103
 60dB
-90
2 3 4 5 6 7 8 9 10
10 10 10 10 10 10 10 10 10
Frequency [Hz]
• Beware of important parasitics & include them in the model …

Dynamic Range & Electronic Noise
• Dynamic range is defined as the ratio of maximum

possible signal handled by a circuit and the minimum
useful signal
– Maximum signal handling capability usually determined by
maximum possible voltage swings which in turn is a
function of supply voltage & circuit non-linearity
– Minimum signal handling capability is normally
determined by electronic noise
• Amplifier noise due to device thermal and flicker noise
• Resistor thermal noise
• Dynamic range in analog ckts has direct implications
for power dissipation
Analog Dynamic Range

Example: First Order Lowpass Filter
• Once the poles and zeroes of the analog filter
transfer function are defined then special attention
must be paid to the actual implementation
• Of the infinitely many ways to build a filter with a

given transfer function, each of those combinations
result in a different level of output noise!
• As an example noise and dynamic range for the 1st

order lowpass filter will be derived

First Order Filter Noise
• Capacitors are
noiseless
• Resistors have thermal R
vIN vOUT
noise
– This noise is uniformly
distributed in the C
frequency domain from
dc to infinity
– Frequency-independent
noise is called “white
noise”
Resistor Noise
• Resistor noise
characteristics
– A mean value of zero R
– A mean-squared value vIN vOUT
ohms
vn2  4kBTr Rf C
measurement bandwidth (Hz)

Volts2
absolute temperature (°K)
Boltzmann’s constant = 1.38e-23 J/°K

Resistor Noise
• Theoretically, resistor rms
noise voltage in a 10Hz band
centered at 1kHz is the same
as resistor rms noise in a R
10Hz band centered at 1GHz vIN vOUT
• Resistor noise spectral
density, N0, is the rms noise
C
per Hz of bandwidth:
vn2
N0   4k BTr R
f
Resistor Noise
Good numbers to memorize:
• N0 for a 1k resistor at room
temperature is 4nV/Hz
R
• Scaling R, vIN vOUT
– A 10M resistor gives 400nV/Hz
– A 50 resistor gives 0.9nV/Hz
C
• Or, remember
kBTr = 4x10-21 J (Tr = 17 oC)
• Or, remember
kBTr /q = 26mV (q = 1.6x10-19 C)

• To derive noise @ the output
node:
– Short circuit the input to
ground. R
– Resistor noise gives the filter a
- + vOUT
vIN
non-zero output when vIN=0 e
– In this simple example, both
the input signal and the C
resistor noise obviously have
the same transfer functions to
the output
– Since noise has random
phase, we can use any
polarity convention for a noise
source (but we have to use it
consistently)

• What is the thermal noise of this R=8k
RC filter? vIN - + vOUT
e
• Let‟s ask SPICE!
Netlist: C=1nF
*Noise from RC LPF

vin vin 0 ac 1V
r1 vin vout 8kOhm
c1 vout 0 1nF 1
.ac dec 100 10Hz 1GHz o   2  2 0k H z
.noise V(vout) vin RC
.end

Output Noise Spectral Density
100
Noise Spectral Density [nV/Hz]

20 kHz corner
10
N 0  4k BTr R
1 nV
 8 4
Hz
nV
 11.3
0.1 Hz
0.01
101 103 105 107 109 [Hz]
Total Noise
• Total noise is what the display on a volt-meter connected to vo
would show!
• Total noise is found by integrating the noise power spectral
density within the frequency band of interest
• Note that noise is integrated in the mean-squared domain,
because noise in a bandwidth df around frequency f1 is
uncorrelated with noise in a bandwidth df around frequency f2
– Powers of uncorrelated random variables add
– Squared transfer functions appear in the mean-squared integral
f2
vo2   vn2 H( j ) 2df
f1

vo2   4kB T R H( 2 jf ) 2df
0
*Ref: “Analysis & Design of Analog Integrated Circuits”, Gray, Hurst, Lewis, Meyer- Chapter 11

Total Noise

vo2   4kBTR H( 2 jf ) df
2
0
 2 
1 1 
  4kBTR df  4kBTR  df  4kBTRx 1 tan 1  2 RCf 
0
1  2 jfRC 0 1   2 fRC 2 2 RC 0
 vo2  kBT
C
• This interesting and somewhat counter intuitive result means that even
though resistors are the components generating the noise, total noise is
determined by noiseless capacitors!
• For a given capacitance, as resistance goes up, the increase in noise

density is balanced by a decrease in noise bandwidth
kT/C Noise
• kT/C noise is a fundamental analog circuit limitation
• The rms noise voltage of the simplest possible (first order) filter is
(kBT/C)1/2
• For 1pF capacitor, (kBT/C)1/2 = 64 V-rms (at 298°K)
• In our example C=1000pF gives 2 V-rms
• The noise of a more complex & higher order filter is given by:
(a x kBT/C)1/2
where a depends on implementation and features such as filter order

Lowpass Filter Total Output Noise
100
Integrated Noise Voltage [ Vrms]
Noise Spectral Density [nV/Hz]
10
2Vrms
1
0.1
0.01
101 103 105 107 109 [Hz]
Lowpass Filter Output Noise
• Note that the integrated noise essentially

stops growing above 100kHz for this lowpass
filter with f-3dB=20kHz
• Beware of faulty intuition which might tempt

you to believe that an 80, 1000pF filter has
lower total output noise compared to our
8000, 1000pF filter…

Lowpass Filter Output Noise
100
Integrated Noise Voltage ( Vrms)

Noise Spectral Density (nV/Hz)
80 &1000pF 8000 & 1000pF
10
0.1
0.01
101 103 105 107 109 [Hz]
Analog Circuit Dynamic Range

• Maximum voltage swing for analog circuits (assuming no inductors
are used!) can at most be equal to power supply voltage VDD
(normally is smaller)
1 VDD
• Assuming a sinusoid signal  Vmax ( rms) 
2 2
k T
• Noise for a filter  Vn (rms )  a B
C
V (rms ) VDD C
D.R.  max  [V/V]
Vn (rms ) 8a k BT
 Dynamic range in dB is:

 C
 20log10  VDD   75 [dB] with C in [pF]
 a

Analog Circuit Dynamic Range
• For integrated circuits built in modern CMOS

processes, VDD < 1.5V and C < 100pF
– D.R. < 98 dB (assuming a = 1)
• For printed-circuit board type circuits built with “old-

fashioned” 30V opamps and discrete capacitors of <
100nF
– D.R . < 140dB

– A 42dB advantage!
Dynamic Range versus Number of Bits
• Number of bits and dynamic range in terms of dB are

related:
D.R.  1.76  6.02 N  [dB] N  number of bits
– see “quantization noise”, later in the course
• Hence
98 dB  16 Bits
140 dB  23 Bits

Dynamic Range versus Power Dissipation
• Addition of each extra bit corresponds to 6dB extra dynamic range

• Increasing dynamic range by one bit  6dB less noise  decrease in
noise power by 4x!
• This translates into 4x larger capacitors
• To keep speed constant (speed prop Gm/C): Gm must increase 4x
• Power dissipation is proportional to Gm increases by 4x(for fixed supply and
Vdsat)
In analog circuits with performance limited by thermal noise,

1 extra bit costs 4x extra power dissipation
E.g. 16Bit ADC at 200mW  17Bit ADC at 800mW
Do not overdesign the dynamic range of analog circuits!
Noise & Dynamic Range Summary
• Thermal noise is a fundamental property of

(electronic) circuits
• In filters, noise is closely related to
– Capacitor size
• In higher order filters, noise is a function of C, filter
order, Q, and depends on implementation
• Operational amplifiers used in active filters can also
contribute significant levels of extra noise to overall
filter noise
• Reducing noise in most analog circuits is costly in
terms of power dissipation and chip area

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EECS 247

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 1

Instructor‟s Technical Background

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 2

• Course web page:

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 3

Office Hours & Grading

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 4

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 5

Analog-Digital Interface Circuitry

Analog Output Analog Input

Analog/Digital Digital Digital/Analog

• Naturally occurring signals are analog

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 6

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 7

CMOS Technology Evolution versus Time

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 8

• Minimum feature sizes ~X1/100

Note: Moore‟s Law every 18months # of transistors per sq-inch

Impact of CMOS Scaling on

Direct beneficiary of VLSI technology down scaling

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 10

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 11

 Rapid shift of function implementation from processing in

*Ref: International Technology Roadmap for Semiconductors, http://public.itrs.net

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 12

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 13

Analog Digital Interface Circuitry

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 14

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 15

Areas Utilizing Analog/Digital Interface Circuitry

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 16

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 17

UCB Graduate Level Analog Courses

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 18

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 19

Books (on reserve @ Eng. Library)

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 20

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 21

• Typical filter applications:

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 22

• Ideal filter • Practical filter

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 23

Steady-state frequency response:

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 25

Magnitude Response Characteristics

• Typically, magnitude response is plotted as a function of frequency and

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 26

Steady-state frequency response:

Filter Frequency Response

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 28

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 29

Filter Frequency Response

• Beware of important parasitics & include them in the model …

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 30

• Dynamic range is defined as the ratio of maximum

EECS 247 Lecture 1: Introduction © 2010 H.K. Page 31

Analog Dynamic Range

• Of the infinitely many ways to build a filter with a