GSM Based Home Security System

GSM BASED HOME SECURITY SYSTEM
CHAPTER 1 INTRODUCTION
1. INTRODUCTION
The project is aimed at developing the security of Home against Intruders , Gas Leak and Fire . In any of the above three cases any one met while you are out of your home than the device sends SMS to the emergency no provided to it.The report consists of a background into the area of 8051 microcontroller and mobile communication. In this project we interfaced 8051 microcontroller with Motorolas C168 GSM mobile phone to decode the received message and do the required action. The microcontroller pulls the SMS received by phone, decode it, recognizes theMobile no. and then switches on the relays attached to its port to control the appliances. After successful operation, controller sends back the acknowledgement to the users mobile through SMS.
ST.ANNS COLLEGE OF ENGINEERING AND TECHNOLOGY
Page 1
CHAPTER 2 8051 2.1. Block diagram of 8051
fig: 2.1.1 Block Diagram of 8051
Page 2
2.2. Pin Configuration
Fig: 2.2.1 Pin Configuration of 8051
Page 3
2.3.Pindescription
Page 4
Page 5
Page 6
CHAPTER 3 FUNCTIONAL DESCRIPTION 3.1. Power-On reset code execution

Following reset, the P89V51RD2 will either enter the Soft ICE mode (if previously enabled via ISP command) or attempt to auto baud to the ISP boot loader. If this auto baud is not successful within about 400 ms, the device will begin execution of the user code.
3.2. In-System Programming (ISP)

In-System Programming is performed without removing the microcontroller from the system. The In-System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89V51RD2 through the serial port. This firmware is provided by Philips and embedded within each P89V51RD2 device. The Philips In-System Programming facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD, VSS, TxD, RxD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.
3.3. Input/output (I/O) ports

32 of the pins are arranged as four 8-bit I/O ports P0P3. Twenty-four of these pins are dual purpose with each capable of operating as a control line or part of the data/address bus in addition to the I/O functions. Details are as follows:
Page 7
Port 0 This is a dual-purpose port occupying pins 32 to 39 of the device. The port is an opendrain bidirectional I/O port with Schmitt trigger inputs. Pins that have 1s written to them float and can be used as high-impedance inputs. The port may be used with external memory to provide a multiplexed address and data bus. In this application internal pull-ups are used when emitting 1s. The port also outputs the code bytes during EPROM programming. External pull-ups are necessary during program verification. Port 1 This is a dedicated I/O port occupying pins 1 to 8 of the device. The pins are connected via internal pull-ups and Schmitt trigger input. Pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs; as inputs, pins that are externally pulled low will source current via the internal pull-ups. The port also receives the low-order address byte during program memory verification. Pins P1.0 and P1.1 could also function as external inputs for the third timer/counter i.e.: (P1.0) T2 Timer/counter 2 external count input/clockout (P1.1) T2EX Timer/counter 2 reload/capture/direction control Port 2 This is a dual-purpose port occupying pins 21 to 28 of the device. The specification is similar to that of port 1. The port may be used to provide the high-order byte of the address bus for external program memory or external data memory that uses 16-bit addresses. When accessing external data memory that uses 8-bit addresses, the port emits the contents of the P2 register. Some port 2 pins receive the high-order address bits during EPROM programming and verification. Port 3 This is a dual-purpose port occupying pins 10 to 17 of the device. The specification is similar to that of port 1. These pins, in addition to the I/O role, serve the special features of the 80C51 family; the alternate functions are summarized below: P3.0 P3.1 P3.2 RxD serial data input port TxD serial data output port INT0 external interrupt 0
Page 8
P3.3 P3.4 P3.5 P3.6 P3.7
INT1 external interrupt 1 T0 timer/counter 0 external input T1 timer/counter 1 external input WR external data memory writes strobe RD external data memory read strobe.
3.4. Timers/counters 0 and 1

The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured tooperate either as timers or event counters (see Table 12 and Table 13). In the Timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of six oscillator periods, the count rate is 16 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register in the machine cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 112 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. In addition to the Timer or Counter selection, Timer 0 and Timer 1 have four operating modes from which to select. The Timer or Counter function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text.
Page 9
TMOD - Timer/Counter mode control register (address 89H) bit allocation Not bit addressable; Reset value: 00000000B; Reset source(s): any source
TMOD - Timer/Counter mode control register (address 89H) bit description
TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating mode
Page 10
; Reset value: 00000000B; Reset source(s): any reset
TCON - Timer/Counter control register (address 88H) bit allocation Bit addressable
TCON - Timer/Counter control register (address 88H) bit description
Page 11
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a fixed divide-by-32 prescaler. Figure 7 shows Mode 0 operation.
Page 12
Fig: 3.4.1 Timer/counter 0 or 1 in mode 0
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function Register TCON (Figure 6). The GATE bit is in the TMOD register. The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers. Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 7). There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Mode 1
Page 13
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used.
Fig: 3.4.2 Timer/Counter 0 or 1 in mode 1
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 9. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.
Page 14
Mode 3
When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 and Timer 0 is shown in Figure 10. TL0 uses the Timer 0 control bits: T0C/T, T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, the P89V51RD2 can look like it has an additional Timer. Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.
Page 15
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate Generator which are selected according to Table 17 using T2CON (Table 18 and Table 19) and T2MOD (Table 20 and Table 21). Timer 2 operating mode
T2CON - Timer/Counter 2 control register (address C8H) bit allocation
Page 16
T2MOD - Timer 2 mode control register (address C9H) bit allocation
Page 17
T2MOD - Timer 2 mode control register (address C9H) bit description
3.5 .Capture mode

In the Capture Mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which upon overflowing sets bit TF2, the Timer 2 overflow bit. The capture mode is illustrated in Figure 11.
Fig: 3.5.1 Timer 2 in capture mode This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt). The Timer 2
Page 18
interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt. There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2 pin transitions or fosc/6 pulses. Since once loaded contents of RCAP2L and RCAP2H registers are not protected, once Timer2 interrupt is signalled it has to be serviced before new capture event on T2EX pin occurs. Otherwise, the next falling edge on T2EX pin will initiate reload of the current value from TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to previously reported interrupt.
3.6. Auto-reload mode (up or down counter)

In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (via C/T2 in T2CON), then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Table 20 and Table 21). When reset is applied, DCEN = 0 and Timer 2 will default to counting up. If the DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 12 shows Timer 2 counting up automatically (DCEN = 0).
Fig: 3.6.1 Timer 2 in auto-reload mode(DCEN=0) In this mode, there are two options selected by bit EXEN2 in T2CON register. If EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means.
Page 19
Auto reload frequency when Timer 2 is counting up can be determined from this formula:
Where Supply Frequency is either fosc (C/T2 = 0) or frequency of signal on T2 pin (C/T2 = 1). If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 is 1. Microcontrollers hardware will need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2 = 1: in the first machine cycle pin T2EX has to be sampled as 1; in the second machine cycle it has to be sampled as 0, and in the third machine cycle EXF2 will be set to 1. In Figure 13, DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.
Fig: 3.6.2 Timer 2 in auto-reload mode(DCEN=1)
Page 20
When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed.
3.7. Baud rate generator mode

Bits TCLK and/or RCLK in T2CON allow the UART) transmit and receive baud rates to be derived from either Timer 1 or Timer 2 (See Section 7.5 UARTs on page 35 for details). When TCLK = 0, Timer 1 is used as the UART transmit baud rate generator. When TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLK has the same effect for the UART receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates Timer 1 or Timer 2. Figure 14 shows Timer 2 in baud rate generator mode:
Fig: 3.7.1 Timer 2 in Baud Rate Generator Mode The baud rate generation mode is like the auto-reload mode, when a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are determined by Timer 2s overflow rate given below:
Page 21
Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate/16 The timer can be configured for either timer or counter operation. In many applications, it is configured for timer' operation (C/T2 = 0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e., 16 the oscillator frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the baud rate formula is as follows: Modes 1 and 3 Baud Rates =
Where: (RCAP2H, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 22 shows commonly used baud rates and how they can be obtained from Timer 2.
3.8. Summary of baud rate equations
Page 22
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Baud rate = Timer 2 overflow rate / 16 If Timer 2 is being clocked internally, the baud rate is: Baud rate = fosc / (16 (65536 - (RCAP2H, RCAP2L))) Where fosc = oscillator frequency To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: RCAP2H, RCAP2L = 65536 - fosc / (16 baud rate) Table 22: Timer 2 generated commonly used baud rates
3.9. POWER SUPPLY

The power supply section is the important one. It should deliver constant output regulated power supply for successful working of the project. A 0-5V Vcc is used for our purpose; the primary of this power is connected in to main supply through on/off switch & fuse for protecting from overload and short circuit protection. The secondary is connected to the diodes convert from 12V AC to 12V DCvoltage, which is further regulated to +5v, by usingIC 7805.
Page 23

+12V IC 1 C1 1 LM7805 3 C2 47u F /16V +5V
D1 L1 230V AC 230/0-12V D4 1N 4007 D2 1N 4007 1N 4007 D3 1N4007
2 1000u F /25V
Fig: 3.9.1 Power Supply Unit
3.10. Regulator IC (LM 7805)
Fig: 3.10.1 Pins of LM7805 The LM7805 monolithic 3-terminal positive voltage regulators employ internal current-limiting, thermal shutdown and safe-area compensation, making them essentially indestructible. If adequate heat sinking is provided, they can deliver over 1.0A output current. They are intended as fixed voltage regulators in a wide range of applications including local (on-card) regulation for elimination of noise and distribution problems associated with single-point regulation. In addition to us these devices can be used with external components to obtain adjustable output voltages and currents. Considerable effort was expended to make the entire series of regulators easy to use and minimize the number of external components. It is not necessary to bypass the output, although this does improve transient response. Input bypassing is needed only if the regulator is located far from the filter capacitor of the power supply.
Page 24
3.11. RS-232
Information being transferred between data processing equipment and peripherals is in the form of digital data which is transmitted in either a serial or parallel mode. Parallel communications are used mainly for connections between test instruments or computers and printers, while serial is often used between computers and other peripherals.Serial transmission involves the sending of data one bit at a time, over a single communications line. In contrast, parallel communications require at least as many lines as there are bits in a word being transmitted (for an 8-bit word, a minimum of 8 lines are needed).Serial transmission is beneficial for long distance communications, whereas parallel is designed for short distances or when very high transmission rates are required.
Fig: 3.11.1 9-pin Configuration
3.12.Standards
One of the advantages of a serial system is that it lends itself to transmission over telephone lines. The serial digital data can be converted by modem, placed onto a standard voicegrade telephone line, and converted back to serial digital data at the receiving end of the line by another modem. Officially, RS-232 is defined as the Interface between data terminal Equipment and data communications equipment using serial binary data exchange. This definition defines data terminal equipment (DTE) as the computer, while data communications equipment (DCE) is the modem. A modem cable has pin-to-pin connections, and is designed to connect a DTE device to a DCE device.
ST.ANNS COLLEGE OF ENGINEERING AND TECHNOLOGY Page 25
3.13. Interfaces
In addition to communications between computer equipment over telephone lines, RS232 is now widely used for direct connections between data acquisition devices and computer systems. As in the definition of RS-232, the computer is data transmission equipment (DTE). However, many interface products are not data communications equipment (DCE). Null modem cables are designed for this situation; rather than having the pin- to-pin connections of modem cables, null modem cables have different internal wiring to allow DTE devices to communicate with one another.
3.14. Cabling Options

RS-232 cables are commonly available with either 4, 9 or 25-pin wiring. The 25-pin cable connects every pin; the 9-pin cables do not include many of the uncommonly used connections; 4-pin cables provide the bare minimum connections, and have jumpers to provide handshaking for those devices that require it. These jumpers connect pins 4, 5 and 8, and also pins 6 and 20.The advent of the IBM PC AT has created a new wrinkle in RS-232 communications. Rather than having the standard 25-pin connector, this computer and many new expansion boards for PCs feature a 9-pin serial port. To connect this port to a standard 25- pin port, a 9-to-25-pin adaptor cable can be utilized, or the user can create his own cable specifically for that purpose
3.15. UART
The UART operates in all standard modes. Enhancements over the standard 80C51 UART include Framing Error detection, and automatic address recognition. Mode 0 Serial data enters and exits through RxD and TxD outputs the shift clock. Only 8 bits are transmitted or received, LSB first. The baud rate is fixed at 16 of the CPU clock frequency. UART configured to operate in this mode outputs serial clock on TxD line no matter whether it sends or receives data on RxD line.
Page 26
Mode 1 10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 12 overflow rate. More about UART mode 1 Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and (b) Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. Mode 2 11 bits are transmitted (through TxD) or received (through RxD): start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned Or (e.g. the parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data bit goes into RB8 in
Page 27
Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 116 or 132 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. Mode 3 11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1/2 overflow rate. More about UART modes 2 and 3 Reception is performed in the same manner as in mode 1. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. Table 23: SCON - Serial port control register (address 98H) bit allocation
Page 28
Table 24: SCON - Serial port control register (address 98H) bit description
Page 29
Table 25: SCON - Serial port control register (address 98H) SM0/SM1 mode definition
3.16. Framing error

Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0, SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0 is set to 1.
3.17. Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed so that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in a way that the 9th bit is 1 in an address byte and 0 in the data byte. With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is 0. However, an address byte having the 9th bit set to 1 will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed or not. The addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that follow.
Page 30
The slaves that werent being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error flag. When UART receives data in mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
3.18. Automatic address recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled for the UART by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the Given address or the Broadcast' address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two Special Function Registers are used to define the slaves address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are dont careThe SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves.Use of the given address allows multiple slaves to be recognized while excluding others.
Page 31
Fig: 3.18.1 Schemes used by UART The following examples will help to show the versatility of this scheme. Table 26: Slaves 0 and 1 scheme examples
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both
Page 32
slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0
3.19. Watchdog timer

The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and automatic recovery. To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period. If the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (WDRE = 1). The software can be designed such that the WDT times out if the program does not work properly. The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a Watchdog counter rather than a Watchdog timer. The WDT register will increment every 344,064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT. The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear WDTS by writing 1' to it. Figure 19 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control Watchdog timer operation. During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt exit from idle. The time-out period of the WDT is calculated as follows: Period = (255 - WDTD) 344064 1/fCLK (XTAL1) Where WDTD is the value loaded into the WDTD register and fosc is the oscillator frequency.
Page 33
Fig: 3. 19.1 Block diagram of Watchdog timer Table 33: WDTC - Watchdog control register (address COH) bit allocation
Table 34: WDTC - Watchdog control register (address COH) bit description
Page 34
3.20. Security Bit

The Security Bit protects against software piracy and prevents the contents of the flash from being read by unauthorized parties in Parallel Programmer Mode. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. When the Security Bit is activated all parallel programming commands except for Chip-Erase are ignored (thus the device cannot be read). However, ISP reads of the users code can still be performed if the serial number and length has not been programmed. Therefore, when a user requests to program the Security Bit, the programmer should prompt the user and program a serial number into the device.
3.21. Reset
A system reset initializes the MCU and begins program execution at program Memory location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ALE, PSEN are weakly pulled high during reset. During reset, ALE and PSEN output a high level in order to perform a proper reset. This level must not be affected by external element. A system reset
Page 35
will not affect the 1 kbyte of on-chip RAM while the device is running, however, the contents of the on-chip RAM during power up are indeterminate.
3.22. Power-on Reset

At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash. When power is applied to the device, the RST pin must be held HIGH long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 mF capacitor and to VSS through an 8.2 kW resistor as shown in Figure 26. Note that if an RC circuit is being used, provisions should be made to ensure the VDD rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10 milliseconds. For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an
Page 36
indeterminate location, which may cause corruption in the code of the flash. The power-on detection is designed to work as power-up initially, before the voltage reaches the brown-out detection level. The POF flag in the PCON register is set to indicate an initial power-up condition. The POF flag will remain active until cleared by software. Please refer to the PCON register definition for detail information. Following reset, the P89V51RD2 will either enter the SoftICE mode (if previously enabled via ISP command) or attempt to autobaud to the ISP boot loader. If this autobaud is not successful within about 400 ms, the device will begin execution of the user code.
Fig: 3.22.1. Power-on reset circuit.
3.23. Software reset

The software reset is executed by changing FCF[1] (SWR) from 0 to 1. A software
ST.ANNS COLLEGE OF ENGINEERING AND TECHNOLOGY Page 37
reset will reset the program counter to address 0000H. All SFR registers will be set to their reset values, except FCF[1] (SWR), WDTC[2] (WDTS), and RAM data will not be altered.
3.24. Brown-out detection reset

The device includes a brown-out detection circuit to protect the system from severed supplied voltage VDD fluctuations. The P89V51RD2s brown-out detection threshold is 3.85 V. For brown-out voltage parameters. When VDD drops below this voltage threshold, the brown-out detector triggers thecircuit to generate a brown-out interrupt but the CPU still runs until the suppliedvoltage returns to the brown-out detection voltage VBOD. The default operation for a brown-out detection is to cause a processor reset.VDD must stay below VBOD at least four oscillator clock periods before the brown-outdetection circuit will respond.Brown-out interrupt can be enabled by setting the EBO bit in IEA register (addressE8H, bit 3). If EBO bit is set and a brown-out condition occurs, a brown-out interrupt will be generated to execute the program at location 004BH. It is required that the EBO bit be cleared by software after the brown-out interrupt is serviced. EBO bit when the brown-out condition is active will properly reset the device. If brown-out interrupt is not enabled, a brown-out condition will reset the program toresume execution at location 0000H.
3.25. Power-down mode

The Power-down mode is entered by setting the PD bit in the PCON register.In the Power-down mode, the clock is stopped and external interrupts are active for levelsensitive interrupts only. SRAM contents are retained during Power-down, the minimum VDD level is 2.0 V. The device exits Power-down mode through either an enabled external level sensitive
Page 38
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits Power-down mode. Holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit.
CHAPTER 4 GSM 4.1 BLOCK DIAGRAM
L C D
D E V I C E S D E V I C E S 8 0 5 1 D E V I C E S G S M M O D E M C E L L P H O N E
Fig: 4.1.1. Transmitter.
Fig: 4.1.2 Receiver
4.2.Definition
Global system for mobile communication (GSM) is a globally accepted standard for digital cellular communication. GSM is the name of a standardization group established in 1982 to create a common European mobile telephone standard that would formulate specifications for a pan-European mobile cellular radio system operating at 900 MHz. It is estimated that many countries outside of Europe will join the GSM partnership.
Page 39
4.3.Overview
This tutorial provides an introduction to basic GSM concepts, specifications,networks, and services. A short history of network evolution is provided in order set the context for understanding GSM.
4.4. Introduction to GSM Modem

The modem delivers all the power of instant wireless connectivity to your multiple applications. Because the modem is fully type approved, it can dramatically speed up the time to market with SMS features.Housed in a rugged aluminium alloy extrusion casing with good aesthetics and surface finish to withstand toughest field environments. The open interfaces and AT commands can embed and run your applications very efficiently. With its proven technology, the modem can be relied on for enduring and dependable performance.
4.5. FEATURES 1
Dual band EGSM/GPRS module (EGSM 900/1800 MHz, EGSM 950/1900 MHz) designed for M2M and automotive applications. Compliant with ETSI GSM Phase 2+ standard. Class 4 (2W @ 900MHz). Class 1 (1W @ 1800MHz) Less than 3.5mA current is required during the idle mode. Remote control by AT commands (according to GSM 07.07 and GSM 07.05). Can be used with normal SIM card with GPRS facility activated by the service provider.
Page 40
Standard RS-232 interface using 9 pin D connector provided with the device for communication. Modem can be linked to a PC or a micro-controller based embedded system for sending SMS . Data circuit asynchronous, transparent and non-transparent upto 14400 bits/s and baud rate of 30 to 115,200 bits/s. GPRS class 2. Coding schemes: CS1 to CS4. Point to Point(MT/MO) and Cell Broadcast. Latch type SIM holder (3V/5V SIM interface).
4.6.TECHNICAL SPECIFICATIONS
FEATURES Working Frequency Noise Transmission Power Receiving Sensitivity Working Temperature Storage Temperature Transmitting Current Receiving Current VALUES 900/1800 MHz. <-79dBm. 33dBm +/- 2dBm. -102dBm. -20C to 55C. -30C to 85C. <=2A (peak). <=80mA(peak).
Page 41
Idle mode Current Working Humidity
<3.5mA. 10% ~90% relative humidity without condensation.
Power Supply Dimensions Interface Baud rate
5 .3V to 12V DC, 2A peak. 123.5mm X 68.75mm X 23.6mm. RS-232, 9 pin D connector. 300 to 115,200 bits/s.
Page 42
CHAPTER 5 CODE 5.1. Code of the Project

#include<REG51F.H> #include"UART.c" sbit device1 = P1^0; sbit device2 = P1^1; sbit device3 = P1^2; sbit device4 = P1^3; sbit status = P2^0; main() { int i,j,k; char a[68],temp; P1=0x00; Init_Uart(); for(j=0;j<4444;j++);
send_char(0x0A); send_char(0x0D);
// catrige return // catrige return
Page 43
send_string("AT+CNMI=2,2,2,0,0"); // for send_char(0x0A); send_char(0x0D); for(i=0;i<6;i++) temp=RX_CHAR(); // just for discarding ok // catrige return // catrige return
send_char(0x0A); send_char(0x0D);
// catrige return // catrige return
send_string("AT+CMGF=1");//for making the GSM modem to work in text mode. send_char(0x0A); send_char(0x0D); for(i=0;i<6;i++) temp=RX_CHAR(); P1=0x00; while(1) { status=0; for (i=0;i<68;i++) // just for discarding ok // catrige return // catrige return
{ a[i]=RX_CHAR(); if(a[i]=='>') { k=i; // the SMS message from the mobile should be ended with '>'
Page 44
status=1; temp=SBUF; temp=SBUF; break;
} } k=k-1; if(a[k]=='1') { device1=1; } else if(a[k]=='2') { device1=0; } else if(a[k]=='3') { device2=1; } else if(a[k]=='4') { device2=0; } // DEVICE 2 Off WHEN MESSAGE UNREAD.. // DEVICE 2 ON WHEN MESSAGE UNREAD // DEVICE 1 off WHEN MESSAGE READ //DEVICE 1 ON WHEN MESSAGE READ
Page 45
else if(a[k]=='5') { device3=1; } else if(a[k]=='6') { device3=0; } else if(a[k]=='7') { device4=1; } else if(a[k]=='8') { device4=0; }
// DEVICE 3 ON WHEN MESSAGE UNREAD..
// DEVICE 3 Off WHEN MESSAGE UNREAD..
// DEVICE 4 ON WHEN MESSAGE UNREAD..
// DEVICE 4 Off WHEN MESSAGE UNREAD..
temp=SBUF; // jus for clearing the read buffer temp=SBUF; temp=SBUF; temp=SBUF; } }
Page 46
CHAPTER 6 APPLICATIONS 6.1. APPLICATIONS

The applications of the GSM/GPRS modem are as follows: 1 Pre-stored messaging Remote home appliance control. Industrial warning system. GSM based internet surfing. Automatic Meter Reading (AMR). GSM Pay Phones. Fleet/Traffic Management (with optional GPS integration). Security Systems. Mobile / Fixed Internet Connectivity. Remote Data logging and reporting. Low cost router. System to monitor data over Internet. Remote monitoring of Vending machines.
Page 47
CHAPTER 7 SOFTWARE REQUIREMENTS
7.1. SOFTWARE REQUIRMENTS

COMPILER - KEIL-uV3
Keil Software is used provide you with software development tools for 8051 based microcontrollers. With the Keil tools, you can generate embedded applications for virtually every 8051 derivative. The supported microcontrollers are listed in the -viSION
LANGUAGE
- EMBEDDED_C
CONTROLLER - P89V51RD2
Page 48
CHAPTER 8 ADVANTAGES 8.1. ADVANTAGES

This maturity means a more stable network with robust features.
Less signal deterioration inside buildings.
Ability to use repeaters.
Talktime is generally higher in GSM phones due to the pulse nature of transmission. The much bigger number of subscribers globally creates a better network effect foGSM .
Page 49
CHAPTER 9 DISADVANTAGES 9.1.DISADVANTAGES

I. Pulse nature of TDMA transmission used in 2G interferes with some electronics, especially certain audio amplifiers. 3G uses W-CDMA now. II. Intellectual property is concentrated among a few industry participants, creating barriers to entry for new entrants and limiting competition among phone manufacturers.
III.
GSM has a fixed maximum cell site range of 35 km, which is imposed by technical limitations.
Page 50
CHAPTER 10 CONCLUSION
GSM technology capable solution has provide home security and is cost-effective as compared to the previously existing systems. Hence we can conclude that the required goals and objectives of HACS have been achieved. The basic level of home appliance control and remote monitoring has been implemented. The system is extensible and more levels can be further developed using automatic motion/glass breaking detectors so the solution can be integrated with these and other detection systems. In case of remote monitoring other appliances can also be monitored such that if the level of tem-perature rises above certain level then it should generate SMS or sensors can also be applied that can detect gas, smoke or fire in case of emergency the system will automatically generate SMS.
Page 51
BIBLIOGRAPHY
1. U s e r M a n u a l P89V51RD2
2. Mahamad Ali Mazadi http://www.academypublisher.com/jnw/vol03/no02/jnw03025863.pdf
Page 52

GSM Based Home Security System

Uploaded by

Copyright:

Available Formats

GSM Based Home Security System

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

GSM Based Home Security System

Uploaded by

Copyright:

Available Formats

GSM BASED HOME SECURITY SYSTEM

ST.ANNS COLLEGE OF ENGINEERING AND TECHNOLOGY