2012 IEEE International Conference on Power Electronics, Drives and Energy Systems

December16-19, 2012, Bengaluru, India

Intentional Islanding Operations of Distributed

Generation Systems with a Load Shedding Algorithm
Geethi Krishnan and D.N.Gaonkar
Department of Electrical and Electronics Engineering
National Institute of Technology Karnataka
INDIA
k.geethi@yahoo.com,dngaonkar@gmail.com

Abstract—Intentional islanding is a condition in which a To implement a successful intentional island, the system
distributed generation source continues to supply power to the local should detect the islanding event, as soon as the grid gets
loads during a catastrophic utility failure. With a properly co- disconnected. An efficient islanding detection algorithm is
ordinated and sophisticated control scheme, islanding can be a needed for this task. Several islanding detection methods are
possible solution, to ensure reliable power to the critical loads. This
proposed in the literature. These can be broadly classified as
paper analyzes a control scheme for intentional islanding operation
of an inverter based DG system. In grid connected mode, the local methods and remote methods. Remote methods are based
interface control is designed to provide constant active and reactive on the communication between local DG and the utility grid
power to the load. When grid is disconnected, an islanding whereas local methods rely on monitoring parameters like
detection algorithm will transfer the inverter into voltage control voltage and frequency at the DG site [5]-[6].
mode. The mismatch between load and generation is removed by Many works have been reported in the literature regarding
implementing a load shedding algorithm. This paper also the interface and control of the DG systems in grid connected
investigates the performance and the Non Detection Zones of the and islanding modes. In [7], two control algorithms are
islanding detection scheme with different interface controllers. proposed for grid connected and islanded operation, with an
Key words—Distributed generation (DG), Grid connected intelligent load shedding algorithm and an algorithm for
mode, Islanded mode, Anti islanding methods, Non Detection Zone synchronization. In [8], the effect of different interface control
(NDZ), Point of Common Coupling (PCC) on islanding detection is analyzed. Reference [9] proposes a
control strategy based on voltage controlled voltage source
I. INTRODUCTION converter which inherently provide an islanding detection
The gap between the generation and demand of the power method with negligible NDZ.
provided by conventional sources of power is fast increasing. This paper presents a control strategy for grid connected as
This is due to inadequate transmission capacity and the non well as islanding modes of operation. Initially the DG system
uniform allocation of load and generating centers. The need of operates in a current controlled mode to provide the required
the hour is to tap the potential of distributed generation to power to the load. When the grid gets disconnected, a simple
meet the increasing power demand. However, many problems passive detection algorithm transfers the system to voltage
arise due to the change in power grid paradigm from the control mode. A priority based load shedding scheme, based
conventional centralized power stations to the deregulated on the measurement of the voltage at PCC, is used to
structure [1]. One of the major concerns in this regard is neutralize the load generation mismatch.
islanding. Islanding is a condition in which a part of The paper is organized as follows. Section II introduces a
study system and systematically explains the modeling of the
distribution network is supplied by a DG, even when the main
control scheme for grid connected and islanding modes.
grid is disconnected from the system [2]. The island will
Section III explains the islanding detection algorithm and the
remain operational for a long time, if the DG alone can meet analytical explanation for the NDZ. Section IV presents the
the local load demand. This may interfere with the recloser load shedding algorithm. Section V analyzes the performance
system, protection co-ordination and can even lead to hazards. of the system by conducting time domain simulations in
In spite of the fact that the likelihood of the islanding is very MATLAB/SIMULINK. Section VI concludes the paper.
less, because of the above mentioned problems, current
standards require disconnection of the DG system from the
grid when islanding is detected [3]. Also controlled islanding II. STUDY SYSTEM
can improve the reliability of the power system considerably. Fig.1 shows the single line diagram of the system under
Moreover in a system with high DG penetration, the study. The system consists of a DG represented by a dc source
disconnection can create several power quality problems. interfaced to the grid through a voltage source inverter, LC
Hence in order to maximize the benefits from DG, it is filter and a breaker. L and C represent the inductance and
advisable to go for intentional islanding. IEEE 1547 states that capacitance values of the filter and R represents the combined
one of its tasks for future consideration is the implementation ohmic losses in the filter inductor and on state resistance of the
of intentional islanding [4].

978-1-4673-4508-8/12/$31.00 ©2012 IEEE

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 VSI. Two parallel RLC loads are connected to the system. The Iq

interface control is designed with PI controllers, with the Ia Id

ω*Li

dq Id Vd is the rated voltage

control variables defined in the synchronous reference frame. Ib
+-

+
Ic abc Iq PI
+

-
Pref
A phase locked loop (PLL) is used to determine the frequency cos(wt),sin(wt)
Vgd
Divide
and angular reference at the Point of Common Coupling Va Vgd Idref
abc
(PCC). Vb dq
dq
PCC Vc abc Vd Vgq
i
Vgq Reference
CB Iqref
cos(wt),sin(wt) Divide ω*Li for PWM
R L C generation
GRID
PLL Qref
++

-
PI
+

+
LC FILER
+-

DG VSI Id
RLC 1 RLC 2
Iq
Va Vb Vc

Figure.2.Block diagram of current controlled mode of operation

Figure.1.Single line diagram of the system under study
separately, by controlling id and iq values.
Equation (2) and (3) can be rewritten as
A. Modeling of the System in DQ Frame V id ' ( s ) = V id ( s ) − V gd ( s ) − ω L i i q ( s ) (6 )
From the single line diagram,
di ( t )
V iq ' ( s ) = V iq (s) − V gq ( s ) + ω L i i d (s) (7 )
V ik ( t ) =V gk ( t ) + R i i k ( t ) + L i k
dt
(1) Vid ' ( s ) and Viq ' ( s ) can be defined as:
Ri , Li are the resistance and inductance between DG and PCC V id ' ( s ) = R i id ( s ) + S L i id ( s ) (8 )
which includes the resistance and inductance of the filter also. V iq ' ( s ) = R i i q ( s ) + sL i i q ( s ) (9 )
Vik , Vgk represents the inverter side voltage and grid side The transfer function of the system to be controlled is
voltage respectively and k=a, b, c. Vid ' ( s ) Viq ' ( s ) 1
= =G ( s ) = (10)
Applying park transformation, (1) becomes,
id ( s ) iq ( s ) Ri + sLi

di (t ) The error between the reference current and the inverter

Vid (t ) =Vgd (t ) + Ri id (t ) + Li d
dt
− ωLi iq (t ) (2) output current is processed by PI controllers. As the control is
implemented in the synchronous frame, the inputs to the PI
diq (t ) controllers are dc quantities. The controller reduces the steady
Viq ( t ) =Vgq (t ) + Ri iq (t ) + Li
dt
+ ωLiid (t ) (3) state error to zero and generate modulating reference for the
Where ‘ ω ’ is the angular frequency of the system. PWM switching.

B. Grid Connected Mode C. Islanded Mode

In grid connected mode, DG should provide constant active In autonomous or islanded mode, the above mentioned
and reactive power to the system. The voltage and frequency conventional current controlled strategy is not suitable, as
at the point of common coupling are dictated by the grid. The there is no grid to maintain the voltage and frequency at the
synchronization process is carried out by the 3 phase PLL, PCC. Hence when grid is disconnected, the interface
which sets Vgq as zero. Hence according to instantaneous controller should be switched to a voltage control mode.
power theory, real and reactive power can be represented in dq Normally, instead of directly controlling voltage, voltage
frame as control through current compensation, is suggested in the
3 3 literature. This scheme allows current limiting and enhances
P= Vgd id (4) Q = − Vgd iq (5) system protection.
2 2 Iq
Where Vgd is the maximum value of the voltage at the point ωLi
Ia
of common coupling and id and iq are the components of the Ib dq Id
Id
-
+-

PI +
current in the dq axis. According to (4) and (5), active and Ic abc Iq Vgdref
Vgd
+

reactive power components can be decoupled and controlled

+-

PI
cos(wt),sin(wt) Idref
Va Vgd abc
Vb dq dq
abc
Vc Id Reference
Vgq Iqref
cos(wt),sin(wt) ωLi for PWM
+-

PI generation
PLL +
+-

Vgqref PI +
+
Iq
Vgq
Va Vb Vc

Figure.3.Block diagram for islanded mode of operation

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 III. ISLANDING DETECTION ALGORITHM IV. LOAD SHEDDING ALGORITHM
In our system we consider a simple hybrid passive islanding With the suggested islanding detection algorithm, some
detection method based on frequency (OFP/UFP) and voltage load generation mismatch is needed, for transferring the
(OVP/UVP) measurement, for implementing the intentional control from grid connected to islanded mode. But such a
islanding operations. The frequency and voltage variations are system cannot sustain an island due to the excessive variation
dependent on the load generation mismatch. If these of frequency and voltage. Hence, when the required demand is
parameters exceed the threshold specified by the algorithm, more, some load should be cut off using an efficient load
islanding will be detected. shedding scheme, to prevent the voltage and frequency
An islanding detection algorithm should be collapse. Here a priority based load shedding is implemented.
dependable, secure and fast. It should discriminate between The magnitude of the voltage at the PCC, obtained from the
islanding and other events and should detect all possible
DQ PLL, is continuously measured. When it crosses the
formation of islands. The threshold value is decided based on
specified voltage level, specified in the algorithm shown in
the above requirements. Moreover, with this algorithm,
Fig.5, signal is given to the circuit breaker to remove the load.
islanding is detected only if the parameter excursions remain
for a sufficient time delay. This will help to prevent the Load 2 is made to have more priority than load 1, and will not
misinterpretation of other grid dynamics for islanding. shut down until large voltage variation persists. [11]
Islanding detection algorithm is shown in Fig.4. The first voltage levels 0.15pu and 0.3pu corresponds to
But if the generation-load mismatch is negligible, this immediate trip of load 1 and load 2. The second voltage level
algorithm cannot detect islanding within the required time 0.1pu triggers a load shedding command only when the
frame and will produce Non Detection Zones. NDZ is defined voltage remains there for the specified time delay. T1 and T2
as the range of loads for which islanding is not detected. For a are the delay time for load 1 and load 2 respectively, where
constant power controlled interface operating in unity power T2>T1
factor mode, the NDZ for OVP/UVP and OFP/UFP can be
derived as (11) and (12) V. SIMULATION RESULTS AND DISCUSSION

[V V
max
]2 − 1 ≤
ΔP
P
[
≤ V V
min
]2 − 1 ( 11 )
The performance of the system in grid connected and
islanding mode of operation is analyzed using the simulated
Qf . (
1 − ⎡⎢ f f
⎣ max ⎥⎦ P
)
⎤ 2 ≤ ΔQ ≤ Qf . (
1 − ⎡⎢ f f
⎣
⎤2
min ⎥⎦
) (12 )
system in MATLAB/SIMULINK. The simulated system is
shown in Fig.6. The inverter is operating with unity power
Qf is the quality factor of the local load circuit and Vmax, Vmin, factor, delivering 10kW power to the load. The system
fmax and fmin represents the maximum and minimum frequency parameters are given in table 1.
and voltage limits. For a current controlled interface the NDZ
for the OFP/UFP remains the same as above but that of
Start
OVP/UVP protection turns out to be different as shown in (13)
[V V
max
] 1 ≤ ΔPP ≤ [V
− V
min
]− 1 (13 )
Vd=Vref-u1

START

S2 S1
2 2
Measure voltage 1
and frequenc y 1
0.1 0.3
Vd 0.1 0.15 Vd

Is NO YES
1.1pu<vd<0. YES
88pu Is S2==2 Is S 1==2

YES NO NO

NO
NO NO
Is 60.5Hz < Is S2==1 RETURN Is S1==1
f < 59.3Hz

YES YES
YES Increase t
Lasted for
NO
Lasted for
T2 period
NO T1 period
Is t > delay NO

YES

TRIP LOAD 2
Islanding is detec ted TRIP LOAD 1

Figure.5.Load shedding Algorithm

Figure.4.Islanding Detection Algorithm

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 VSI From
g [Pulse] LC FILTER GRID
+
A A A aA A a aA A
DG B B B bB B b bB
B
-
C C C cC C c cC
C
PCC LS CB
1

A
B
C

com
A
B
C
CB1

C
A
B
VABC Signal(s) Pulses [Pulse]

b
a

c
PWM GENERATOR

B
A

C
B
A

C
Vabc In1 RLC LOAD 1 RLC LOAD 2
Out1 [VABC]

C
B
A
C
B
A
Iabc In2
CONTROLLER

Figure.6.Simulated System
Grid gets disconnected at t=2sec.Designing the interface
control as constant current controlled, four cases as analyzed.
Active Power(watts)
4
x 10
Case1: Load is adjusted to operate the inverter at 100% 2
active power (P) balance and 100% reactive power
balance (Q) 0
Case2: Load is adjusted at 50% rated P and 100% Q balance
Case1 Case2 Case3 Case4
Case 4: Load at 100% rated P and 96.6% Q balance -2
0 0.5 1 1.5 2 2.5 3 3.5 4
Case 5: Load at 125% rated P and 103.4% Q balance. Time(s)
The simulated results are shown in Fig.7.With the above (a)
5000
Reactive Power(Var)

suggested islanding detection algorithm, only during case 4,

islanding will be detected.
0
For a constant preset current output, once islanding occurs, the
output power and voltage becomes a function of the load. It is -5000
Case1 Case2 Case3 Case4
also observed that, the performance of constant power
controlled interface during islanding operation is different from 0 1 2 3 4
Time(s)
the constant current controlled interface. The NDZ is shown in (b)
Fig.8 1.5

TABLE 1 1
Vd(pu)

SYSTEM PARAMETERS 0.5

0 case1 case2 case3 case4

INVERTER LOAD PARAMETERS -0.5

0 1 2 3 4
Switching frequency 10kHz R2 4.33Ω Time (s)
Input Dc voltage 400V L2 4.584mH (c)
Filter Inductance 4.2mH C2 1.535mF
Frequency(Hz)

Filter Capacitor 31µF R1 5.1838Ω

Voltage (Phase to ground) 120Vrms L1 4.584mH
50
DG output power 10kw C1 4.535mF
GRID PARAMETERS
Frequency 60Hz case1 case2 case3 case4
0
Grid Inductance 0.05mH 0 1 2 3 4
Grid resistance 0.02Ω Time(s)
(d)
Figure.7.Variation of (a) Active power (b) Reactive power (c) Magnitude of
voltage at PCC in pu (d) Frequency in Hz for a current controlled interface
before and after islanding

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 10 300
Reactive Power m ism atch (% )

Id and Idref
CONSTANT POWER CONTROLLED
200
CONSTANT CURRENT CONTROLLED
5 100
5.5% OF
-14% -8.17% 0% 12.8% 29%
0
0
OV UV -100
0 0.5 1 1.5 2 2.5 3 3.5 4
-5 -7.15% Time(s)
50
UF

Iq and Iqref
-10
-15 -10 -5 0 5 10 15 20 25 30
Active Power Mismatch(%)
0
Figure.8. Simulated NDZ for constant current controlled interface
and constant power controlled interface for OVP/UVP and -50
OVF/UVF protection 0 0.5 1 1.5 2 2.5 3 3.5 4
Time(s)
Figure 11: Id and Iq tracking Idref and Iqref
Certain points which are noted from the results:
1) The NDZ for the constant power controlled 1

Vabc(pu)
interface is larger comparing with the current
0
controlled interface.
2) NDZ for reactive power mismatch is less -1

comparing with the active power mismatch. Reactive 1.9 2 2.1 2.2 2.3
Time(s)
power variations are more sensitive and produce 200
notable deviations in frequency to trigger islanding
detection. When grid is not providing the desired Iabc(A)
0
reactive power, frequency varies, to reach the
resonant frequency of the load.
-200
3) With the specified islanding detection algorithm, 1.9 2 2.1 2.2 2.3
Time(s)
both active and reactive power variations are needed 1
for reliable detection. Large active power mismatch
LS

0.5
can produce frequency deviation in addition to Load sheddding command
to circuit breaker

voltage variation. But it wouldn’t result in fast 0

0 0.5 1 1.5 2 2.5 3 3.5 4
detection. 1
Time(s)
ISLANDED MODE

A. Grid connected to Islanded Mode

ID

0.5

Islanding detection algorithm continuously monitors 0

GRID CONNECTED MODE
0 0.5 1 1.5 2 2.5 3 3.5 4
the variations in the frequency and voltage at the Time(s)

PCC. After the grid gets disconnected at t=2sec, the Figure. 12. (a)Three phase voltage at the PCC (b) Three phase current from
algorithm waits for the specified time delay and will the inverter (c) Command from the load shedding algorithm to shut down the
give a switching command at 2.05sec. Load shedding load (d) Islanding detection algorithm output

algorithm works in parallel with the ID algorithm and

check for the deviation in voltage. The load 1 will be REFERENCES
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x 10
P(Watts) and Q (Var)

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