SIST, Department of EEE

SIST, Department of EEE

SIST, Department of EEE
SIST, Department of EEE
EXPERIMENT 2-DESIGN & CONSTRUCTION OF ADDER AND DIFFERENTIATOR USING OP-AMP
IC741

Vin Vout Output voltage

S. No
Theory Practical Theory Practical Vout = -(V1+V2)
1
2
RESULT:

DIFFERENTIATOR:

PROCEDURE:
1 connect the differentiator circuit as shown in fig1. Adjust the signal generator to produce a 5 volt
peak sine wave at 100 Hz.
2 observe input Vi and Vo simultaneously on the oscilloscope measure and record the peak value
of Vo and the phase angle of Vo with respect to Vi.
3. Repeat step2 while increasing the frequency of the input signal.
Find the maximum frequency at which circuit offers differentiation. Compare it with the
calculated value of fa Observe & sketch the input and output for square wave.

THEORY
The operational amplifier can be used in many applications. It can be used as
differentiator and integrator. In differentiator the circuit performs the mathematical
operation of differentiation that is the output wave form is the derivative of the input
waveform for good differentiation, one must ensure that the time period of the input
signal is larger than or equal to RfC1.the practical differentiator eliminates the problem
of instability and high frequency noise.

Waveform Amplitude Time period

( No. of div x Volts per div ) ( No. of div x Time per div )

Input

Output
MODEL GRAPH:
PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.

2. Give the input signal as specified.
3. Switch ON the dual supply.
4. Note down the o/p from CRO.
5. Draw the necessary waveform on the graph sheet.
6. Repeat the process for all circuits.

RESULT:

The a p p l i c a t i o n s of operational amplifier like Adder, Differentiator are performed

using IC 741
 EXPERIMENT 2-DESIGN & CONSTRUCTION OF OP-AMP NON LINEAR APPLICATION-
TRIANGULAR WAVE GENERATOR
AIM:
To Design and Construct the Non Linear Applications of Op -Amp using IC 741
1. Triangular Wave Generator

EQUIPMENT REQUIRED:

SL.
NAME OF THE APPARATUS RANG TYPE QTY
NO
E
1. Regulated Power Supply +12 V
DC 1 No
2. Resistors 4.7K 1 No
10 K 2 No
3. Capacitor 0.1μF 1 No
4. Operational amplifier IC 741 1 No
5. CRO 1 No
6. Breadboard 1 No

TRIANGULAR WAVEFORM GENERATOR

MODEL GRAPH

OBSERVATION

Waveform Amplitude Time period

( No. of div x Volts ( No. of div x Time
per div ) per div )

TRIANGULAR WAVE GENERATOR:

If differential amplifier and integrator are connected together in series it will generate
triangular waveform, so by combining the two circuits we get the Triangular Waveform Generator.

Frequency F = (1/T ) = [R3 / (4R1C1R2)]

PROCEDURE

Triangular Wave Generator:

1. Connect the output of the square wave generator to an integrator circuit.
2. Observe the output waveform on a CRO and frequency.

RESULT:
Thus the Non Linear Applications of Op -Amp using IC 741 was designed and constructed for
the following
1. Triangular Wave Generator
 DESIGN AND CONSTRUCTION OF PWM GENERATION USING 555 TIMER

AIM OF THE EXPERIMENT

To generate the pulse with different width using IC 555(ASTABLE IN NATURE)

CIRCUIT DIAGRAM

PLEASE INCLUDE IC CONFIGURATION OF 555 TIMER IC

Tabular column

AMPLITUDE(V) Ton(ms) Toff(ms) T= Ton+Toff(ms) T=0.69 (RA + 2RB) C

practical (theoretical)
2*2 0.12*.5 0.2*.5 .16ms

Executed file from tinker cad

Graph
Result.
 DESIGN AND CONSTRUCTION OF R-2R LADDAR USING IC741
AIM OF THE EXPERIMENT

CIRCUIT DIAGRAM

DESIGN FOR THE DATA 100

TABULAR COLUMN

DATA CONVERTERD ANALOG VALUE

000 0.00
001 -0.625
010 -1.25
011 -1.815
100 -2.5
101 -3.125
110 -3.75
111 -4.375
RESULT
P-SPICE PROGRAMS
 LOW PASS FILTER
Aim :-
To find out the Frequency Response of Low Pass Filter using P-Spice.

Program Coding :-
v1 7 0 dc 15v
v2 4 0 dc -15v
vin 1 0 ac 2v sin(0 2v 10khz)
r1 2 0 10k
r2 2 6 10k
r3 1 3 22k
c 3 0 0.01uf
rl 6 0 10k
*c2 8 6 0.0047uf
*c3 3 0 0.0047uf
x 3 2 7 4 6 uA741
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
*|||||
.subckt uA741 1 2 3 4 5
*
c1 11 12 8.661E-12
c2 6 7 30.00E-12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2),(3,0),(4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -1E3 1E3 10E6 -10E6
ga 6 0 11 12 188.5E-6
gcm 0 6 10 99 5.961E-9
iee 10 4 dc 15.16E-6
hlim 90 0 vlim 1K
q1 11 2 13 qx
q2 12 1 14 qx
r2 6 9 100.0E3
rc1 3 11 5.305E3
rc2 3 12 5.305E3
re1 13 10 1.836E3
re2 14 10 1.836E3
ree 10 99 13.19E6
ro1 8 5 50
ro2 7 99 100
rp 3 4 18.16E3
vb 9 0 dc 0
vc 3 53 dc 1
ve 54 4 dc 1
vlim 7 8 dc 0
vlp 91 0 dc 40
vln 0 92 dc 40
.model dx D(Is=800.0E-18 Rs=1)
.model dy D(Is=800.00E-18 Rs=1m Cjo=10p)
.model qx NPN(Is=800.0E-18 Bf=93.75)
.ends
.tran 0us 500us uic
.tf v(6) vin
.noise v(6) vin
.ac dec 5 10hz 1000khz
.probe
.op
.end

Simulated Output :-

Result :-
 HIGH PASS FILTER

Aim :-
To find out the Frequency Response of High Pass Filter using P-Spice.

Program Coding :-
v1 7 0 dc 15v
v2 4 0 dc -15v
vin 1 0 ac 2v sin (0 2v 10khz)
r 3 0 22k
r1 2 0 10k
rf 6 2 10k
rl 6 0 10k
c 3 1 0.01uf
x 3 2 7 4 6 ua741
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
*|||||
.subckt uA741 1 2 3 4 5
*
c1 11 12 8.661E-12
c2 6 7 30.00E-12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2),(3,0),(4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -1E3 1E3 10E6 -10E6
ga 6 0 11 12 188.5E-6
gcm 0 6 10 99 5.961E-9
iee 10 4 dc 15.16E-6
hlim 90 0 vlim 1K
q1 11 2 13 qx
q2 12 1 14 qx
r2 6 9 100.0E3
rc1 3 11 5.305E3
rc2 3 12 5.305E3
re1 13 10 1.836E3
re2 14 10 1.836E3
ree 10 99 13.19E6
ro1 8 5 50
ro2 7 99 100
rp 3 4 18.16E3
vb 9 0 dc 0
vc 3 53 dc 1
ve 54 4 dc 1
vlim 7 8 dc 0
vlp 91 0 dc 40
vln 0 92 dc 40
.model dx D(Is=800.0E-18 Rs=1)
.model dy D(Is=800.00E-18 Rs=1m Cjo=10p)
.model qx NPN(Is=800.0E-18 Bf=93.75)
.ends
.tf v(6) vin
.ac dec 5 10hz 100khz
.tran 0us 100ms uic
.probe
.op
.end

Simulated Output :-

Result :-
 BAND PASS FILTER
Aim :-
To find out the Frequency Response of Band Pass Filter using P-Spice.

Program Coding :-
v1 7 0 dc 15v
v2 4 0 dc -15v
vin 1 0 ac 2mv sin (0 2mv 10khz)
r1 1 8 4.7k
r2 8 0 6.2k
r3 3 0 10k
rl 6 0 10k
r4 2 6 100k
c1 8 2 0.01uf
c2 8 6 0.01uf
x 3 2 7 4 6 ua741
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
*|||||
.subckt uA741 1 2 3 4 5
*
c1 11 12 8.661E-12
c2 6 7 30.00E-12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2),(3,0),(4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -1E3 1E3 10E6 -10E6
ga 6 0 11 12 188.5E-6
gcm 0 6 10 99 5.961E-9
iee 10 4 dc 15.16E-6
hlim 90 0 vlim 1K
q1 11 2 13 qx
q2 12 1 14 qx
r2 6 9 100.0E3
rc1 3 11 5.305E3
rc2 3 12 5.305E3
re1 13 10 1.836E3
re2 14 10 1.836E3
ree 10 99 13.19E6
ro1 8 5 50
ro2 7 99 100
rp 3 4 18.16E3
vb 9 0 dc 0
vc 3 53 dc 1
ve 54 4 dc 1
vlim 7 8 dc 0
vlp 91 0 dc 40
vln 0 92 dc 40
.model dx D(Is=800.0E-18 Rs=1)
.model dy D(Is=800.00E-18 Rs=1m Cjo=10p)
.model qx NPN(Is=800.0E-18 Bf=93.75)
.ends
.tf v(6) vin
.tran 0us 10ms uic
.ac dec 5 10hz 1000khz
.probe
.op
.end

Simulated Output :-

Result :-
 BAND REJECT FILTERAim :-
To find out the Frequency Response of Band Reject Filter using P-Spice.

Program Coding :-
v1 7 0 dc 15v
v2 4 0 dc -15v
vin 1 0 ac 2v sin (0 2v 10khz)
r1 1 8 15k
r2 8 3 15k
r3 9 0 7.5k
c1 1 9 0.01uf
c2 9 3 0.01uf
c3 8 0 0.02uf
rl 6 0 10k
r 2 6 1ohm
x 3 2 7 4 6 ua741
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
*|||||
.subckt uA741 1 2 3 4 5
*
c1 11 12 8.661E-12
c2 6 7 30.00E-12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2),(3,0),(4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -1E3 1E3 10E6 -10E6
ga 6 0 11 12 188.5E-6
gcm 0 6 10 99 5.961E-9
iee 10 4 dc 15.16E-6
hlim 90 0 vlim 1K
q1 11 2 13 qx
q2 12 1 14 qx
r2 6 9 100.0E3
rc1 3 11 5.305E3
rc2 3 12 5.305E3
re1 13 10 1.836E3
re2 14 10 1.836E3
ree 10 99 13.19E6
ro1 8 5 50
ro2 7 99 100
rp 3 4 18.16E3
vb 9 0 dc 0
vc 3 53 dc 1
ve 54 4 dc 1
vlim 7 8 dc 0
vlp 91 0 dc 40
vln 0 92 dc 40
.model dx D(Is=800.0E-18 Rs=1)
.model dy D(Is=800.00E-18 Rs=1m Cjo=10p)
.model qx NPN(Is=800.0E-18 Bf=93.75)
.ends
.tf v(6) vin
.ac dec 5 10hz 100khz
.probe
.op
.end

Simulated Output :-

Result :-
 WEIN BRIDGE OSCILLATOR
Aim :-
To find out the Frequency Response of Wein Bridge Oscillator using P-Spice.

Program Coding :-
v1 7 0 dc 15v
v2 4 0 dc -15v
r1 1 3 1.5k
r2 3 0 1.5k
rf 6 2 2k
ri 2 0 1k
c1 3 0 0.1uf
c2 1 6 0.1uf
x 3 2 7 4 6 uA741
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
*|||||
.subckt uA741 1 2 3 4 5
*
c1 11 12 8.661E-12
c2 6 7 30.00E-12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2),(3,0),(4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -1E3 1E3 10E6 -10E6
ga 6 0 11 12 188.5E-6
gcm 0 6 10 99 5.961E-9
iee 10 4 dc 15.16E-6
hlim 90 0 vlim 1K
q1 11 2 13 qx
q2 12 1 14 qx
r2 6 9 100.0E3
rc1 3 11 5.305E3
rc2 3 12 5.305E3
re1 13 10 1.836E3
re2 14 10 1.836E3
ree 10 99 13.19E6
ro1 8 5 50
ro2 7 99 100
rp 3 4 18.16E3
vb 9 0 dc 0
vc 3 53 dc 1
ve 54 4 dc 1
vlim 7 8 dc 0
vlp 91 0 dc 40
vln 0 92 dc 40
.model dx D(Is=800.0E-18 Rs=1)
.model dy D(Is=800.00E-18 Rs=1m Cjo=10p)
.model qx NPN(Is=800.0E-18 Bf=93.75)
.ends
.tran 1ms 10ms uic
.probe
.op
.end

Simulated Output :-

Result :-
 Experiment No.1. Verification of the Basic Logic gates

AIM:

To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates.

APPARATUS REQUIRED:

S.No Name of the Apparatus IC number Quantity

1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required

THEORY:

a. AND gate:
An AND gate is the physical realization of logical multiplication operation. It is an
electronic circuit which generates an output signal of ‘1’ only if all the input signals are
‘1’.

b. OR gate:
An OR gate is the physical realization of the logical addition operation. It is an electronic
circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.

c. NOT gate:
A NOT gate is the physical realization of the complementation operation. It is an
electronic circuit which generates an output signal which is the reverse of the input signal.
A NOT gate is also known as an inverter because it inverts the input.

d. NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate will be ‘0’ if
all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.

e. NOR gate:
A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all the
inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.

f. EX-OR gate:
An Ex-OR gate performs the following Boolean function,

A B = ( A . B’ ) + ( A’ . B )
It is similar to OR gate but excludes the combination of both A and B being equal to one. The
exclusive OR is a function that give an output signal ‘0’ when the two input signals are equal
either ‘0’ or ‘1’.

PROCEDURE:

1. Connections are given as per the circuit diagram

2. For all the ICs 7th pin is grounded and 14 th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for all gates.
AND GATE

LOGIC DIAGRAM: PIN DIAGRAM OF IC 7408 :

TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y=A.B
1. 0 0 0
2. 0 1 0
3. 1 0 0
4. 1 1 1
OR GATE

LOGIC DIAGRAM: PIN DIAGRAM OF IC 7432:

TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y=A+B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 1

NOT GATE

LOGIC DIAGRAM: PIN DIAGRAM OF IC 7404

:

TRUTH TABLE:

INPUT OUTPUT
S.No
A Y = A’
1. 0 1
2. 1 0

NAND GATE

LOGIC DIAGRAM: PIN DIAGRAM OF IC 7400:

TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y = (A. B)’
1. 0 0 1
2. 0 1 1
3. 1 0 1
4. 1 1 0

NOR GATE

LOGIC DIAGRAM: PIN DIAGRAM OF IC 7402:

TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y = (A + B)’
1. 0 0 1
2. 0 1 0
3. 1 0 0
4. 1 1 0

EX-OR GATE

LOGIC DIAGRAM PIN DIAGRAM OF IC 7486:

TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y=A B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 0

RESULT:

The truth tables of all the basic digital ICs were verified.
 Experiment No.1b Verification of a Boolean function using logic gates

AIM:

To design the logic circuit and verify the truth table of the given Boolean expression,

F (A, B, C, D) = Σ (0, 1, 2, 5, 8, 9, 10)

APPARATUS REQUIRED:

S.No Name of the Apparatus IC number Quantity

1. Digital IC trainer kit 1
2. AND gate IC 7408
3. OR gate IC 7432
4. NOT gate IC 7404
5. NAND gate IC 7400
6. NOR gate IC 7402
7. EX-OR gate IC 7486
8. Connecting wires As required

DESIGN:

Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10)

The output function F has four input variables hence a four variable Karnaugh Map is used to
obtain a simplified expression for the output as shown,
From the K-Map,

F = B’ C’ + D’ B’ + A’ C’ D

Since we are using only two input logic gates the above expression can be re-written as,

F = C’ (B’ + A’ D) + D’ B’

Now the logic circuit for the above equation can be drawn.

CIRCUIT DIAGRAM:
TRUTH TABLE:

INPUT OUTPUT
S.No
A B C D F=D’B’+C’(B’+A’D)
1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
4. 0 0 1 1 0
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
9. 1 0 0 0 1
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagram

2. For all the ICs 7th pin is grounded and 14 th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the given Boolean expression.

RESULT:

The truth table of the given Boolean expression was verified.

Experiment No. 2 Construction and verification of full and half adder using logic gates.

AIM:

To design and verify the truth table of the Half Adder & Full Adder circuits.

APPARATUS REQUIRED:

S.No Name of the Apparatus IC number Quantity

1. Digital IC trainer kit 1
2. AND gate IC 7408
3. OR gate IC 7432
4. NOT gate IC 7404
5. EX-OR gate IC 7486
6. Connecting wires As required

THEORY:

The most basic arithmetic operation is the addition of two binary digits. There are four possible
elementary operations, namely,

0+0=0

0+1=1

1+0=1

1 + 1 = 102

The first three operations produce a sum of whose length is one digit, but when the last operation
is performed the sum is two digits. The higher significant bit of this result is called a carry and
lower significant bit is called the sum.

HALF ADDER:

A combinational circuit which performs the addition of two bits is called half adder. The input
variables designate the augend and the addend bit, whereas the output variables produce the sum
and carry bits.

FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder.
The three input bits include two significant bits and a previous carry bit. A full adder circuit can
be implemented with two half adders and one OR gate.
 HALF ADDER

TRUTH TABLE:

INPUT OUTPUT
S.No
A B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 0 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,

Sum, S = A B

Carry, C = A . B

CIRCUIT DIAGRAM:
 FULL ADDER

TRUTH TABLE:

INPUT OUTPUT
S.No
A B C SUM CARRY
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,

SUM = A’B’C + A’BC’ + AB’C’ + ABC

CARRY = A’BC + AB’C + ABC’ +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

SUM CARRY

SUM = A’B’C + A’BC’ + AB’C’ + ABC = A B C

CARRY = AB + AC + BC
CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14 th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

RESULT:

The design of the half adder and full adder circuits was done and their truth tables were verified.
 Experiment No.3 Design and Implementation of Encoder and Decoder:

Aim:

To design and implement encoder and decoder using logic gates.

Apparatus Required:

SI. No. COMPONENT SPECIFICATIO QTY

N
1. NOT GATE IC 7404 1

2. OR GATE IC 7432 1

3. AND Gate IC 7408 1

4. DIGITAL IC TRAINER - 1
KIT

5. PATCH CORD - -

Theory:

Encoder:

An encoder is a combinational logic circuit that has 2n input lines and n output lines.
As an example consider an four input and two output encoder. It is assumed that only
one input has ‘1’ at any given time. From truth table, it is obvious that the output is ‘1’
for A when the input is 2 and 3; B is ‘1’ when the input is 1 and 2.

De-Coder:

A decoder is a combinational circuit that converts n-bit binary input lines into 2n
output lines such that output line will be activated for only one of possible combination of
inputs. The outputs are selected based on two select inputs. The inputs AB are decoded
into four digits output each representing one of minterms of two input variables.
Logic Diagram:

4x2 Encoder:

Truth Table:

Input Output

D0 D1 D2 D3 A B
1 0 0 0 0 0

0 1 0 0 0 1

0 0 1 0 1 0

0 0 0 1 1 1

A = D2 + D3

B = D1 + D3
Logic Diagram:

2x4 De-Coder:

Truth Table:

Input Output

A B D0 D1 D2 D3
0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

D0 =

A’B’ D1

= A’B
D2 =

AB’ D3

= AB

Procedure:

1. Make the connections as per the circuit diagram.

2. Switch on VCC and apply various combinations of input according to truth table.

3. For all input combinations verify the outputs with the truth table.

Result:

Thus the Encoder and De-Coder were designed and implemented using logic gates
with their truth table verified.
 Experiment No. 4 Realization of flip flops FLIPFLOP

AIM:
To verify the characteristic table of RS, D, JK, and T Flip flops.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. NOR gate IC 7402

3. NOT gate IC 7404

4. AND gate ( three input ) IC 7410

5. NAND gate IC 7400

6. Connecting wires As required

THEORY:

A Flip Flop is a sequential device that samples its input signals and changes its output
states only at times determined by clocking signal. Flip Flops may vary in the number of
inputs they possess and the manner in which the inputs affect the binary states.

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and
R inputs reach the second level NAND gates in their complementary form. The Flip Flop
is reset when the R input high and S input is low. The Flip Flop is set when the S input is
high and R input is low. When both the inputs are high the output is in an indeterminate
state.

D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when
both inputs are high at the same time, in the D Flip Flop the inputs are never made equal
at the same time. This is obtained by making the two inputs complement of each other.

JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK

inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is NAND
 with K input and the clock pulse, similarly the output Q’ is NAND with J input and the
Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and
Q’ output retain their previous values. When the clock pulse is high, the J and K inputs
reach the NOR gates. When both the inputs are high the output toggles continuously. This
is called Race around condition and this must be avoided.

T FLIP FLOP:

This is a modification of JK Flip Flop, obtained by connecting both inputs J and K

inputs together. T Flip Flop is also called Toggle Flip Flop.

Circuit Diagram:

Truth Table RS Flip -Flop

Clock Input Present Next

Pulse S R State (Q) State(Q+1)

1 0 0 0 0

2 0 0 1 1

3 0 1 0 0

4 0 1 1 0

5 1 0 0 1

6 1 0 1 1

7 1 1 0 X

8 1 1 1 X
JK Flip -Flop

Clock Input Present Next

Pulse J K State (Q) State(Q+1)

1 0 0 0 0

2 0 0 1 1

3 0 1 0 0

4 0 1 1 0

5 1 0 0 1

6 1 0 1 1

7 1 1 0 1

8 1 1 1 0
D Flip -Flop
Result: Thus the characteristic tables of RS, D, JK, and T Flip flops are verified.
EXPERIMENT No 5 VERIFICATION OF VARIOUS SHIFT REGISTERS
RESULT: