Cambridge Institute of Technology North Campus, Bengaluru

ANALOG CIRCUITS LABORATORY-18ECL48

(for IV Sem ECE)

Subject Code: 18ECL48 IA Marks: 40

No. of Practical hrs per week: 04 Exam Marks: 60
Total no. of Practical hrs: 48 Exam Hours: 03

HARDWARE EXPERIMENTS-PART(A)

EXP. TITLE PAGE

NO. NO.
1 Design and setup the Common Source JFET/MOSFET amplifier and
plot the frequency response.

2 Design and set up the BJT common emitter voltage amplifier with
and without feedback and determine the gain- bandwidth product,
input and output impedances

3 Design and set-up BJT/FET

i) Colpitts Oscillator, and
ii) Crystal Oscillator

4 Design active second order Butterworth low pass and high pass
filters.

5 Design Adder, Integrator and Differentiator circuits using Op-Amp

Adder

6 Test a comparator circuit and design a Schmitt trigger for the given
UTP and LTP values and obtain the hysteresis.

7 Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4

bit binary input from toggle switches and (ii) by generating digital
inputs using mod-16 counter

8 Design Monostable and a stable Multivibrator using 555 Timer

SIMULATION EXPERIMENT-PART B
9 RC Phase shift oscillator and Hartley oscillator

10 Narrow Band-pass Filter and Narrow band-reject filter

11 Precision Half and full wave rectifier

12 Monostable and A stable Multivibrator using 555 Timer.

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EXPERIMENT NO-1
FET- AMPLIFIER

AIM:
Design and setup the Common Source JFET/MOSFET amplifier and plot the
frequency response.

Given VDD = 12V, IDss = 10 mA, VGS = - 2V, VP = -6 V

Theory
FET can accomplish faithful amplification only if proper associated circuitry is used. The
circuit shown is for common source amplifier. The gate resistor R G serves two purposes. It
keeps the gate at approximately 0 V DC (therefore gate current is nearly 0) and its large value
prevents loading of AC signal source. The bias voltage is provided by the drop across RS.
The bypass capacitor CS bypasses the AC signal and thus keeps the source of FET effectively
at AC ground. CC1 couples the input signal to the FET amplifier. The high input impedance
and low output impedance and low noise level make JFET far superior to the bipolar
transistor.

CIRCUIT DIAGRAM:

DESIGN:
For proper biasing: VDD=12 V; VDS = 6 V;
VS = VDD/10 = 1.2V
VGS = - 0.7 to -2V

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To find RD :

ID = IDSS (1-VGS/ VP)2

= 10x10-3 (1- 2/6)2
= 4.4 mA  5mA
Applying KVL to the output loop of the circuit
VDD = VDS + IDRD + VRS
12 = RD (5 x 10-3 ) + 6 + 1.2
RD = 960   1 k

To find RS :
VRS = ISRS
RS = VRS/IS = 1.2 / 5x10 -3  240   270
RS = 330
Assume RG = 2 M

To find CS :
XS = Rs /10= 33 
XS = 1/2𝝅fL3dBCs
CS= 48.22𝛍F
Therefore CS = 48µf

Input impedance (Zin):

For FET the input impedance is equal to RG. Therefore Zin = 2M

Output impedance (Zout):

Zo = RD
Zo = 1K

To choose the coupling capacitors C1 and C2

Input Coupling Capacitor C1=

Where, Zin is the input impedance

C1=1/(2𝝅x100x2M)
=795.77pF

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Choose Standard C1= 1000pF

Output Coupling Capacitor C2=

C2= 1/(2𝝅x100x1K)
C2= 1.59𝛍F
Choose Standard C2=1𝛍F

Procedure :

a) To plot Frequency response:

1. Rig up the circuit as per the given circuit diagram.
2. Switch on the D.C. power supply and check the D.C. conditions without any input
signal and record in table 1.
3. Select sine wave input and set the input signal frequency at 10 KHz constant, and
observe the input wave and output wave on the CRO and adjust the input
amplitude such that the output is undistorted waveform. Calculate mid-band gain
using AV = Vo(p-p) / Vin(p-p).
4. Keeping the input amplitude constant, vary the frequency from 50Hz to 1MHz
and note down the corresponding output voltage (p-p) in the table 2.
5. Calculate gain in db and plot the frequency response curve and find the
bandwidth.

b) Procedure to measure input impedance Zi:

1. Connect the circuit as in figure.

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2. Set the following:

DRB to zero.
Input sine wave amplitude of 40mV
Input sine wave frequency to any mid band frequency.

3. Measure V0(p-p)
4. Increase DRB till V0(p-p) = V0(p-)/2 . The corresponding DRB value gives
the input impedance Zin.

Procedure to measure output impedance:

1. Connect the circuit as shown in the Figure.

2. Set the following:
DRB to maximum value.
Input sine wave amplitude to 40mv.
Input sine wave frequency to any mid band frequency(10 KHz)
3. Measure VO(p-p).
4. Decrease DRB till VO = VO(p-p)/2. The corresponding DRB value gives the output
impedance ZOut.
5.
Observations
Table 1: D.C. Conditions:
Parameter VD VDS VS
Theoretical 4V 6V 1.47 V
Practical

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Table 2: Frequency response Vin = Volts

Frequency
V0 (V) AV AV (dB)
(Hz)
50
100
.
.
.
.
.
1M

FREQUENCY RESPONSE CURVE ( in Semilog )

Bandwidth = f2 – f1
Zin and Zo:

Parameter Theoretical Practical

Zin 2M
Zo

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Expected Waveform:

Results: The RC-coupled amplifier using FET was designed and rigged up. The parameters
were found matching with the design values.

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EXPERIMENT N0 2

BJT COMMON EMITTER VOLTAGE AMPLIFIER

AIM:
Design and setup the BJT Common Emitter Voltage Amplifier with and without
feedback and determine its gain bandwidth product , input and output impedances.
Given: Q point (VCEQ, ICQ)=( 6V,4mA), 𝝱=100, VBE= 0.7V, fL3dB= 100 Hz

Theory

The RC Coupled BJT amplifier is also named common- emitter amplifier because the emitter
of the transistor is common to both the input circuit and output circuit. The input signal is
applied across the ground and the base circuit of the transistor. The output signal appears
across ground and the collector of the transistor. Since the emitter is connected to the ground,
it is common to signals, input and output.

The common- emitter circuit is the most widely used of junction, transistor amplifiers. As
compared with the common- base connection, it has higher input impedance and lower output
impedance. A single power supply is easily used for biasing. In addition, higher voltage and
power gains are usually obtained for common- emitter (CE) operation.

Current gain in the common emitter circuit is obtained from the base and the collector circuit
currents. Because a very small change in base current produces a large change in collector
current, the current gain (β) is always greater than unity for the common-emitter circuit, a
typical value is about 100.

The improved ac power level in the amplifier is the result of a transfer of energy from the
applied dc supplies. The analysis and design of a transistor requires a knowledge of both the
dc and ac response of the system. But, the superposition theorem is applicable, and the
analysis of dc conditions can be totally separated from ac response. However, during design
or synthesis stage the choice of parameters for the required dc levels will affect the ac
response and vice versa

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CIRCUIT DIAGRAM

Design Approach
VCE= ; ( 50% of VCC)

VE= ; (10% of VCC)

DESIGN:
Given VCE = 6V, IC = 4mA,  = 100.
For good biasing VCE=

Therefore VCC= 6x2

VCC=12V
VE= = = 1.2V

VE= 1.2V; IE  IC = 4 mA
To find RE:
From the fig. We see that,
RE =

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RE = 1.2 / (4 x 10-3 ) = 300

Choose Standard RE = 330
To find RC:
Voltage drop across RC is given by applying KVL to output loop
ICRC =VCC -VCE -VE
(4 x 10-3 )RC =12 – 6 -1.2
RC=(4.8V)/(4mA)
Therefore RC = 1.2k
To find VC and IC
VC=VCC - ICRC
= 12V- 4.8V
VC=7.2V
IC=  IB
4mA = (100)IB
IB=40𝛍A

To find biasing resistors R1 & R2:

VB = VBE+ VE
= 0.7 + 1.2
VB = 1.9V
Assume 10 IB Current flows through R1 , IB will flow through the base and 9IB will flow
through R2.

W.K.T. IC = IB
4 x 10-3 = 100 IB
Therefore IB = 40 A

From the fig. we see that,

R1 = (VCC – VB )/ 10 IB

= (12 – 1.9) / (10 x 40 x 10-6 )

R1 = 25.25k

Choose Standard R1  22k+3.3K

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R2 = VB / 9IB
= 1.9 / (9 x 40 x 10-6 )

R2= 5.28k

Choose Standard R2  4.7k+470

To choose CE (Bypass Capacitor)

 The Bypass Capacitor provides a low impedance path for AC signal. Thereby, solving
the conflicting bias and gain issues of the amplifier.
 For a stable bias- RE must be large
 For high gain- RE must be small because for good gain the magnitude of (RC/RE)
must be large
Therefore, XCE should be 10 times lower than RE (Design Approach)
Where, XCE – Capacitive reactance of bypass capacitor

Let XCE = RE/10

W.K.T fL3dB = 100Hz and RE = 330
XCE = 330/10
XCE = 33

XCE =

CE = 1 / 2 (100)(33)
= 48F
Choose Standard CE  47F.
To find Input and Output Impedance (Zin & Zout)
Zin= R1|| R2|| 𝝱re
Zout= RC
Where, re= 26mV/IE
= 26mV/4mA
re=6.5
Zin= 22K || 4.7K ||6.5
Zin=556
Zout= 1.2K

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To choose the coupling capacitors CB and CC

Input Coupling Capacitor CB=

Where, Zin is the input impedance

CB=1/(2𝝅x100x556)
=2.86𝛍F
Choose Standard CB= 2.2𝛍F

Output Coupling Capacitor CC=

CC= 1/(2𝝅x100x1.2K)
CC= 1.326𝛍F
Choose Standard CC=1𝛍F

Circuit Diagram with Design values

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Circuit diagram with current and voltages levels

PROCEDURE:
1) To measure Q point:
Connect the circuit without Vi and capacitors. Set Vcc= 12V. Measure dc voltages at the
base VB, collector Vc and VE with respect to ground using Multimeter
Determine VCE = VC – VE = --------- V
IC = (VCC-VC)/RC = -------- mA
Q point is Q(VCE,IC)
To check biasing conditions:
With VCC=12V; VCE should be VCC/2 = 6V
VE should be VCC/10 = 1.2V
VBE = 0.7V
2) Connect the circuit as per the circuit diagram
3) Feed a sine wave of peak to peak amplitude about Vi=40mVp-p from signal generator.
4) Vary the input sine wave frequency from 10Hz to 1MHz in steps and measure the
output voltage VO of the amplifier. Verify that the input voltage Vi should remain
constant throughout the frequency range.
5) Tabulate the results.
6) Plot the graph of frequency f versus gain (dB) and determine the Gain Band-Width
product.

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Procedure to measure input impedance Zin:

Input Impedance is the total resistance looking into the amplifier at input coupling
capacitor. It represents the total resistance presented to the AC source.

2) Connect the circuit as shown in the Figure.

3) Set the following:
DRB to zero.
Input sine wave amplitude of 40mV
Input sine wave frequency to any mid band frequency (10KHz).
4) Measure VO(p-p)
5) Increase DRB till VO(p-p) = VO(p-p)/2 . The corresponding DRB value gives the input
impedance Zin.

Procedure to measure output impedance:

1) Connect the circuit as shown in the Figure.

2) Set the following:
DRB to maximum value.
Input sine wave amplitude to 40mv.
Input sine wave frequency to any mid band frequency(10 KHz)
3) Measure VO(p-p).
4) Decrease DRB till VO = VO(p-p)/2. The corresponding DRB value gives the output
impedance ZOut.

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Expected WAVEFORM:

Simulated Waveform

OBSERVATION
Table 1: D.C. Conditions:

Parameter VC VCE VE VBE VB

Theoretical 4.8 6 1.2 0.7 1.9
Practical
Table 2: Frequency response Vi =__________ mV

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Output Voltage
Freq. (Hz) AV = Vo(p-p) / Vin(p-p). AV (dB) = 20log AV
Vo(p-p) (Volts)

100
.
.
.
1M

Expected FREQUENCY RESPONSE CURVE ( in Semilog )

Bandwidth = f2 – f1

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Simulated Frequency Response for Vi(p-p)=2mV

Zin and Zo:

Parameter Practical
Zin
Zo

Result: The BJT amplifier was designed and rigged up. The parameters were found matching
with the design values.

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EXPERIMENT -3(A)

COLPITTS OSCILLATOR

AIM: Design Colpitts Oscillator for a frequency fo = 100kHz .

COMPONENTSREQUIRED:

Sl. No. Components Details Specification Quantity

1. Transistor SL100 1
2.2µf, 1µf, 47µf, 2.3µf No 1
2. Capacitors No
100pf 2 No
3. Resistors 22k, 4.7k, 1.2k, 330 1 No

4. Inductors 100µH, 1mH, 5mH 1 No

5. Potentiometer 1k 1 No
DC Supply, CRO with Probes, Spring Board / Bread Board

GIVEN: fo = 100 kHz

Avβ > 1
VCC = 12 V
IC = 2mA
β = 50

DESIGN APPROACH: VCE = VCC / 2, VE = VCC / 10, VC = VE+ VCE

THEORY: Oscillators are devices, which generate oscillations. The frequency of

Oscillations depends on the feedback network. Feedback may be of two types namely
positive and negative. In positive feedback, the feedback signal is applied in phase with the
input signal thus increasing it. In negative feedback, the feedback signal is applied out of
phase with the input thus reducing it. The feedback used in oscillators is positive feedback.
The oscillators work on the principle of Barkhausen criteria. This states that for sustained
oscillations
i) Loop gain Av must be equal to1
ii) The phase shift around the loop must be 0ºor 360º
Here Av is the gain of the amplifier and is t h e a t t e n u a t i o n of the feedback
network. Consider the feedback network shown in the figure (1) below

Amplifier

VIN Vo
AV

β
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Assume an amplifier with input signal VIN. The output signal VO will be 180º out of
phase with VIN. So to get an in-phase output, the feedback network provides 180º phase shift.
Therefore the output VF from the feedback network will be in-phase and equal in amplitude
to VIN. Even i f VIN is removed the oscillations continue. Practical oscillations do not need
any input signal to start oscillations. They are self-starting due to thermally produced noise in
resistors and other component. Only one frequency (fo) of noise satisfies, Barkhausen criteria
and the circuit oscillates with that frequency. The Hartley oscillator consists of two inductors
and a capacitor. The Colpitts oscillator consists of two capacitors and an inductor.

FORMULAE:
The resonant frequency fofor Hartley Oscillator is

where Leq = L1+L2

The resonant frequency fo for Colpitts Oscillator is

where

COLPITTS OSCILLATOR

BASIC CIRCUIT DIAGRAM:

VCC

RC
0 R1

C2

C1

SL100

R3 Pot
R2

RE CE

C3 C4

L1

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CIRCUIT DIAGRAM WITH VALUES:

VCC

12V

RC
0 R1 1.2k

22k C2

C1 1uF

SL100
2.2uF
V

R2 0
R3
4.7k

RE 330
CE 47uF

C3 C4

100pF 100pF

L1

0.05066H

SPECIFIC DESIGN:
(a) BJT Amplifier
For design refer BJT amplifier experiment.

(b) Tank circuit for Hartley Oscillator

Given fo= 100 kHz

Where L = L1+L2 [L1<L2]

Let L1 = 100 uH, L2 = 1mH
Therefore C = 2.3 nF

(c) Tank circuit for Colpitts Oscillator

Assume C1 = C2 = 0.01 uF

Where
Therefore L = 0.05066 H

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PROCEDURE:
For both Hartley and Colpitts Oscillator:
1. Rig up the circuit as per the circuit diagram shown.
2. Switch on the power supply and check the D.C conditions.
3. Obtain the output waveform on the CRO and measure the period of
oscillation and calculate the frequency and compare with its theoretical one.

OBSERVATIONS:
Table1. D.C conditions:
Parameter VRC VCE VE VBE VB

Theoretical 4 6 2 0.7 2.7

Practical

EXPECTED WAVEFORM:

Vo

t
T

Therefore frequency fo = 1/T

GENERATED WAVEFORM OF HARTLEY AND COLPITTS OSCILLATOR:

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RESULT:
Designedfrequency fo= 100 kHz
Hartley Oscillator practically fpra = _______ kHz
Colpitts Oscillator practically fpra = _______ kHz

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EXPERIMENT-3(B)
CRYSTAL OSCILLATOR
AIM:
To design and setup Crystal oscillator .
SPECIFIC OBJECTIVE: To observe sinusoidal output waveform of frequency 2MHz.
Given: Q point (VCEQ, ICQ) = ( 6V,4mA), β = 100, VBE= 0.7V, fL3dB= 100 Hz and
fO = 2MHz
Design Approach
VCE= ; ( 50% of VCC)

VE= ; (10% of VCC)

THEORY:
A crystal oscillator is an electronic oscillator circuit that uses the mechanical resonance of a
vibrating crystal of piezoelectric material to create an electrical signal with a very precise
frequency. This frequency is commonly used to keep track of time (as in quartz
wristwatches), to provide a stable clock signal for digital integrated circuits, and to stabilize
frequencies for radio transmitters and receivers. The most common type of piezoelectric
resonator used is the quartz crystal, so oscillator circuits incorporating them became known as
crystal oscillators, but other piezoelectric materials including polycrystalline ceramics are
used in similar circuits.

High-frequency crystals are typically cut in the shape of a simple, rectangular plate. Low-
frequency crystals, such as those used in digital watches, are typically cut in the shape of a
tuning fork. For applications not needing very precise timing, a low-cost ceramic resonator is
often used in place of a quartz crystal.

When a crystal of quartz is properly cut and mounted, it can be made to distort in an electric
field by applying a voltage to an electrode near or on the crystal. This property is known as
electrostriction or inverse piezoelectricity. When the field is removed, the quartz will
generate an electric field as it returns to its previous shape, and this can generate a voltage.
The result is that a quartz crystal behaves like a circuit composed of an inductor, capacitor
and resistor, with a precise resonant frequency.

Quartz has the further advantage that its elastic constants and its size change in such a way
that the frequency dependence on temperature can be very low. The specific characteristics
will depend on the mode of vibration and the angle at which the quartz is cut (relative to its
crystallographic axes). Therefore, the resonant frequency of the plate, which depends on its
size, will not change much, either. This means that a quartz clock, filter or oscillator will
remain accurate. For critical applications the quartz oscillator is mounted in a temperature-
controlled container, called a crystal oven, and can also be mounted on shock absorbers to
prevent perturbation by external mechanical vibrations.

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CIRCUIT DIAGRAM:

DESIGN:

Given VCE = 6V, IC = 4mA,  = 100.

For good biasing VCE=

Therefore VCC= 6x2

VCC=12V
VE= = = 1.2V

VE= 1.2V; IE  IC = 4 mA
To find RE:
From the fig. We see that,
RE =

RE = 1.2 / (4 x 10-3 ) = 300

Choose Standard RE = 330

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To find RC:
Voltage drop across RC is given by applying KVL to output loop
ICRC =VCC -VCE -VE

(4 x 10-3 )RC =12 – 6 -1.2

RC=(4.8V)/(4mA)
Therefore RC = 1.2k
To find VC and IC
VC=VCC - ICRC
= 12V- 4.8V
VC=7.2V
IC=  IB
4mA = (100)IB
IB=40𝛍A

To find biasing resistors R1 & R2:

VB = VBE+ VE

= 0.7 + 1.2
VB = 1.9V
Assume 10 IB Current flows through R1 , IB will flow through the base and 9IB will flow
through R2.

W.K.T. IC = IB
4 x 10-3 = 100 IB
Therefore IB = 40 A

From the fig. we see that,

R1 = (VCC – VB )/ 10 IB

= (12 – 1.9) / (10 x 40 x 10-6 )

R1 = 25.25k

Choose Standard R1  22k+3.3K

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R2 = VB / 9IB

= 1.9 / (9 x 40 x 10-6 )

R2= 5.28k

Choose Standard R2  4.7k+470

To choose CE (Bypass Capacitor)

 The Bypass Capacitor provides a low impedance path for AC signal. Thereby, solving
the conflicting bias and gain issues of the amplifier.
 For a stable bias- RE must be large
 For high gain- RE must be small because for good gain the magnitude of (RC/RE)
must be large
Therefore, XCE should be 10 times lower than RE (Design Approach)
Where, XCE – Capacitive reactance of bypass capacitor

Let XCE = RE/10

W.K.T fL3dB = 100Hz and RE = 330

XCE = 330/10
XCE = 33
XCE =

CE = 1 / 2 (100)(33)
= 48F
Choose Standard CE  47F.

To find Input and Output Impedance (Zin & Zout)

Zin= R1|| R2|| 𝝱re
Zout= RC
Where, re= 26mV/IE
= 26mV/4mA
re=6.5
Zin= 22K || 4.7K ||6.5

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Zin=556
Zout= 1.2K
To choose the coupling capacitors CB and CC
Input Coupling Capacitor CB=

Where, Zin is the input impedance

CB=1/(2𝝅x100x556)
=2.86𝛍F
Choose Standard CB= 2.2𝛍F

Output Coupling Capacitor CC=

CC= 1/(2𝝅x100x1.2K)
CC= 1.326𝛍F
Choose Standard CC=1𝛍F

CIRCUIT DIAGRAM WITH VALUES:

Circuit Diagram with Design values

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Circuit diagram with current and voltages levels

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PROCEDURE:

1. Rig up the circuit as shown in the circuit diagram.

2. Before connecting the feedback network, check the circuit for biasing conditions .
To measure Q point:
Connect the circuit without feedback and capacitors. Set Vcc= 12V. Measure dc
voltages at the base VB, collector Vc and VE with respect to ground using Multimeter
Determine VCE = VC – VE = --------- V
IC = (VCC-VC)/RC = -------- mA
Q point is Q(VCE,IC)
To check biasing conditions:
With VCC=12V; VCE should be VCC/2 = 6V
VE should be VCC/10 = 1.2V
VBE = 0.7V

3. After connecting the feedback network. Check the output.

4. Check for the sinusoidal waveform at output. Note down the frequency of the
output waveform and check for any deviation from the designed value of the
frequency.
5. To get a sinusoidal waveform adjust 1K potentiometer.

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OUTPUT:

RESULT:

Designed frequency = 2MHz

Frequency of crystal oscillator practically =

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EXPERIMENT N0 4(A)
SECOND ORDER ACTIVE LOW PASS FILTER

Aim: To obtain the frequency response of an active low pass filter for the desired cut off
frequency.

Components required:

Resistors- 33KΩ, 10KΩ, 5.86 KΩ

Capacitors 2200pF, opamp –μA 741

Design

For a 2nd order Filter, F H = 1 / 2RC Hz

Let FH = 2 KHz and R = 33 K

 2  10 3 = 1 / 2   33  10 3  C

 C = 2200 pF

The pass band gain of the filter, AF = (1+R f / R1)

For a second order filter, AF = 1.586, Let R1 = 10K

RF = 5.86 k 

Low pass circuit Diagram

R1 Rf

5.8k
10K 7
0 2 V+
-
uA741
R R Vo
3 V-
+
33k 33k
4
0
V1

C
C 2200Pf
2200Pf

0
0

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 31

 Cambridge Institute of Technology North Campus, Bengaluru

Procedure:

1. Before wiring the circuit, check all the components.

2. Design the filter for a gain of 1.586 and make the connections as shown in the circuit
diagram.
3. Set the signal generator amplitude to 10V peak to peak and observe the input voltage
and output voltage on the CRO
4. By varying the frequency of input from Hz range to KHz range, note the frequency and
the corresponding output voltage across pin 6 of the op amp with respect to the gnd.
5. The output voltage (VO) remains constant at lower frequency range.
6. Tabulate the readings in the tabular column.
7. Plot the graph with ‘f ‘on X-axis and gain in dB on Y axis.

RESULT: The frequency response of an active low pass filter for the desired cut off
frequency is designed and roll off factor is calculated.

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 32

 Cambridge Institute of Technology North Campus, Bengaluru

EXPERIMENT N0 4(B)

SECOND ORDER ACTIVE HIGH PASS FILTER

AIM: To obtain the frequency response of an active high pass filter for the desired cut off
frequency.

Components required:

Resistors- 33KΩ, 10KΩ, 5.86 KΩ

Capacitors 2200pF, opamp –μA 741

Design:

For a 2nd order Filter, FL= 1 / 2RC Hz

Let FL = 2 KHz and R = 33 K

 2  10 3 = 1 / 2   33  10 3  C

 C = 2200 pF

The pass band gain of the filter, AF = (1+R f / R1)

For a second order filter, AF = 1.586, Let R1 = 10K

RF = 5.86 k 

High pass circuit Diagram

R1 Rf

5.8k
10K 7
0 2 V+
-
uA741
C C Vo
3 V-
+

2200Pf 2200Pf 4
0
V1 R

R 33k

33k
0

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 33

 Cambridge Institute of Technology North Campus, Bengaluru

Procedure:

1. Before wiring the circuit, check all the components.

2. Design the filter for a gain of 1.586 and make the connections as shown in the circuit
diagram.
3. Set the signal generator amplitude to 10V peak to peak and observe the input voltage
In addition, output voltage on the CRO.
4. By varying the frequency of input from HZ range to KHA range, note the frequency
And the corresponding output voltage across pin 6 of the op amp with respect to the
gnd.
5-.The output voltage (VO) remains constant at lower frequency range.
6. Tabulate the readings in the tabular column.
7. Plot the graph with ‘f ‘on X-axis and gain in dB on Y axis.

RESULT: The frequency response of an active high pass filter for the desired cut off
frequency is designed and roll off factor is calculated.

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 34

 Cambridge Institute of Technology North Campus, Bengaluru

EXPERIMENT NO. 5(A)

ADDER

AIM:
To design adder using Op-Amp

APPARATUS:
Name Description Qty
Op Amp µA741 1

Resistors 1 KΩ 3

DC Power Supply - 3

CIRCUIT DIAGRAM:

DESIGN:

Let
PROCEDURE:
1. Rig up the circuit as shown in figure.
2. Apply input V1=0.5V and V2=0.5V
3. Measure the output using multimeter and compare it with theoretical value

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 35

 Cambridge Institute of Technology North Campus, Bengaluru

RESULT:

Sl no Input V1(V) Input V2(V) Theritical Practical

output(V) output(V)
1 0.5 0.5 1
2 1 1.5 2.5

CONCLUSION:

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 36

 Cambridge Institute of Technology North Campus, Bengaluru

EXPERIMENT NO. 5(B)

INTEGRATOR

AIM:
To design Integrator using Op-Amp

APPARATUS:
Name Description Qty
Op Amp µA741 1
100 KΩ 1
Resistors
10 KΩ 1

Capacitor 0.01 µF 1

AFO - 1
CRO - 1
DC Power Supply - 1

CIRCUIT DIAGRAM:

DESIGN:

For an Integrator, R1C>>T, R1C=10T ,

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 37

 Cambridge Institute of Technology North Campus, Bengaluru

Assume C= 0.01µF and T= 0.1 ms then R1=10kΩ

Gain limiting can be produced by shunting the integrator capacitor with a

resistor This resistor sets the upper limit voltage gain to Amax=
Choose RF= 10 R1 then RF= 100 kΩ
Critical frequency is that frequency above which the circuit act like an integrator and it is
given by flow= .

PROCEDURE:
1. Rig up the circuit as shown in figure.
2. Apply the input Square wave of 0.5 V, 1KHz
3. Observe the output on CRO

EXPECTED WAVEFORMS:

CONCLUSION:

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 38

 Cambridge Institute of Technology North Campus, Bengaluru

Experiment No. 5(c)

DIFFERENTIATOR
AIM:
To design Differentiator using Op-Amp

APPARATUS:
Name Description Qty
Op Amp µA741 1
100 Ω 1
Resistors
5 KΩ 1
0.01 µF 1
Capacitor
1nF 1
AFO - 1
CRO - 1
DC Power Supply - 1

CIRCUIT DIAGRAM:

DESIGN:

For an Differentiator Rf<<T, RfC=10/T

Mr.Sridhar T N, Asst. Prof., Dept. of ECE Page 39

Assume C= 0.01µF and T= 0.5 s then Rf= 5 kΩ
Choose R1=Rf/50, then R1=100Ω
FHIGH=1/2πRfCf, Where FHIGH is the highest frequency for differentiator .
/

Hence choose Cf= 1nF

PROCEDURE:
1. Rig up the circuit as shown in figure.
2. Apply the input Square wave of 0.5 V, 1KHz
3. Observe the output on CRO

EXPECTED WAVEFORMS:

CONCLUSION:
 EXPERIMENT NO. 6

DESIGN AND TEST A SCHMITT TRIGGER CIRCUIT FOR THE GIVEN

VALUES OF UTP AND LTP

AIM:
Test a comparator circuit and design a Schmitt trigger for the given UTP and LTP values
and obtain the hysteresis.

COMPONENTS REQUIRED:
Op-Amp - A741 – 1
Resistors – 1k - 1, 2.2k - 1

THEORY:
Schmitt Trigger is also known as Regenerative Comparator. This is a square wave generator
which generate a square based on the positive feedback applied. As shown in the fig. below, the
feedback voltage is Va. The input voltage is applied to the inverting terminal and the feedback
voltage is applied to the non-inverting terminal. In this circuit the op-amp acts as a comparator. It
compares the potentials at two input terminals. Here the output shifts between
+ Vsat and –Vsat. When the input voltage is greater than Va, the output shifts to – Vsat and when the
input voltage is less than Va, the output shifts to + Vsat. Such a comparator circuit exhibits a curve
known as Hysterisis curve which is a plot of Vin vs V0. The input voltage at which the output
changes from + Vsat to – Vsat is called Upper Threshold Point (UTP) and the input voltage at which
the output shifts from – Vsat to + Vsat is called Lower Threshold Point (LTP). The feedback voltage
Va depends on the output voltage as well as the reference voltage.
A Zero Cross Detector is also a comparator where op-amp compares the input voltage with
the ground level. The output is a square wave and inverted form of the input.

CIRCUIT DIAGRAM:

Schmitt Trigger
+ Vcc
U1
7
1

3
+ 6 Vo
2
-
UA741 R1
4
5

2.2k
Vin - Vcc

R2
1k

+ Vref

Zero Cross Detector

+ Vcc
U2
7
1

3
+ 6 Vo
2
-
UA741
Vin
4
5

- Vcc
DESIGN:

Given UTP = + 4V and LTP = - 2V

Let I1 be the current through R1 and I2 be the current through R2.
W.K.T the current into the input terminal of an op-amp is zero.
 I1 + I2 = 0
I1 = ( V0 – Va ) / R1
I2 = ( Vref – Va ) / R2
 ( V0 – Va ) / R1 + ( Vref – Va ) / R2 = 0
 Va = ( V0 R2 + Vref R1 ) / ( R1 + R2 )
When V0 = + Vsat, Va = UTP
When V0 = - Vsat, Va = LTP
 [ ( Vsat R2 ) / ( R1 + R2) ] + [ ( Vref R1 ) / ( R1 + R2 ) ] = UTP ------- (1)
 [ ( - Vsat R2 ) / ( R1 + R2 ) ] + [ ( Vref R1 / (R1 + R2 ) ] = LTP -------(2)
(1) – (2) 
( 2 Vsat R2 ) / ( R1 + R2 ) = UTP – LTP = 6V
Simplifying this equation we get,
7 R2 = 3 R1
Assume R2 = 1k
 R1 = 2.2k
(1) + (2)
( 2 Vref R1 ) / ( R1 + R2 ) = UTP + LTP = 2V
Simplifying the above equation, we get
Vref = 1.4V

PROCEDURE:

1. Rig up the connections as shown in the circuit diagram.

2. Give a sinusoidal input of 10V peak to peak and 500 Hz from a signal generator.
3. Check the output at pin no. 6 (square wave).
4. Coincide the point where the output shifts from + Vsat to – Vsat with any point on the
input wave.
5. Measure the input voltage at this point. This voltage is UTP.
6. Coincide the point where the output shifts from – Vsat to + Vsat with any point on the
input wave.
7. Measure the input voltage at this point. This voltage is LTP.
8. Another method of measuring UTP and LTP is using the Hysterisis Curve.
9. To plot the hysterisis curve give channel 1 of CRO to the output and channel 2 of CRO
to the input.
10. Press the XY knob. Adjust the grounds of both the knobs.
11. Measure UTP and LTP as shown in the fig. and check whether it matches with the
designed values.
WAVEFORMS:

Vin
5
4
0 t
-2
-5
Schmitt Trigger
V0

10
0 t

- 10
Zero Cross Detector
V0
10

0 t
- 10

HYSTERISIS CURVE:
V0
+ Vsat
Vin
LTP UTP
- Vsat

RESULT: Thus a square wave generator for given UTP and LTP is designed and generated.
 EXPERIMENT N0 7

R-2R DAC USING OP-AMP

AIM:
Design 4 bit R – 2R Op-Amp Digital to Analog Converter
(i) using 4 bit binary input from toggle switches and
(ii) by generating digital inputs using mod-16 counter.

COMPONENTS REQUIRED:
Op-amp - A741
Resistors – 10k - 4
22k - 6
Dual power supply, Multimeter, bread board, connecting wires.

THEORY:
Nowadays digital systems are used in many applications because of their increasingly
efficient, reliable and economical operation. Since digital systems such as microcomputers use a
binary system of ones and zeros, the data to be put into the microcomputer have to be converted
from analog form to digital form. The circuit that performs this conversion and reverse conversion
are called A/D and D/A converters respectively.
D/A converter in its simplest form uses an op-amp and resistors either in the binary
weighted form or R-2R form.
The fig. below shows D/A converter with resistors connected in R-2R form. It is so called as
the resistors used here are R and 2R. The binary inputs are simulated by switches b 0 to b3 and the
output is proportional to the binary inputs. Binary inputs are either in high (+5V) or low (0V) state.
The analysis can be carried out with the help of Thevenin’s theorem. The output voltage
corresponding to all possible combinations of binary inputs can be calculated as below.
V0 = - RF [ (b3/2R) + (b2/4R) + (b1/8R) + (b0/16R) ]
Where each inputs b3, b2, b1 and b0 may be high (+5V) or low (0V).
The great advantage of D/A converter of R-2R type is that it requires only two sets of
precision resistance values. In weighted resistor type more resistors are required and the circuit is
complex. As the number of binary inputs is increased beyond 4 even D/A converter circuits get
complex and their accuracy degenerates. Therefore in critical applications IC D/A converter is used.
Some of the parameters must be known with reference to converters. They re resolution,
linearity error, settling time etc.

Resolution = 5V / 28 = 5 / 256 = 0.0195

WAVEFORMS:
R- 2R LADDER NETWORK RF = 2R
1 2

+vcc U1
7 5
UA741
2 -
6
2R R R R
3 + Vo
0
-vcc
2R 2R 2R 2R 4 1

LSB MSB
b0 b1 b2 b3
0

Vref

0
DESIGN:
The equation for output voltage is given by
V0 = - RF [ (b3/2R) + (b2/4R) + (b1/8R) + (b0/16R) ]
V0 = - RF . Vref[ (b3/2R) + (b2/4R) + (b1/8R) + (b0/16R) ]
Case (i) If b0 b1 b2 b3 = 1 0 0 0 for 0.5 volts change in output for LSB change
- 0.5 = - 20 x 103.Vref [ (1 / (16 x 1.103)) + 0 + 0 + 0)
Vref = 4V
Case (ii) If Vref = 5V and b0 b1 b2 b3 = 0 1 0 0, then
V0 = - 20.103 . 5 [ (0 + (1/ (8.1.103)) + 0 + 0) ]
V0 = - 1.25V

TABULAR COLUMN:

Inputs Output voltage

b3 b2 b1 b0 Theoretical Practical

0 0 0 0
.
.
.
.
.
1 1 1 1

PROCEDURE:
1. Test the op-amp and other components before rigging up the circuit.
2. Rig up the circuit as shown in the fig.
3. Apply different combination of binary inputs using switches.
4. Observe the output at pin no. 6 of op-amp using multimeter or CRO.
5. Tabulate the readings as shown.
6. Calculate the resolution of the converter.

RESULT: For digital BCD inputs ,the analog output has been verified and resolution is obtained.
 EXPERIMENT N0 8 (A)
ASTABLE MULTIVIBRATOR
AIM:
To design and verify the operation of astable multivibrator using 555 Timer for given
frequency and duty cycle.

APPARATUS REQUIRED:
Timer - 555
Resistors – 10k - 1
4.5k - 2
7.25k- 1
Capacitors – 0.01F-1
0.1F-1
Signal Generator, DC power supply, CRO and connecting wires

THEORY:
A 555 timer is a monolithic timing circuit that can produce accurate and highly stable time
delays or oscillations, some of the applications of 555 are square wave generator, astable and
monostable multivibrator.
Astable multivibrator is a free running oscillator has two quasi stable state in one state o/p voltage
remains low for a time interval of Toff and then switches over to other state in which the o/p
remains high for an interval of Ton the time interval Ton and Toff are determined by the external
resistors a capacitor and it does not require an external trigger, when the power is switched on the
timing capacitor begins to charge towards 2/3 Vcc through R A & RB, when the capacitor voltage
has reached this value, the upper comparator of the timer triggers the flip flop in it and the
capacitor begins to discharge through RB when the capacitor voltage reaches 1/3 Vcc the lower
comparator is triggered and another cycle begins, the charging and discharging cycle repeats
between 2/3 Vcc and 1/3Vcc for the charging and discharging periods t1and t2 respectively. Since
the capacitor charges through RA and RB and discharges through RB only the charge and discharge
are not equal as a consequence the output is not a symmetrical square wave and the multivibrator is
called an asymmetric astable multivibrator

CIRCUIT DIAGRAM:

SYMMETRIC MULTIVIBRATOIR
Vcc+5V

8 4
Ra
VC RE
C SE
T
7
DISCHARGE
Rb
O/P
D1 3
D2 OUTPUT
555D

6
THRESHOLD
CO
2 NT
TRIGGER GN RO
D L
C1
1 5
C2

0
ASSYMETRIC MULTIVIBRATOR

Vcc +5V
RA

4
RESET
VCC
7
DISCHARGE

RB
555 OUTPUT
3 CRO
6
THRESHOLD

CONTROL
2
TRIGGER GND

C
1

5
0.01uf

DESIGN: 0

ASSYMETRIC: Given f = 1khz

Duty cycle = 60%

T = 0.693(Ra + 2Rb) C
F = 1.45/ [(Ra + 2Rb) C]
Duty cycle = (Ra + Rb)/Ra + 2Rb)
1K = 1.45/ [(Ra + 2Rb) 0.1*10-6]
Ra + 2Rb = 14.5K
Ra + Rb = 8.7K
Assume Ra = 4.7K
Rb = 9.57K  10K
SYMETRIC Given f = 1khz
Duty cycle = 50%

Charging time = Discharging time

T = TON =TOFF

T = 0.693(Ra + Rb) C
F = 1.45/ [(Ra + Rb) C]
Duty cycle = (Ra + Rb)/Ra + Rb)
1K = 1.45/ [(Ra + Rb) 0.1*10-6]
Ra + 2Rb = 14.5K
Since the duty cycle is 50%, Ra = Rb

2Ra = 14.5K
Ra = 7.25K  6.8K
Rb = 7.25K  6.8K
 PROCEDURE:

1. Connections are made as shown in the circuit diagram

2. Switch on the DC power supply unit

3. Observe the wave form on CRO at pin 3 and measure the o/p pulse amplitude

4. Observe the wave form on CRO at pin 6 and measure Vcmax and Vc min

5. Verify that Vcmax=2/3Vcc and Vc min=1/3 Vcc

6. Calculate the duty cycle D, o/p frequency and verify with specified value

TABULAR COLUMN
F(theo) =
Ra Rb C Ton Toff T F DY
1.45/(Ra + Rb)

WAVEFORMS:

Upper threshold
Vc at pin 6 voltage
=2/3*Vcc Lower
2/3VCC threshold

Voltage
1/3VCC
=Vcc/3
0V t

Vout 5V
at pin 3
Toff
0V
t
Ton

RESULT: Thus the operation of astable multivibrator using 555 Timer for given frequency and
duty cycle is designed and verified.
 EXPERIMENT N0 8 (B)

MONOSTABLE MULTIVIBRATOR
AIM:
To design and verify the operation of monostable multivibrator using 555 Timer for given
Pulse width.

APPARATUS REQUIRED:
Timer - 555
Resistors – 10k - 1
Capacitors – 0.01F-1
0.1F-1
Signal Generator, DC power supply, CRO and connecting wires

THEORY:

Monostable multivibrator has a stable state and a quasi stable state, the output of it is normally
low and it corresponds to reset of the flip flop in the timer, on the application of external negative
trigger pulse at pin 2 the circuit is triggered and the flip flop in the timer is set which in turn
releases the short across C and pushes the output high, At the same time the voltage across C rises
exponentially with the time constant RAC and remains in this state for a period RAC even if it is
triggered again during this interval, When the voltage across the capacitor reaches 2/3 Vcc, the
threshold comparator resets the flip flop in the timer which discharges C and the output is driven
low the circuit will remain in this state until the application of the next trigger pulse

CIRCUIT DIAGRAM
Vcc +5V
8

BY127 Rt RA
RESET
VCC

2 6
TRIGGER THRESHOLD
Input Ct
7
DISCHARGE
555
C
CONTROL

CRO 3
OUTPUT 0
GND
1

0.01uf

0
DESIGN:
Given Tp = 1ms
F = 1KHz

T = 1.1R C
Let C = 0.1uF
 R = (1*10-3 ) / (1.1*0.1*10-6 )
R = 9.09 K  10K

PROCEDURE:

1. Rig up the circuit as shown in the figure after checking all the components.
2. Apply suitable inputs to the astable multivibrator (DC & Trigger inputs)
3. Observe the waveform across the timing capacitor in one channel and the output in the other
channel..
4. Verify the designed values and the repeat the above procedure for different set of values.

TABULAR COLUMN

R C Tp = 1.1RC Tp(prac)

WAVEFORMS:

Input trigger pulses

Vcc

T
t
Trigger pulses at pin 2

t
Capacitor voltage Vc at pin 5

Upper
threshold
voltage t
Output pulse at pin 3 2/3*Vcc

Tp t

RESULT: Thus the operation of monostable multivibrator using 555 Timer for given
pulse width is designed and verified.
 EXPERIMENT-09(A)
RC PHASE SHIFT OSCILLATOR

AIM:
To design and set up an RC phase shift oscillator using BJT.

SPECIFIC OBJECTIVE: To observe sinusoidal output waveform of frequency 7 KHz.

Given: Q point (VCEQ, ICQ)=( 6V,4mA), β=100, VBE= 0.7V, fL3dB= 100 Hz and
fO = 7 KHz
Design Approach
VCE= ; ( 50% of VCC)

VE= ; (10% of VCC)

THEORY:
A phase-shift oscillator is a linear electronic oscillator circuit that produces a sine wave output. It
consists of an inverting amplifier element such as a transistor or op amp with its output fed back to its input
through a phase-shift network consisting of resistors and capacitors.

A single stage amplifier will produce 180o of phase shift between its output and input signals when
connected in a class-A type configuration. For an oscillator to sustain oscillations indefinitely, sufficient
feedback of the correct phase, i.e "Positive Feedback" must be provided with the amplifier being used as one
inverting stage to achieve this. In a RC Oscillator the input is shifted 180o through the amplifier stage and
180o again through a three section-RC Network (Each RC providing 60o phase shift) giving us "180o + 180o
= 360o" of phase shift which is the same as 0o thereby giving us the required positive feedback. In other
words, the phase shift of the feedback loop should be "0".

Barkhausen's criterion applies to linear circuits with a feedback loop. It states that if A is the gain of the
amplifying element in the circuit and β(jω) is the transfer function of the feedback path, so βA is the loop
gain around the feedback loop of the circuit, the circuit will sustain steady-state oscillations only at
frequencies for which:

1. The loop gain is equal to unity in absolute magnitude, that is,

2. The phase shift around the loop is zero or an integer multiple of 2π:

In a Resistance capacitance Oscillator or simply an RC oscillator, we make use of the fact that a
phase shift occurs between the input and output of a RC network. By using RC elements of appropriate
values, a 180o phase shift can be introduced in the feedback branch of an amplifier.

RC Phase-Shift Network
 The circuit on the left shows a single resistor-capacitor network and whose output voltage
"leads" the input voltage by some angle less than 90o. An ideal RC circuit would produce a phase shift of
exactly 90o. The amount of actual phase shift in the circuit depends upon the values of the resistor and the
capacitor, and the chosen frequency of oscillations with the phase angle ( Φ ) being given as:

Phase Angle

In our simple example above, the values of R and C have been chosen so that at the required
frequency the output voltage leads the input voltage by an angle of about 60 o. Then the phase angle between
each successive RC section increases by another 60o giving a phase difference between the input and output
of 180o (3 x 60o).

Then by connecting together three such RC networks in series we can produce a total phase shift in
the circuit of 180o at the chosen frequency and this forms the basis of a "phase shift oscillator" otherwise
known as a RC Oscillator circuit.

If all the resistors, R and the capacitors, C in the phase shift network are equal in value, then the
frequency of oscillations produced by the RC oscillator is given as:

f= 1/2ϖRC√2N where N = 3,

f= 1/2ϖRC√6
  Where:
 ƒ is the Output Frequency in Hertz
 R is the Resistance in Ohms
 C is the Capacitance in Farads
 N is the number of RC stages. (in our example N = 3)

CIRCUIT DIAGRAM:

DESIGN:
Given VCE = 6V, IC = 4mA,  = 100.

For good biasing VCE=

Therefore VCC= 6x2

VCC=12V
VE= = = 1.2V

VE= 1.2V; IE  IC = 4 mA
To find RE:
From the fig. We see that,
RE =

RE = 1.2 / (4 x 10-3 ) = 300

Choose Standard RE = 330
To find RC:
Voltage drop across RC is given by applying KVL to output loop
ICRC =VCC -VCE -VE

(4 x 10-3 )RC =12 – 6 -1.2

RC=(4.8V)/(4mA)
Therefore RC = 1.2k
To find VC and IC
VC=VCC - ICRC
= 12V- 4.8V
VC=7.2V
IC=  IB
4mA = (100)IB
IB=40𝛍A

To find biasing resistors R1 & R2:

VB = VBE+ VE
= 0.7 + 1.2
VB = 1.9V

Assume 10 IB Current flows through R1 , IB will flow through the base and 9IB will flow through R2.

W.K.T. IC = IB
4 x 10-3 = 100 IB
Therefore IB = 40 A

From the fig. we see that,

R1 = (VCC – VB )/ 10 IB

= (12 – 1.9) / (10 x 40 x 10-6 )

R1 = 25.25k

Choose Standard R1  22k+3.3K

R2 = VB / 9IB

= 1.9 / (9 x 40 x 10-6 )

R2= 5.28k

Choose Standard R2  4.7k+470

To choose CE (Bypass Capacitor)

 The Bypass Capacitor provides a low impedance path for AC signal. Thereby, solving the
conflicting bias and gain issues of the amplifier.
 For a stable bias- RE must be large
 For high gain- RE must be small because for good gain the magnitude of (RC/RE)
must be large
Therefore, XCE should be 10 times lower than RE (Design Approach)
Where, XCE – Capacitive reactance of bypass capacitor

Let XCE = RE/10

W.K.T fL3dB = 100Hz and RE = 330
XCE = 330/10

XCE = 33
XCE =

CE = 1 / 2 (100)(33) = 48F

Choose Standard CE  47F.

To find Input and Output Impedance (Zin & Zout)
Zin= R1|| R2|| 𝝱re
Zout= RC
Where, re= 26mV/IE
= 26mV/4mA
re=6.5
Zin= 22K || 4.7K ||6.5
Zin=556
Zout= 1.2K

To choose the coupling capacitors CB and CC

Input Coupling Capacitor CB=

Where, Zin is the input impedance

 CB=1/(2𝝅x100x556)
=2.86𝛍F
Choose Standard CB= 2.2𝛍F

Output Coupling Capacitor CC=

CC= 1/(2𝝅x100x1.2K)
CC= 1.326𝛍F
Choose Standard CC=1𝛍F
DESIGN OF TANK CIRCUIT:
We know that f0= 1/2πRC√6
Given fO = 7 KHz
Assume C=0.02 µF
R = 1/2πf0C√6 = 527 Ω  470 Ω

Circuit Diagram with values:

0 DC = 12V

V1

R1 R3
22K 1.2K

C4 C5 C6

0.02UF 0.02UF 0.02UF

C1
R5 R6 R7

2.2Uf SL100 470 470 470

2
0

R9
1k
1

R2
R4 C3
4.7K 330 47UF

Circuit Diagram with Design values

 0V 2.148mA
0 DC = 12V

V1

12.00V

451.2uA R1 R3 1.697mA
22K 1.2K

0V

C4 C5 C6

1.697mA
0.02UF 0.02UF 0.02UF
9.964V
C1 0A
R5 R6 R7

2.2Uf 9.977uA SL100 470 470 470

-1.707mA 0V 0A
0A
1.707mA 2
1.417V 0
2.074V
R9
1k
1

563.2mV

441.2uA
R2 1.707mA
R4 C3

0V 4.7K 330 47UF

0V
0

Circuit diagram with current and voltage levels

PROCEDURE:
7) To measure Q point:
Connect the circuit without feedback and capacitors. Set Vcc= 12V. Measure dc voltages at the base
VB, collector Vc and VE with respect to ground using Multimeter
Determine VCE = VC – VE = --------- V
IC = (VCC-VC)/RC = -------- mA
Q point is Q(VCE,IC)
To check biasing conditions:
With VCC=12V; VCE should be VCC/2 = 6V
VE should be VCC/10 = 1.2V
VBE = 0.7V
8) Connect the circuit as per the circuit diagram.
9) Adjust the 1k potentiometer to get sinusoidal waveform at the output.

10) To measure the phase shift

a] Connect channel 1 to point D and channel 2 to point A.

Press the XY knob and measure the phase shift.
θ = sin-1 (a/b) ( approx.= 60o )

b] Connect channel 2 to point B the graph is as shown

θ = sin-1 (a/b) , phase angle = 1800 – θ

( approx.= 1200 )
C] Connect channel 2 to point C

The transfer function will be almost a straight line and θ = 00 and therefore

phase angle =1800 - 00 = 1800

OUTPUT:
Result:
Designed frequency = 7KHz

Frequency of crystal oscillator practically =

APPLICATIONS:
a) musical instruments
b) oscillators
c) voice synthesis
d) GPS units.

Viva Questions
1) What is an Oscillator? Classify them.
A) An electronic oscillator is an electronic circuit that produces a periodic, oscillating electronic signal,
often a sine wave or a square wave. Oscillators convert direct current (DC) from a power supply to
an alternating current signal.

2) What are The Blocks, which forms an Oscillator circuits?

A) Amplifer and feedback network
3) What are damped & Un-damped Oscillations?
A) Damping is an influence within or upon an oscillatory system that has the effect of reducing,
restricting or preventing its oscillations.
Undamped oscillations are sustained oscillations.
4) What is Barkhausen's criteria?
A) For sustained oscillations
i. The total phase shift around a loop is precisely 0 degree or 360 degree.
ii. The magnitude of the product of open loop gain of the amplifier and the magnitude of the
feedback factor is unity.
That is │Aβ│=1
5) Why RC tank Circuit Oscillator is used for AF range?
A) In an RC oscillator circuit, the filter is a network of resistors and capacitors. RC oscillators are
mostly used to generate lower frequencies, for example in the audio range
 6) What type of feedback is used in Oscillator circuit?
A) Positive feedback.

Exercise Questions
1) Design an oscillator for 10 kHz and verify the frequency of oscillations and Barkhausen conditions.
2) Design an oscillator for 8 kHz and verify the frequency of oscillations and Barkhausen conditions.
3) Design aRC phase shift oscillator for 7 kHz and measure the oscillating frequency.Verify the phase shift
conditions also.
4) Design an oscillator of 9 kHz whose feedback network includes RC networks and verify the oscillating
frequency. Verify the phase shift conditions also.
5) Design a RC phase shift oscillator for 10 kHz. Verify frequency of oscillations the phase shift conditions.
 EXPERIMENT- 9(B)

HARTLEY OSCILLATOR

AIM: Design a BJT Hartley Oscillator for a frequency fo = 100kHz and test their performance.

COMPONENTSREQUIRED:

Sl. No. Components Details Specification Quantity

1. Transistor SL100 1 No
2.2µf, 1µf, 47µf, 2.3µf 1 No
2. Capacitors 100pf 2 No
3. Resistors 22k, 4.7k, 1.2k, 330 1 No

4. Inductors 100µH, 1mH, 5mH 1 No

5. Potentiometer 1k 1 No
DC Supply, CRO with Probes, Spring Board / Bread Board

GIVEN: fo = 100 kHz

Avβ > 1
VCC = 12 V
IC = 2mA
β = 50

DESIGN APPROACH: VCE = VCC / 2, VE = VCC / 10, VC = VE+ VCE

THEORY: Oscillators are devices, which generate oscillations. The frequency of Oscillations
depends on the feedback network. Feedback may be of two types namely positive and negative. In
positive feedback, the feedback signal is applied in phase with the input signal thus increasing it. In
negative feedback, the feedback signal is applied out of phase with the input thus reducing it. The
feedback used in oscillators is positive feedback. The oscillators work on the principle of
Barkhausen criteria. This states that for sustained oscillations

iii) Loop gain Av must be equal to1

iv) The phase shift around the loop must be 0ºor 360º

Here Av is the gain of the amplifier and is t h e a t t e n u a t i o n of the feedback network.

Consider the feedback network shown in the figure (1) below
 Amplifier

VIN Vo
AV

β
Vf

Figure 1

Assume an amplifier with input signal VIN. The output signal VO will be 180º out of phase
with VIN. So to get an in-phase output, the feedback network provides 180º phase shift. Therefore
the output VF from the feedback network will be in-phase and equal in amplitude to VIN. Even i f
VIN is removed the oscillations continue. Practical oscillations do not need any input signal to start
oscillations. They are self-starting due to thermally produced noise in resistors and other
component. Only one frequency (fo) of noise satisfies, Barkhausen criteria and the circuit oscillates
with that frequency. The Hartley oscillator consists of two inductors and a capacitor. The Colpitts
oscillator consists of two capacitors and an inductor.

FORMULAE:
The resonant frequency fofor Hartley Oscillator is

Where Leq = L1+L2

The resonant frequency fo for Colpitts Oscillator is

Where
HARTLEY OSCILLATOR
BASIC CIRCUIT DIAGRAM:
VCC

RC
0 R1

C2

C1

SL100

R3 Pot
R2

RE CE

L1 L2

C3

CIRCUIT DIAGRAM WITH VALUES:

VCC

12V

RC
0 R1 1.2k

22k C2

C1 1uF

SL100
2.2uF

R2 0
R3
4.7k

RE 330
CE 47uF

L1 L2

1mH 1mH
C3

2.3uF
CIRCUIT DIAGRAM WITH VOLTAGE VALUES:
VCC

12V
12.00V

RC
0 R1 1.2k

22k C2

C1 1uF
7.145V
SL100
2.2uF 2.024V

V
1.343V

R2 0
R3
4.7k 1.343V

0V 0V
RE 330
CE 47uF

0
0V
L1 L2

1mH 1mH
C3

2.3uF

CIRCUIT DIAGRAM WITH CURRENT VALUES:

VCC

12V
4.046mA
453.5uA
4.500mA RC
0 R1 1.2k

22k 4.046mA C2

C1 1uF

SL100
2.2uF 22.92uA

V
430.6uA -4.069mA 4.069mA

R2 0
R3
4.7k

4.069mA

RE 330
CE 47uF

0
0A 0A
L1 L2

1mH 1mH
C3

2.3uF
SPECIFIC DESIGN:
(a) BJT Amplifier
For design refer BJT amplifier experiment.

(b) Tank circuit for Hartley Oscillator

Given fo= 100 kHz

Where L = L1+L2 [L1<L2]

Let L1 = 100 uH, L2 = 1mH
Therefore C = 2.3 nF

PROCEDURE:
For both Hartley Oscillator:
4. Rig up the circuit as per the circuit diagram shown.
5. Switch on the power supply and check the D.C conditions.
6. Obtain the output waveform on the CRO and measure the period of oscillation and calculate
the frequency and compare with its theoretical one.

OBSERVATIONS:
Table1. D.C conditions:
Parameter VRC VCE VE VBE VB

Theoretical 4 6 2 0.7 2.7

Practical
EXPECTED WAVEFORM:

Vo

t
T

Therefore frequency fo = 1/T

GENERATED WAVEFORM OF HARTLEY OSCILLATOR:

RESULT:
Designedfrequency fo= 100 kHz
Hartley Oscillator practically fpra = _______ kHz
 EXPERIMENT N0 10(A)

NARROW BAND PASS FILTER

Aim: To obtain the frequency response of an active band pass filter for the desired cut off
frequency and to verify the roll off.

Components required:

Resistors- 33KΩ, 10KΩ, 5.86 KΩ

Capacitors 2200pF, opamp –μA 741
Design:

For a 2nd order Filter, F= 1 / 2RC Hz

(i) For High pass section

Let FL = 2 KHz and R = 33 K

 2  10 3 = 1 / 2   33  10 3  C

 C = 2200 pF

(ii) For low pass section

Let FH = 10 KHz And R = 33 k

 10  10 3 = 1 / 2   33  10 3  C

 C’ = 470 pF

The pass band gain of the filter, AF = (1+R f / R1)

For a second order filter, AF = 1.586, Let R1 = 10K

RF = 5.86 k 

The Center frequency FC =  FH  FL

Hence fC = 4.5 KHz

Circuit Diagram:-

BAND PASS FILTER

R1 Rf R1 Rf

5.8k 7 5.8k
10k 10k
7 2 V+
-
2 V+ uA741 6
-
0 uA741 6 0 3 Vo
+ V-
3 V- R R
+ 4
C
C C' C'
V1 4 0
0V R R
0
0 0

Procedure:

1. Before wiring the circuit, check all the components.

2. Design the two filters for the desired cut off frequencies and make the connections as shown
in the circuit diagram.
3. Set the signal generator amplitude to 10V peak to peak and observe the input voltage
And output voltage on the CRO.
4. By varying the frequency of input from Hz range to KHz range, note the frequency
And the corresponding output voltage across pin 6 of the op amp with respect to the
gnd.
5-.The output voltage (VO) remains constant at lower frequency range.
6. Tabulate the readings in the tabular column.
7. Plot the graph with ‘f ‘on X-axis and gain in dB on Y axis.

Result: The frequency response of an active band pass filter for the desired cut off frequency is
designed and roll off factor is calculated.
 EXPERIMENT N0 10(B)
NARROW BAND REJECT FILTER
Aim: To obtain the frequency response of an active band reject filter for the desired cut off
frequency and to verify the roll off.

Components required:

Resistors- 33KΩ, 10KΩ, 5.86 KΩ

Capacitors 2200pF , opamp –μA 741
Design:

For a 2nd order Filter, F= 1 / 2RC Hz

(ii) For High pass section

Let FL = 10 KHz and C = 0.01 F, F L = 1 / 2RC Hz

 10  10 3 = 1 / 2   R  0.01  10 -6

 R = 1.59 k 

(ii) For low pass section

Let FH = 2 KHz And R = 33 k 

 2  10 3 = 1 / 2   33  10 3  C

 C = 2200 pF

The pass band gain of the filter, AF = (1+R f / R1)

For a second order filter, AF = 1.586, Let R1 = 10K 

RF = 5.86 k 
Circuit Diagram:-
BAND REJECT FILTER
R1
Rf

10k 5.8K

7
0 SUMMER
2

V+
- R2 = 10k R4 = 10k
HIGH PASS uA741 6
C C
SECTION 3

V-

7
+
0.01uF 0.01uF 2

V+
-

4
uA741 6
R R
3

V-
+

R5 = 3.3K
0

4
R1
0
10k Rf = 5.8K
7

0
2
V+

-
LOW PASS SECTION R3 = 10k
uA741 6
R' R'
3
V-

+
4

C' C'

Procedure:

1. Before wiring the circuit, check all the components.

2. Design the two filters for the desired cut off frequencies and make the connections as shown
in the circuit diagram.
3. To simplify the design, set R2=R3=R and C2=C3=C then choose a value of C <=1 µF
Calculate the value of R using the equation
R= 1 / (2   fH  C)

R’=1 / (2   fL  C )
4. Because of the equal resistor R2=R3 and C2=C3 values the pass band voltage gain
AF = (1+R f / R1) of the second order low pass and high pass filter has to be equal
To 1.586 i.e. R f =0.586 R1 .This gain is necessary to guarantee Butterworth filter response.
Hence choose the value of R1 <100K and calculate the value for RF

5. Set the signal generator amplitude to 10V peak to peak and observe the input voltage
And output voltage on the CRO.
6. By varying the frequency of input from HZ range to KHA range, note the frequency
 And the corresponding output voltage across pin 6 of the op amp with respect to the
Ground.
7-.The output voltage (VO) remains constant at lower frequency range.
8. Tabulate the readings in the tabular column.
9 .Plot the graph with ‘f ‘on X-axis and gain in dB on Y axis.

Result: The frequency response of an active band reject filter for the desired cut off frequency
is designed and roll off factor is calculated.
 EXPERIMENT N0 11 (A)
ASTABLE MULTIVIBRATOR
AIM:
To design and verify the operation of astable multivibrator using 555 Timer for given
frequency and duty cycle.

APPARATUS REQUIRED:
Timer - 555
Resistors – 10k - 1
4.5k - 2
7.25k- 1
Capacitors – 0.01F-1
0.1F-1
Signal Generator, DC power supply, CRO and connecting wires

THEORY:
A 555 timer is a monolithic timing circuit that can produce accurate and highly stable
time delays or oscillations, some of the applications of 555 are square wave generator, astable
and monostable multivibrator.
Astable multivibrator is a free running oscillator has two quasi stable state in one state o/p
voltage remains low for a time interval of Toff and then switches over to other state in which the
o/p remains high for an interval of Ton the time interval Ton and Toff are determined by the
external resistors a capacitor and it does not require an external trigger, when the power is
switched on the timing capacitor begins to charge towards 2/3 Vcc through RA & RB, when the
capacitor voltage has reached this value, the upper comparator of the timer triggers the flip flop
in it and the capacitor begins to discharge through RB when the capacitor voltage reaches 1/3
Vcc the lower comparator is triggered and another cycle begins, the charging and discharging
cycle repeats between 2/3 Vcc and 1/3Vcc for the charging and discharging periods t1and t2
respectively. Since the capacitor charges through RA and RB and discharges through RB only the
charge and discharge are not equal as a consequence the output is not a symmetrical square wave
and the multivibrator is called an asymmetric astable multivibrator
CIRCUIT DIAGRAM:

SYMMETRIC MULTIVIBRATOIR
Vcc+5V

8 4
Ra
VC RE
C SE
T
7
DISCHARGE
Rb
O/P
D1 3
D2 OUTPUT
555D

6
THRESHOLD
CO
2 NT
TRIGGER GN RO
D L
C1
1 5
C2

ASSYMETRIC MULTIVIBRATOR

Vcc +5V
RA
8

4
RESET
VCC

7
DISCHARGE

RB
555 OUTPUT
3 CRO
6
THRESHOLD
CONTROL

2
TRIGGER
GND

C
1

0.01uf

DESIGN: 0

ASSYMETRIC: Given f = 1khz

Duty cycle = 60%

T = 0.693(Ra + 2Rb) C
F = 1.45/ [(Ra + 2Rb) C]
 Duty cycle = (Ra + Rb)/Ra + 2Rb)
1K = 1.45/ [(Ra + 2Rb) 0.1*10-6]
Ra + 2Rb = 14.5K
Ra + Rb = 8.7K
Assume Ra = 4.7K
Rb = 9.57K  10K
SYMETRIC Given f = 1khz
Duty cycle = 50%

Charging time = Discharging time

T = TON =TOFF

T = 0.693(Ra + Rb) C
F = 1.45/ [(Ra + Rb) C]
Duty cycle = (Ra + Rb)/Ra + Rb)
1K = 1.45/ [(Ra + Rb) 0.1*10-6]
Ra + 2Rb = 14.5K
Since the duty cycle is 50%, Ra = Rb

2Ra = 14.5K
Ra = 7.25K  6.8K
Rb = 7.25K  6.8K

PROCEDURE:

7. Connections are made as shown in the circuit diagram

8. Switch on the DC power supply unit

9. Observe the wave form on CRO at pin 3 and measure the o/p pulse amplitude

10. Observe the wave form on CRO at pin 6 and measure Vcmax and Vc min

11. Verify that Vcmax=2/3Vcc and Vc min=1/3 Vcc

12. Calculate the duty cycle D, o/p frequency and verify with specified value

TABULAR COLUMN
F(theo) =
Ra Rb C Ton Toff T F DY
1.45/(Ra + Rb)
 WAVEFORMS:

Upper threshold
Vc at pin 6 voltage
=2/3*Vcc Lower
2/3VCC threshold

Voltage
1/3VCC
=Vcc/3
0V t

Vout 5V
at pin 3
Toff
0V
t
Ton

RESULT: Thus the operation of astable multivibrator using 555 Timer for given frequency and
duty cycle is designed and verified.
 EXPERIMENT N0 11 (B)

MONOSTABLE MULTIVIBRATOR
AIM:
To design and verify the operation of monostable multivibrator using 555 Timer for
given Pulse width.

APPARATUS REQUIRED:
Timer - 555
Resistors – 10k - 1
Capacitors – 0.01F-1
0.1F-1
Signal Generator, DC power supply, CRO and connecting wires

THEORY:

Monostable multivibrator has a stable state and a quasi stable state, the output of it is normally
low and it corresponds to reset of the flip flop in the timer, on the application of external
negative trigger pulse at pin 2 the circuit is triggered and the flip flop in the timer is set which in
turn releases the short across C and pushes the output high, At the same time the voltage across
C rises exponentially with the time constant RAC and remains in this state for a period RAC even
if it is triggered again during this interval, When the voltage across the capacitor reaches 2/3
Vcc, the threshold comparator resets the flip flop in the timer which discharges C and the output
is driven low the circuit will remain in this state until the application of the next trigger pulse

CIRCUIT DIAGRAM
Vcc +5V
8

BY127 Rt RA
RESET
VCC

2 6
TRIGGER THRESHOLD
Input Ct
7
DISCHARGE
555
C
CONTROL

CRO 3
OUTPUT 0
GND
1

0.01uf

0
DESIGN:
Given Tp = 1ms
F = 1KHz

T = 1.1R C
Let C = 0.1uF
R = (1*10-3 ) / (1.1*0.1*10-6 )
R = 9.09 K  10K

PROCEDURE:

5. Rig up the circuit as shown in the figure after checking all the components.
6. Apply suitable inputs to the astable multivibrator (DC & Trigger inputs)
7. Observe the waveform across the timing capacitor in one channel and the output in the other
channel..
8. Verify the designed values and the repeat the above procedure for different set of values.

TABULAR COLUMN

R C Tp = 1.1RC Tp(prac)

WAVEFORMS:

Input trigger pulses

Vcc
T
t
Trigger pulses at pin 2

t
Capacitor voltage Vc at pin 5

Upper
threshold
voltage t
Output pulse at pin 3 2/3*Vcc

Tp t

T
RESULT: Thus the operation of monostable multivibrator using 555 Timer for given
pulse width is designed and verified.
 EXPERIMENT NO 10

FULL WAVE AND HALF WAVE PRECISION RECTIFIER

AIM:
Design and test the working of half and full Wave Precision Rectifier using op-amp.

COMPONENTS REQUIRED:
OP-Amp - A741 -1
Resistors - 10k - 3
22k - 1
3.3k - 1
Diodes - BY127 - 2

THEORY:
Precision Rectifier name itself suggests that it rectifies even lower input voltages i.e.
voltages less than 0.7v (diode drop). A rectifier is a device, which converts AC voltage to DC
voltage. Precision rectifier converts AC to pulsating DC. Normal rectifiers using transformers
cannot rectify voltages below 0.7v, so we go for precision rectifiers. In this circuit the diodes are
placed in such a way that one diode is forward biased in the positive half cycle and the other in
the negative half cycle. Consider the circuit diagram shown below. Here in the positive half
cycle D1 is forward biased and D2 is reverse biased. The simplified circuit will act as two
inverted amplifiers connected in series. Hence the total gain will be the product of individual
gains. During the negative half cycle, D1 is reverse biased and D2 is forward biased. Hence the
simplified circuit is an inverting amplifier connected in series with a non-inverting amplifiers.
Hence the output will be inverted and a DC output (unidirectional) is obtained .The precision
rectifier we are using is a full wave rectifier.

CIRCUIT DIAGRAM:
Half Wave rectifier

R1 = 22k R = 10k R = 10k

D1
7 +Vcc 7 +Vcc
Vin 2- 2-
6 6 Vout
R = 10k 3+ 3+
UA741 UA741
4 -Vcc D2 4
-Vcc
GND

R2 = 3.3K
DESIGN:
Given : Vo = +0.5V in the +ve cycle
= +0.1V in the -ve cycle
During the +ve half cycle the simplified circuit will be as shown below.

 V = (-R1 / R) Vin
V0 = (-R / R)V
= (-R / R) (-R1 / R) Vin
V0 = (R1/R) Vin
As V0 = 0.5V, Vin = 0.25V
 R1 / R = 0.5 / 0.25 = 2
Assume R = 10k , then
R1 = 20k
NOTE: A DRB can be used in the place of R1 and that resistance can be adjusted to 20K or
22K resistance can be used.
During the negative half cycle, the simplified circuit will be shown below.

I1 V

R1 R R
I2

7 +Vcc 7 +Vcc
2 - 2 -
Vin
A 6 6 Vout
R = 10k 3 + 3 +
B UA741 UA741

I3 4 -Vcc 4 -Vcc
GND

R2
V
Applying KCL at point A
I1 = I2 + I3
From virtual ground concept
VA = 0 ( VB = 0)
 I1 = Vin / R , I2 = -V / ( R1+R ), I3 = -V / R2
Vin / 10k = - V ( (1 / 30k) + (1 / R2) )
As Vin = - 0.25
 - 0.25 / 10k = -V ( (1 / 30k) + (1 / R2) ) --------(1)
As the second Op-Amp works as a non inverting amplifier
V0 = (1 + (R / R1) + R) V
= (1 + (10k / 30k) ) V ---------(2)
From (1) V = - 0.25 / 10k
= - V ( (R2 + 30k) / (30k x R2 ) )
 V = 0.75 R2 / ( R2 + 30k )
Substituting this in the equation (2) we get
V0 = (1 + 1 / 3) (0.75 R2 / (R2 + 30k) )
0.1 R2 + 3k = R2
0.9 R2 = 3k
 R2 = 3.3k

Full wave rectifier:

R1 = 22k R = 10k R = 10k

D1
7 +Vcc 7 +Vcc
2- 2-
Vin 6 6 Vout
R = 10k 3+ 3+
UA741 UA741
4 -Vcc D2 4 -Vcc
GND

R=10k
R2 = 3.3K
PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram.
2. Give an input of 0.5V peak to peak (sine wave).
3. Check and verify the designed values.
4. Design the same circuit for a different set of values.

WAVEFORMS:
Full wave rectifier:

Half wave rectifier:

Result: Thus the working of half and full Wave Precision Rectifier using op-amp has been
designed and tested.