Tda 3683

TDA3683
Multiple voltage regulator with switch and ignition buffer

Rev. 02 — 7 October 2005 Product data sheet
1. General description
• The TDA3683 is a multiple output voltage regulator with a power switch and an
ignition buffer. Several protections and diagnostic options are incorporated in this
design.
• The TDA3683 is primarily developed to cover the complete power supply
requirements in car radio applications.
• The standby regulators (regulators 1, 2 and 3) are especially designed to supply
digital circuitry that has to be permanently connected e.g. Controller Area Network
(CAN) bus, Digital Signal Processor (DSP) core and the microcontroller. In
combination with the reset delay capacitor (pin RDC1 or pin RDC2/3) and the reset
function (pin RST1 or pin RST2/3), a proper start-up sequence for a microcontroller is
guaranteed. The storage capacitor (pin STC) makes the standby regulator outputs
insensitive for short battery drops (e.g. during engine start-up).
• The switched regulators (regulators 4, 5, 6 and 7) are intended to be used as supply
for the tuner, logic, sound processor and CD / tape control.
• The power switch (pin PSW) can be used for switching the electrically powered
antenna, display unit and CD / tape drives.
• The ignition buffer is intended to produce a clean logic output signal when a polluted
ignition key signal is used as input.
2. Features
■ Three enable pin controlled standby regulators:
◆ REG1: 5 V / 600 mA controlled by the EN1 input
◆ REG2: 3.3 V / 200 mA controlled by the EN2/3 input
◆ REG3: 1.9 V / 150 mA controlled by the EN2/3 input
■ Four mode pin controlled switched regulators:
◆ REG4: 8.5 V / 350 mA
◆ REG5: 5 V / 1.8 A
◆ REG6: 3.3 V / 1.2 A
◆ REG7: 2.4 V to 10 V / 2 A adjustable using external resistor divider
■ One mode pin controlled power switch; 2.2 A continuous and 3 A surge, with delayed
lower current limit so as to be less sensitive to inrush currents
■ One independent ignition buffer (inverted output, open-collector) with good input
protection against high transients
■ A storage capacitor is included to provide back-up supply for the standby regulators in
the event of loss of battery supply
Philips Semiconductors TDA3683
■ A hold output (3-state) which can be used to communicate to a microcontroller in the

event of an internal or external fault condition, such as:
◆ Low supply indication in Standby mode
◆ One or more switched regulators (except REG7) out of regulation
◆ Power switch output short-circuited to ground
◆ Load dump, thermal pre-warning and thermal shutdown
■ Reset outputs (push-pull output stage) can be used to call a microcontroller in a
smooth way (adjustable delay) at the first power-up
■ Two supply pins that can withstand load dump pulses and negative supply voltages;
the second supply pin (connected to REG5 and REG6) can be supplied from a
separate external voltage (e.g. DC-to-DC downconverter) to reduce power dissipation
■ All regulator and power switch outputs are short-circuit proof to ground and supply
lines; the dissipation is limited in this condition since all regulators (except REG3) and
power switch have a foldback current protection incorporated
■ The TDA3683 has three modes of operation:
◆ Sleep: all outputs disabled (very low quiescent current)
◆ Standby: one or more standby regulators enabled (low quiescent current)
◆ On: all outputs enabled
■ The standby regulators (including the reset function) and the ignition buffer also
function during load dump and thermal shutdown; the switched regulators and power
switch will be disabled during these conditions
■ Hysteresis is incorporated on internal switching levels
■ The TDA3683 is protected against Electrostatic Discharge (ESD) on all pins
■ DBS23 package with low thermal resistance and flexible leads.
3. Quick reference data

Table 1: Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VP1 supply voltage 1 operating 9 14.4 18 V
reverse polarity; non-operating - - 18 V
regulators 1, 2 and 3 on 4.0 14.4 50 V
jump start; t ≤ 10 minutes - - 30 V
load dump protection; t ≤ 50 ms; - - 50 V
tr ≥ 2.5 ms
VP2 supply voltage 2 operating 6.5 14.4 18 V
reverse polarity; non-operating - - 18 V
regulators 1, 2 and 3 on 0 - 50 V
load dump protection; t ≤ 50 ms; - - 50 V
tr ≥ 2.5 ms
Iq(tot) total quiescent supply VEN1, VEN2/3 and VMODE < 0.8 V - 5 30 µA
current VMODE and VIGNIN < 0.8 V; - 300 450 µA
VEN1 and VEN2/3 > 2.4 V
Tj junction temperature operating −40 - +150 °C
TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 7 October 2005 2 of 31

Table 1: Quick reference data …continued

Voltage regulator; VP = 14.4 V
Vo(REG1) regulator 1 output 1 mA ≤ IREG1 ≤ 600 mA 4.75 5.0 5.25 V
voltage
voltage
voltage
voltage
voltage
voltage
Vo(REG7) output voltage of 1 mA ≤ IREG7 ≤ 2000 mA Vo − 5 % 2.4 to 10 Vo + 5 % V
regulator 7
Power switch
Vdrop(PSW) drop-out voltage IPSW = 1 A; VP1 = VP2 = 13.5 V - 0.45 0.65 V
IPSW = 2.2 A; VP1 = VP2 = 13.5 V - 1.0 1.8 V
IM(PSW) peak current VP1 = VP2 < 17 V 3 - - A
4. Ordering information
Table 2: Ordering information
Type number Package
Name Description Version
TDA3683J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
TDA3683SD RDBS23P plastic rectangular DIL-bent-SIL (reverse bent) power package; 23 leads SOT889-1
(row spacing 2.54 mm)

5. Block diagram
(14 V)
3000 mA surge
2200 mA continuous
(14.4 V) 1 3
VP1 POWER SWITCH PSW
TEMPERATURE
LOAD DUMP
& PROTECTION
TDA3683
(14 V)
BACKUP SWITCH 14 950 mA
STC
BACKUP CONTROL
(5 V)
19 15 600 mA
EN1 REGULATOR 1 REG1
(3.3 V)
20 13 200 mA
EN2/3 REGULATOR 2 REG2
(1.9 V)
12 150 mA
REGULATOR 3 REG3
+
RESET1
16
RST1
18
RDC1
22
ADJ7
10
RDC2/3 +
RESET2/3
8
RST2/3
&
REGULATOR 7
(2.4 V - 10 V)
21 2000 mA
REG7
17
& REGULATOR 4 REG4
(8.5 V)
350 mA
9
VP2
(5 V)
7 1800 mA
& REGULATOR 5 REG5
(3.3 V)
11 1200 mA
& REGULATOR 6 REG6
6
MODE
3-STATE
5
HOLD
&
THERMAL PREWARN
(> 140 °C)
4
IGNITION IGNOUT
2
IGNIN CLAMP
23
coa007
GND
Fig 1. Block diagram

6. Pinning information
6.1 Pinning
VP1 1
IGNIN 2
PSW 3
IGNOUT 4
HOLD 5
MODE 6
REG5 7
RST2/3 8
VP2 9
RDC2/3 10
REG6 11
TDA3683J
REG3 12
TDA3683SD
REG2 13
STC 14
REG1 15
RST1 16
REG4 17
RDC1 18
EN1 19
EN2/3 20
REG7 21
ADJ7 22
GND 23
001aaa683
Fig 2. Pin configuration
6.2 Pin description

Table 3: Pin description
Symbol Pin Description
VP1 1 supply voltage 1
IGNIN 2 ignition input
PSW 3 power switch output
IGNOUT 4 ignition output
HOLD 5 hold output
MODE 6 enable input for regulators 4, 5, 6, 7 and power switch
REG5 7 regulator 5 output
RST2/3 8 reset output for regulators 2 and 3
VP2 9 supply voltage 2 (for regulators 5 and 6)
RDC2/3 10 reset delay capacitor for regulators 2 and 3

Table 3: Pin description …continued

Symbol Pin Description
STC 14 storage capacitor (backup) output
RST1 16 reset output for regulator 1
RDC1 18 reset delay capacitor for regulator 1
EN1 19 enable input for regulator 1
EN2/3 20 enable input for regulators 2 and 3
ADJ7 22 regulator 7 adjust input
GND 23 ground / substrate [1]
[1] The heat tab is internally connected to pin GND.
7. Functional description
The TDA3683 is a multiple output voltage regulator with a power switch and ignition buffer.
The device is primarily intended for use in car radio applications. An overall functional
description of the building blocks is given in the following sections.
7.1 Standby regulators

The standby regulators (pins REG1, REG2 and REG3) are used for digital circuitry that
has to be permanently connected to a supply voltage (e.g. CAN bus DSP core or
microcontroller). REG1 is controlled by its own active HIGH enable input (EN1). REG2
and REG3 have a combined enable input (EN2/3) with similar logic properties. Permanent
voltage tracking will exist between REG2 and REG3 during power-up and power-down. All
standby regulators have a low quiescent current and will not be switched off during
thermal shutdown and load dump conditions. The outputs are protected against overload
and short-circuit conditions by a current limit / foldback protection.
7.2 Switched regulators

The switched regulators (pins REG4, REG5, REG6 and REG7) are activated by the active
HIGH mode input. The regulators are protected against overload and short-circuit
conditions by a current limit / foldback protection. They will be switched off during thermal
shutdown and load dump conditions. The output voltage of REG7 can be adjusted (2.4 V
to 10 V) by using two external resistors connected between the regulator output, the
feedback input and ground; see Figure 10. REG7 has a built-in flyback clamp for use in
case of inductive loads.

7.3 Power switch

The power switch (pin PSW) is activated by the MODE input. It is switched off during
thermal shutdown and load dump conditions. The power switch output voltage is internally
clamped at 16 V to protect connected application circuitry (e.g. display and CD / tape
drives). The power switch has three different output current modes, depending on its
output voltage, the reset capacitor (RDC1) and the junction temperature (i.e. high current,
low current and foldback protection); see Figure 7. In the event of an overload the power
switch can maintain the maximum output current for a limited period of time (determined
by the integration time of the reset delay capacitor) before it drops back to the lower output
current capability. This functionality is implemented to prevent, in case of loads such as
light bulbs, relays or electrical motors, the power switch from folding back on momentary
high inrush currents. In the event of junction temperatures above 150 °C, the power switch
will drop back to the lower output current capability.The power switch has a built-in flyback
clamp for use in case of inductive loads.
7.4 Enable and mode inputs

The enable inputs (pins EN1 and EN2/3) are used to switch on or switch off the standby
regulators. The mode input (MODE) is used to enable the switched regulators and the
power switch. When all of these inputs are LOW the circuit is in Sleep mode and only the
enable detection circuit and the supply overvoltage protection circuit are active. In Sleep
mode the device draws a very small quiescent current from the supply. When at least one
of the enable inputs is activated the circuit will operate in Standby mode. When the mode
input is activated the on condition will be established; before the MODE pin can be
activated at least one of the standby regulators must be activated. The enable and mode
inputs are 3.3 V and 5 V CMOS logic compatible. A detailed description of the enable and
mode pin dependencies is given in Table 4.
Table 4: Enable and mode pin dependencies

Pin Description
EN1 EN2/3 MODE
0 0 0 standby regulators, switched regulators, power switch and
ignition buffer disabled
0 0 1 standby regulators, switched regulators, power switch and
ignition buffer disabled
0 1 0 standby regulators 2 and 3 and ignition buffer enabled; standby
regulator 1, switched regulators and power switch disabled
0 1 1 standby regulators 2 and 3, switched regulators and ignition
buffer enabled; standby regulator 1 and power switch disabled
1 0 0 standby regulator 1 and ignition buffer enabled; standby
regulators 2 and 3, switched regulators and power switch
disabled
1 0 1 standby regulator 1, switched regulators, power switch and
ignition buffer enabled; standby regulators 2 and 3 disabled
1 1 0 standby regulators and ignition buffer enabled; switched
regulators and power switch disabled
1 1 1 standby regulators, ignition buffer, switched regulators and
power switch enabled

7.5 Storage capacitor

The storage capacitor (pin STC) is used as a back-up supply for the standby regulators
when the battery (pins VP1 / VP2) can no longer provide the supply. This situation may
occur for cold weather engine starts. The rising and falling storage capacitor voltage
threshold levels determine if the standby regulators can be switched on.
The storage capacitor pin is not intended to be used as an output (e.g. supply switch). No
external load should be connected to this pin.
7.6 Reset delay capacitors

The reset delay capacitors (pins RDC1 and RDC2/3) are used to delay the reset pulse
(RST1 and RST2/3) starting from the time the associated standby regulator output voltage
comes within its regulated voltage range i.e. crosses the rising reset threshold level. An
internal current source is used to charge the reset delay capacitor. The reset output will be
released (output goes HIGH) when the voltage on the reset delay capacitor crosses the
rising threshold level.
If the associated standby regulator voltage drops out of its regulated voltage range (drops
below its falling reset threshold level) the reset delay capacitor will be discharged with a
relatively high sink current. The reset output will be activated (output goes LOW) when the
reset delay capacitor crosses the falling threshold level. This feature is included to secure
a smooth start-up of the microcontroller at first connection, without uncontrolled switching
of the relevant standby regulators during a start-up sequence. It should be noted that
RDC1 is also used as a time constant for the delayed current protection of the power
switch.
7.7 Reset outputs

The reset function depends on the reset delay capacitor voltage and includes hysteresis
to avoid oscillation at the threshold level. The reset outputs are push-pull for sourcing or
sinking current. The output voltage can be switched between the ground level and the
output voltage of the relevant standby regulator. An external reset delay capacitor can be
added if a timed reset pulse is required (CRDC1 or CRDC2/3).
Standby regulator 1 has an independent reset function (pins RST1 and RDC1). Standby
regulators 2 and 3 have combined circuitry (pins RST2/3 and RDC2/3). The reset trigger
signals from both regulators are connected using an OR function to the reset output buffer
thus ensuring that both regulators can generate a reset when appropriate. The RST1
output is linked to standby regulator 1 (5 V) and, therefore, generates a 5 V HIGH-level
output voltage. The RST2/3 output is linked to regulator 2 (3.3 V) and, therefore,
generates a 3.3 V HIGH-level output voltage.
7.8 Hold output

The hold output (pin HOLD) is a combined output for the thermal pre-warning signal and
all other diagnostic signals. To distinguish between these signals, the HOLD output is
designed as an active HIGH 3-state output buffer. When a no failure condition is present
the output is LOW. When a thermal pre-warning signal is generated (e.g. to shut down
other circuits in the radio before the regulator itself shuts down) the signal rises to its MID

level. In all other warning situations, the HOLD output rises to its HIGH level. In order to
generate standard CMOS logic compliant signals an external decoding circuit has to be
implemented; see Figure 9.
The HOLD output will be active HIGH when:
• The output voltage of one or more switched regulators is out of regulation (except
REG7), due to overload or supply voltage drops
• The power switch operates in the Foldback mode
• In Standby or On mode the thermal shutdown is activated
• In Standby or On mode the load dump protection is activated
• In Standby mode a low battery voltage occurs (VP1) indicating that it is not possible to
pull REG4 into regulation when switching it on.
It should be noted that there is intentionally no out-of-regulation detection for REG7 since
it can be adjusted to maximum 10 V and would, in that event, activate the HOLD signal
very early.
The HOLD function includes hysteresis in order to avoid oscillations when the hold
threshold level is crossed. A schematic diagram of the HOLD function is illustrated in
Figure 3.

low battery
VP1 detector
internal
voltage reference 1 TDA3683
(8.5 V)
internal (350 mA)
output stage
voltage REG4
reference 2
out of
regulation
enable detector
MODE
REGULATOR 4
(5 V)
output stage (1800 mA)
REG5
out of
regulation
detector
REGULATOR 5
AND
(3.3 V)
REG6
3-STATE
OR
HOLD
out of
regulation
detector
REGULATOR 6
POWER SWITCH
TEMPERATURE
LOAD DUMP FOLDBACK
PROTECTION (2.4 V − 10 V)
MODE
REG7
THERMAL
PREWARN
(> 140 °C)
REGULATOR 7
EN1
OR
EN2/3
coa008
Fig 3. Schematic diagram of the HOLD function

7.9 Ignition buffer

The ignition buffer (pins IGNIN and IGNOUT) is an independent inverting open-collector
output buffer circuit that can be used to sense the start line of the ignition key in a car. The
start line will only be pulled-up to the battery voltage in the event of an engine crank
resulting in a LOW at the inverting output of the ignition buffer. This output signal can be
used to immediately mute an audio amplifier during the engine crank.
To guarantee a reliable LOW output signal, even in extreme cold weather crank conditions
(the battery voltage may momentarily drop down to 3 V) a low supply latch function is
implemented.
To make the ignition buffer input robust, for possible extreme transients present on the
battery line, an input RC filter is strongly advised. A blocking diode is also recommended
to prevent substrate injection in case of negative voltage spikes at the input.
7.10 Supply voltage inputs

The supply voltage inputs (pins VP1 and VP2) are intended to be connected to the battery.
Both inputs are protected against load dump transients and reverse battery connections.
The second supply pin (VP2) is internally connected to the high current/ low output voltage
switched regulators (REG5 and REG6) and can be connected to an external DC-to-DC
downconverter for reduced power dissipation and increased power supply efficiency.
Power must be applied to pin VP1 to ensure that the circuits are functional, since the band
gaps for the switched and standby regulators are connected to this supply pin.
Rising and falling supply voltage threshold levels determine if the switched regulators and
power switch can be switched on.
The timing diagrams for various regulator functions are illustrated in Figure 4 and
Figure 5.

load dump
VP1 = VP2
STC 6.5 V
5.4 V
EN1 > 1.8 V

< 1.3 V
REG1 5V
0V
3.5 V
RDC1 3V
0V
5V
RST1
reset behaviour for regulator 1
load dump
VP1 = VP2
6.5 V
STC 3.9 V
2.5 V
EN2/3 > 1.8 V

< 1.3 V
REG2 3.3 V
0V
REG3 1.9 V
0V
3.3 V
RDC2/3 2.7 V
0V
3.3 V
RST2/3
reset behaviour for regulators 2 and 3
load dump
VP1 = VP2 7V
4.5 V
50 V
> 3.25 V
IGNIN
< 1.1 V
−100 V
IGNOUT 5V
0V
Schmitt trigger ignition (start-up) buffer 001aaa685
Fig 4. Timing diagram of the reset outputs for REG1, REG2 and REG3 and ignition Schmitt trigger

> 22 V
VP1 = VP2 > 9V
> 1.8 V
EN1 < 1.3 V
> 1.8 V
MODE
< 1.3 V
VO(REGx)
REG4, REG5
or REG6
16 V
PSW
> 2V
T (°C) > 150

> 140
HIGH
HOLD MID
LOW
hold output behaviour
load dump
18 V
VP1 = VP2 8.9 V
7.0 V
4.0 V
> 1.8 V
MODE
< 1.3 V
8.5 V
REG4
0V
5.0 V
REG5
0V
EN1 > 1.8 V
< 1.3 V
3.3 V
REG1
0V
VP and enable Schmitt trigger
load dump
16.9 V
VP1 = VP2
7.0 V
4.0 V
> 1.8 V
MODE
< 1.3 V
16 V
PSW
0V
power switch behaviour 001aaa686
Fig 5. Timing diagram of the HOLD output, VP and Schmitt trigger and power switch

8. Limiting values
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VP1 supply voltage 1 operating - 18 V
reverse polarity; non-operating - 18 V
jump start; t ≤ 10 minutes - 30 V
load dump protection; t ≤ 50 ms; tr ≥ 2.5 ms - 50 V
VP2 supply voltage 2 operating - 18 V
reverse polarity; non-operating - 18 V
jump start; t ≤ 10 minutes - 30 V
load dump protection; t ≤ 50 ms; tr ≥ 2.5 ms - 50 V
Tstg storage temperature non-operating −55 +150 °C
Tamb ambient temperature operating −40 +85 °C
Tj junction temperature operating −40 +150 °C
9. Thermal characteristics
Table 6: Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-c) thermal resistance from junction to case 1 K/W
Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W
10. Characteristics
Table 7: Characteristics
VP1 = VP2 = 14.4 V; Tamb = 25 °C; RL= ∞ Ω; measured in test circuits of Figure 8; unless otherwise specified.
Supplies
VP1 supply voltage 1 operating 9 14.4 18 V
regulators 1, 2 and 3 on [1] 4.0 14.4 50 V
load dump protection; - - 50 V
t ≤ 50 ms; tr ≥ 2.5 ms
VP2 supply voltage 2 operating 6.5 14.4 18 V
regulators 1, 2 and 3 on 0 - 50 V
load dump protection; - - 50 V
t ≤ 50 ms; tr ≥ 2.5 ms
Vbat(loaddump) battery overvoltage VP1 and/or VP2 18 20 22 V
shutdown

Table 7: Characteristics …continued

Iq(tot) total quiescent supply VEN1, VEN2/3 and - 5 30 µA
current VMODE < 0.8 V
VMODE and VIGNIN < 0.8 V; - 300 450 µA
VEN1 and VEN2/3 > 2.4 V
VEN1 > 2.4 V; VEN2/3 < 0.8 V
VEN1 < 0.8 V; VEN2/3 > 2.4 V
Schmitt trigger for power supply (regulators 4, 5, 6, 7 and power switch)
Vth(r) rising threshold voltage VP1 and VP2 rising 6.5 7.0 7.5 V
Vth(f) falling threshold voltage VP1 and VP2 falling 4.0 4.5 5.0 V
Vhys hysteresis voltage - 2.5 - V
Schmitt trigger for enable (EN1, EN2/3) and MODE inputs
Vth(r) rising threshold voltage 1.4 1.8 2.4 V
Vth(f) falling threshold voltage 0.9 1.3 1.9 V
Vhys hysteresis voltage IREGx = IPSW = 1 mA - 0.5 - V
ILI input leakage current VENx/MODE = 5 V 1 5 20 µA
Reset trigger level of regulator 1
Vth(r) rising threshold voltage VP1 and VP2 rising; [2] 4.43 VREG1 − 0.15 VREG1 − 0.1 V
IREG1 = 50 mA
Vth(f) falling threshold voltage VP1 and VP2 falling; [2] 4.4 VREG1 − 0.25 VREG1 − 0.13 V
IREG1 = 50 mA
IREG2 = 50 mA
IREG2 = 50 mA
IREG3 = 50 mA
IREG3 = 50 mA
Schmitt triggers for HOLD output
Vth(r)(REG4) rising threshold voltage VP1 and VP2 rising [2] - VREG4 − 0.15 VREG4 − 0.075 V
of regulator 4
Vth(f)(REG4) falling threshold voltage VP1 and VP2 falling [2] 7.9 VREG4 − 0.35 - V
of regulator 4
Vhys(REG4) hysteresis voltage due - 0.2 - V
to regulator 4
of regulator 5
of regulator 5


to regulator 5
of regulator 6
of regulator 6
to regulator 6
Vth(r)(VP) rising threshold voltage VP1 and VP2 rising; 7.8 8.4 9 V
of supply voltage VMODE < 0.8 V;
VEN1 or VEN2/3 > 2.4 V
Vth(f)(VP) falling threshold voltage VP1 and VP2 falling; 7.7 8.1 8.5 V
of supply voltage VMODE < 0.8 V;
VEN1 or VEN2/3 > 2.4 V
Vhys(VP) hysteresis voltage of - 0.3 - V
supply voltage
Hold buffer
Vo(HOLD)(L) LOW-level HOLD 0 0.1 0.6 V
output
Isink(L) LOW-level sink current VHOLD ≤ 0.6 V 0.5 - - mA
Vo(HOLD)(H) HIGH-level HOLD 6.0 7.0 8.0 V
output
Isource(H) HIGH-level source VHOLD = 3.3 V 1 2 - mA
current
Vo(HOLD)(M) MID-level HOLD output 1.8 2.15 2.5 V
Isource(M) MID-level source VHOLD = 1.5 V 1 2 - mA
current
tr rise time CL = 50 pF - 7 50 µs
tf fall time CL = 50 pF - 1 50 µs
Reset and Reset delay 1
Isink(L) LOW-level sink current VRST1 ≤ 0.8 V; VRDC1 < 1.0 V 2 - - mA
Isource(H) HIGH-level source VRST1 = 4.5 V; 240 400 900 µA
current VRDC1 > 3.5 V
Ich charge current VRDC1 = 0 V; VEN1 > 2.4 V 2 4 8 µA
Idch discharge current VRDC1 = 3 V; 1.0 1.6 - mA
VP1 = VP2 = 4.3 V
Vth(r)(RDC1) reset delay capacitor 1 [3] 2.5 3.0 3.5 V
rising voltage threshold
Vth(f)(RDC1) reset delay capacitor 1 [3] 1.0 1.2 1.4 V
falling voltage threshold
td(RST1) delay time reset signal CRDC1 = 47 nF [4] 20 35 70 ms


td(PSW) delay time power CRDC1 = 47 nF [5] 8 17.5 40 ms
switch foldback
protection
VOH(RST1) HIGH-level output IRST1 = 0 A 4.5 5 5.25 V
voltage on pin RST1
VOL(RST1) LOW-level output IRST1 = 0 A 0 0.2 0.8 V
voltage on pin RST1
Reset and reset delay 2/3
Isink(L) LOW-level sink current VRST2/3 ≤ 0.6 V; 2 - - mA
VRDC2/3 < 1.0 V
Isource(H) HIGH-level source VRST2/3 = 2.7 V; 240 400 900 µA
current VRDC2/3 > 3.2 V
Ich charge current VRDC2/3 = 0 V; VEN2/3 > 2.4 V 2 4 8 µA
Idch discharge current VRDC2/3 = 2.7 V; 1.0 1.6 - mA
VP1 = VP2 = 3 V
Vth(r)(RDC2/3) reset delay capacitor [6] 2.2 2.7 3.2 V
2/3 rising voltage
threshold
Vth(f)(RDC2/3) reset delay capacitor [6] 1.0 1.2 1.4 V
2/3 falling voltage
threshold
VOH(RST2/3) HIGH-level output IRST2/3 = 0 A 3.0 3.3 3.45 V
voltage on pin RST2/3
VOL(RST2/3) LOW-level output IRST2/3 = 0 A 0 0.2 0.6 V
voltage on pin RST2/3
td(RST2/3) delay time reset signal CRDC2/3 = 47 nF [4] 20 35 70 ms
Regulator 1 (IREG1 = 5 mA; unless otherwise specified)
Vo(REG1) output voltage 1 mA ≤ IREG1 ≤ 600 mA 4.75 5.0 5.25 V
7 V ≤ VP1/2 ≤ 18 V 4.75 5.0 5.25 V
18 V ≤ VP1/2 ≤ 50 V 4.75 5.0 5.25 V
∆V line regulation 7 V ≤ VP1/2 ≤ 18 V - 2 100 mV
∆VL load regulation 1 mA ≤ IREG1 ≤ 300 mA - 20 50 mV
1 mA ≤ IREG1 ≤ 600 mA - - 100 mV
PSRR supply voltage ripple fi = 3 kHz; Vi = 2 V (p-p) 40 45 - dB
rejection
Vdrop(REG1) drop-out voltage IREG1 = 300 mA; [7] - 0.4 0.6 V
VP1 = VP2 = 4.75 V
IREG1 = 600 mA; [7] - 0.8 1.2 V
VP1 = VP2 = 5.75 V
IREG1 = 300 mA; [8] - 0.2 0.5 V
VSTC = 4.75 V
IREG1 = 600 mA; [8] - 0.8 1.0 V
VSTC = 5.75 V


Im(REG1) current limit VREG1 > 4.5 V [9] 640 1400 2500 mA
Ist(REG1) start-up current VREG1 ≤ 1.5 V 120 - - mA
Isc(REG1) short-circuit current RL ≤ 0.5 Ω [10] 160 250 - mA
7 V ≤ VP1/2 ≤ 18 V 3.15 3.3 3.45 V
18 V ≤ VP1/2 ≤ 50 V 3.15 3.3 3.45 V
1 mA ≤ IREG2 ≤ 200 mA - - 100 mV
rejection
VP1 = VP2 = 4.0 V
IREG2 = 200 mA; [8] - 0.75 0.85 V
VSTC = 4.0 V
Im(REG2) current limit VREG2 > 3 V [9] 225 800 1500 mA
4.0 V ≤ VP1/2 ≤ 18 V 1.72 1.9 2.0 V
18 V ≤ VP1/2 ≤ 50 V 1.72 1.9 2.0 V
1 mA ≤ IREG3 ≤ 150 mA - - 100 mV
rejection
VP1 = VP2 = 4.0 V
IREG3 = 150 mA; [8] - 2.20 2.28 V
VSTC = 4.0 V
Im(REG3) current limit VREG3 > 1.6 V [9] 160 600 1000 mA
Vo(REG2) - output voltage tracking 0 ≤ VP1/2 ≤ 18 V - - 2.8 V
Vo(REG3) REG3 to REG2
Vo(off) output voltage off - 1 400 mV
9.5 V ≤ VP1/2 ≤ 18 V 8.1 8.5 8.9 V
∆V line regulation 9.5 V ≤ VP1/2 ≤ 18 V - 2 50 mV


rejection
VP1 = VP2 = 8.55 V
Im(REG4) current limit VREG4 > 7 V [9] 400 1300 2000 mA
7 V ≤ VP1/2 ≤ 18 V 4.75 5.0 5.25 V
∆V line regulation 7 V ≤ VP2 ≤ 18 V - 2 50 mV
rejection
Vdrop(REG5) drop-out voltage IREG5 = 1800 mA; VP2 = 6 V [7] - 1 1.5 V
Im(REG5) current limit VREG5 > 4.5 V [9] 2.0 4.5 6.25 A
Isc(REG5) short-circuit current RL ≤ 0.5 Ω [10] 1.0 1.2 - A
7 V ≤ VP1/2 ≤ 18 V 3.15 3.3 3.45 V
∆V line regulation 5 V ≤ VP2 ≤ 18 V; VP1 = 7 V - 2 50 mV
∆VL load regulation 1 mA ≤ IREG6 ≤ 1200 mA; - 20 50 mV
Tamb > 0 °C
1 mA ≤ IREG6 ≤ 1200 mA; - 35 70 mV
Tamb ≤ 0 °C
rejection
Vdrop(REG6) drop-out voltage IREG6 = 1200 mA ; VP2 = 5 V [7] - 1.7 2.2 V
Im(REG6) current limit VREG6 > 3.0 V [9] 1.3 2.9 4.0 A
Vo(REG7) output voltage 1 mA ≤ IREG7 ≤ 2000 mA Vo − 5 % 2.4 to 10 Vo + 5 % V
11 V ≤ VP1/2 ≤ 18 V Vo − 5 % 2.4 to 10 Vo + 5 % V
rejection


Vdrop(REG7) drop-out voltage IREG7 = 1000 mA; Vo = 10 V; [7] - 1.0 1.25 V
VP1 = VP2 = 10.75 V
IREG7 = 2000 mA; Vo = 10 V; [7] - 1.25 1.5 V
VP1 = VP2 = 10.75 V
IREG7 = 1000 mA; Vo = 5 V; [7] - 1.0 1.25 V
VP1 = VP2 = 5.75 V
IREG7 = 2000 mA; Vo = 5 V; [7] - 1.25 1.5 V
VP1 = VP2 = 5.75 V
IREG7 = 1000 mA; [7] - 2.6 3.1 V
Vo = 2.4 V; VP1 = VP2 = 5 V
IREG7 = 2000 mA; [7] - 2.6 3.4 V
Vo = 2.4 V; VP1 = VP2 = 5 V
Im(REG7) current limit VREG7 > 8.0 V at Vo = 10 V [9] 2.1 3.7 5.5 A
or
VREG7 > 1.9 V at Vo = 2.4 V
Vfb(REG7) flyback voltage IREG7 = −1000 mA - VP1 + 3 22 V
Power switch
Vdrop(PSW) drop-out voltage IPSW = 1 A; [11] - 0.45 0.65 V
VP1 = VP2 = 13.5 V
IPSW = 2.2 A; [11] - 1.0 1.8 V
VP1 = VP2 = 13.5 V
IDC(PSW) continuous current VP1 = VP2 = 16 V; 2.2 4.3 6.0 A
VPSW = 13.5 V
Vclamp(PSW) clamping voltage VP1 = VP2 ≥ 17 V; 13.5 15.0 16.0 V
1 mA < IPSW < 2.2 A
IM(PSW) peak current VP1 = VP2 < 17 V [5] 3 - - A
Vfb(PSW) flyback voltage IPSW = −1000 mA - VP1 + 3 22 V
Isc(PSW) short-circuit current VP1 = 14.4 V; VPSW < 1.0 V 0.75 1.0 - A
Storage capacitor switch
IDC(STC) continuous current VSTC > 5 V 0.95 1.0 - A
Vclamp(STC) clamping voltage VP1 = VP2 ≥ 16.7 V; - - 16 V
ISTC = 100 mA
Ir(STC) reverse current VP1 = VP2 = 0 V; - - 100 µA
VSTC = 12.4 V
Vth(STC) regulator enable VEN1 or VEN2/3 > 2.4 V [12] 5.5 6.5 7.5 V
threshold voltage
Schmitt trigger for enable input of ignition
Vth(r) rising threshold voltage VEN1 or VEN2/3 > 2.4 V 2.75 3.25 3.75 V
of ignition input
Vth(f) falling threshold voltage VEN1 or VEN2/3 > 2.4 V 0.8 1.1 1.3 V
of ignition input
Vhys hysteresis voltage VEN1 or VEN2/3 > 2.4 V 1.5 - - V
ILI input leakage current VIGNIN = 5 V - - 1.0 µA
II(clamp) input clamping current VIGNIN > 50 V - - 50 mA


VIH(clamp) HIGH-level input VIGNIN = 50 V VP - 50 V
clamping voltage
VIL(clamp) LOW-level input VIGNIN = −100 V −0.6 - 0 V
clamping voltage
Schmitt trigger for power supply of ignition
Vth(r) rising threshold voltage 6.5 7.0 7.5 V
Vth(f) falling threshold voltage VIGNOUT = LOW; 4.0 4.5 5.0 V
VIGNIN > 1.2 V
Ignition buffer
VOL LOW-level output IIGNOUT = 0 mA 0 0.2 0.8 V
voltage
VOH HIGH-level output IIGNOUT = 0 mA 4.5 5.0 5.25 V
voltage
Io(sink)(L) LOW-level output sink VIGNOUT ≤ 0.8 V 0.6 0.8 - mA
current
ILO output leakage current VIGNOUT = 5 V; VIGNIN = 0 V - - 1.0 µA
Temperature protection
Tj(sd) junction temperature 150 160 170 °C
for shutdown
Tj(HOLD) junction temperature 140 150 160 °C
for HOLD thermal
pre-warning
∆Tj delta junction 10 - - °C
temperature
pre-warning / shutdown
[1] Minimum operating voltage, only if VP1 has first exceeded 6.5 V.
[2] The voltage of the regulators 1, 2, 3, 4 and 7 drops as a result of decreasing VP1 voltage. The output voltage of regulators 5 and 6 drops
as a result of decreasing VP2 voltage.
[3] Pin RST1 goes HIGH when Vth(r)(RDC1) is reached and goes LOW when reaching Vth(f)(RDC1).
C 3
[4] The delay time depends on the value of CRDC1 or CRDC2/3: t d = ------- × V C ( th ) = C × ( 750 × 10 ) [ s ]
I ch
C 3
[5] The delay time depends on the value of CRDC1: t d_high current = ------- × V C ( th ) = C × ( 375 × 10 ) [ s ]
I ch
[6] Pin RST2/3 goes HIGH when Vth(r)(RDC2/3) is reached and goes LOW when reaching Vth(f)(RDC2/3).
[7] The drop-out voltage of regulators 1,2,3,4 and 7 is measured between VP1 and REG1, REG2, REG3, REG4 or REG7, the drop-out
voltage of regulators 5 and 6 is measured between VP2 and REG5 or REG6.
[8] The drop-out voltage is measured between pins STC and REG1, REG2 and REG3.
[9] At current limit, Im(REGn) is held constant; see Figure 6.
[10] The foldback current protection limits the dissipated power at short circuit; see Figure 6.
[11] The drop-out voltage of the power switch is measured between pins VP1 and PSW; see Figure 7.
[12] Standby regulators are enabled when the increasing storage capacitor voltage reaches this threshold voltage at first power-up.

001aaa687
Vo(REGx)
Isc(REGx) Im(REGx)
IREGx
Fig 6. Typical foldback current protection curve for all regulators (except REG3)
001aaa688
VSW
VP − 3.3 V
not
generates delayed delayed
hold
2VBE
1A > 2.2 A >3A

ISW
Fig 7. Current protection of the power switch

11. Application information
VP1 HOLD to hold decoder

1 5
circuit
C8a C8b REG1
1000 µF 220 nF 15
C1b C1a
R4 100 nF 47 µF
VP2 10 kΩ
9
4
C9a C9b
IGNOUT
1000 µF 220 nF
EN1 REG2
19 13
C2b C2a
100 nF 47 µF
EN2/3 20
REG3
12
MODE C3b C3a
6 100 nF 47 µF
R3
IGNIN PSW
2 3
10 kΩ R5
C14 C10b C10a
100
1 nF 100 nF 47 µF
kΩ
TDA3683
RST1 REG4
16 17
C4b C4a
100 nF 47 µF
RDC1
18
C13 REG5
47 nF 7
C5b C5a
100 nF 47 µF
RST2/3
8
REG6
11
C6b C6a
100 nF 47 µF
RDC2/3
10
C12 REG7
47 nF 21
C7b C7a
R1 100 nF 47 µF
STC ADJ7
14 22
C11
1000 µF R2
23
001aaa689
Fig 8. Test and application circuit

REG2 output
3.3 V
D1
HOLD output
R3
2 kΩ
T2 R7
10 kΩ
R1 R4
18 kΩ 10 kΩ
temperature diagnostic
prewarn
R6
6.8 kΩ
T1 T3
R2 R5
27 kΩ 330 kΩ
001aaa690
R1 to R7: Standard E12 series resistor, 5 % tolerance

T1, T3: Standard small signal NPN transistor
T2: Standard small signal PNP transistor
D1: Low forward voltage (Schottky) diode
Fig 9. Hold decoder circuit
11.1 Application notes

• A ceramic capacitor of 220 nF must be connected to both supply pins to guarantee
stability over the ambient temperature range. For improved noise performance it is
also recommended to connect a standard electrolytic capacitor of 2200 µF close to
the supply pins.
• A ceramic capacitor of 220 nF must be connected to the storage capacitor pin when
the back-up function is not used to guarantee stability over the ambient temperature
range. There are basically no restrictions for the maximum value of the storage
capacitor, but the required value depends on the actual output currents of the three
standby regulators and the length of time that their outputs must be maintained after
the supply voltage collapsed (VP1 = VP2 = 0 V).
• A standard electrolytic capacitor of 10 µF, or more, must be connected to the output of
the power switch to guarantee stability over the ambient temperature range. A ceramic
capacitor of 100 nF can be added in parallel with the electrolytic capacitor to provide
improved HF performance.
• An electrolytic capacitor of 10 µF, or more, must be connected to each regulator
output to guarantee stability over the ambient temperature range. There are
restrictions concerning the maximum ESR of the electrolytic capacitors that are used;
see Table 8. Usually the nominal value of electrolytic capacitors increases and the
ESR decreases with temperature so the worst case condition for stability (i.e.
minimum capacitance and maximum ESR) exists at low temperatures. Depending on
the specified temperature range of the radio set, some of the regulator outputs may
need low ESR type electrolytic or tantalum capacitors. A ceramic capacitor of 100 nF
can be added in parallel with the electrolytic or tantalum capacitor to provide improved
HF performance. However, in the case of the standby regulators (REG1 to REG3)
these additional ceramic capacitors should preferably not be connected very close to
the device pins to avoid stability issues.

• The output voltage of regulator 7 can be adjusted between 2.4 V and 10 V using two
external resistors (R1 and R2); see Figure 10. The following equation can be used for
global calculations to determine the output voltage at a given value of R1 and R2:
V REG7 = 1.2 ×  1 + -------

R1
 R2
To meet an overall accuracy of 5 % the external resistors should have a 1 % tolerance

and the total resistance of the external resistors should have a value maximum 2 kΩ.
In the event that no external resistors are used the output voltage will be determined only
by the internal feedback resistors. The output voltage will be as follows: Vo = 10 V (±5 %).
Table 8: ESR restrictions

Output of regulator Maximum ESR
Regulator 1 3Ω
Regulator 2 3Ω
Regulator 3 6Ω
Regulator 4 20 Ω
Regulator 5 6Ω
Regulator 6 14 Ω
Regulator 7 10 Ω
TDA3683
1.2 V REG7
R1
(1 %)
ADJ7
R2
(1 %)
001aac136
Fig 10. Application diagram for REG7

12. Package outline
DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
non-concave
x Dh
Eh
view B: mounting base side
A2
d A5
β A4
B E2
j
E
E1
L2
L1 L3
L Q c v M
1 23
e1 m e2
Z w M
bp
e
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A 2 A4 A5 bp c D (1) d D h E (1) e e1 e2 Eh E1 E2 j L L1 L2 L3 m Q v w x β Z (1)
4.6 1.15 1.65 0.75 0.55 30.4 28.0 12.2 6 10.15 6.2 1.85 3.6 14 10.7 2.4 2.1 1.43
mm 12 2.54 1.27 5.08 4.3 0.6 0.25 0.03 45°
4.3 0.85 1.35 0.60 0.35 29.9 27.5 11.8 9.85 5.8 1.65 2.8 13 9.9 1.6 1.8 0.78
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
98-02-20
SOT411-1
02-04-24
Fig 11. Package outline SOT411-1 (DBS23P)


RDBS23P: plastic rectangular-DIL-bent-SIL (reverse bent) power package; 23 leads

(row spacing 2.54 mm) SOT889-1
non-concave
D x Dh
Eh
view B: mounting base side
d A2
β A5
A4
B
j
E
E1
A
L
c e2
1 23
Q
Z e1 w M L1 v M
bp
e
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A2 A4 A5 bp c D (1) d Dh E (1) e e1 e2 Eh E1 j L L1 Q v w x β Z (1)
4.6 1.15 1.65 0.75 0.55 30.4 28.0 12.2 6 10.15 1.85 3.75 3.75 2.1 1.43
mm 13.5 12 2.54 1.27 2.54 0.6 0.25 0.03 45°
4.3 0.85 1.35 0.60 0.35 29.9 27.5 11.8 9.85 1.65 3.15 3.15 1.8 0.78
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
05-02-15
SOT889-1
05-03-24
Fig 12. Package outline SOT889-1 (RDBS23P)

13. Soldering
13.1 Introduction to soldering through-hole mount packages

This text gives a brief insight to wave, dip and manual soldering. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
13.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
13.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
13.4 Package related soldering information

Table 9: Suitability of through-hole mount IC packages for dipping and wave soldering
methods
Package Soldering method
Dipping Wave
CPGA, HCPGA - suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable [1]
PMFP [2] - not suitable
[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2] For PMFP packages hot bar soldering or manual soldering is suitable.

14. Revision history

Table 10: Revision history
Document ID Release date Data sheet status Change notice Doc. number Supersedes
TDA3683_2 20051007 Product data sheet - - TDA3683J_1
Modifications: • Replaced through the document TDA3683J with TDA3683
• Section 4 “Ordering information”: Added TDA3683SD (SOT889-1 package)
• Section 7.5 “Storage capacitor”: Added last paragraph
• Section 10 “Characteristics”
– Added on page 15 two values to Iq(tot)
– Changed on page 16 symbols Vth(r)(RST1) and Vth(f)(RST1) to Vth(r)(RDC1) and Vth(f)(RDC1) with
adapted parameter description
– Added on page 16 parameters VOH(RST1) and VOL(RST1)
– Changed on page 17 symbols Vth(r)(RST2/3) and Vth(f)(RST2/3) to Vth(r)(RDC2/3) and Vth(f)(RDC2/3)
with adapted parameter description
– Added on page 17 parameters VOH(RST2/3) and VOL(RST2/3)
– Changed on page 18 to 20 the values of Im(REG1) to Im(REG7) and IDC(PSW)
• Figure 9: Added a figure note with component specifications
• Section 12 “Package outline”: Added SOT889-1 drawing
TDA3683J_1 20041213 Preliminary data sheet - 9397 750 13057 -

15. Data sheet status
Level Data sheet status [1] Product status [2] [3] Definition
I Objective data Development This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is Right to make changes — Philips Semiconductors reserves the right to
extracted from a full data sheet with the same type number and title. For make changes in the products - including circuits, standard cells, and/or
detailed information see the relevant data sheet or data handbook. software - described or contained herein in order to improve design and/or
Limiting values definition — Limiting values given are in accordance with performance. When the product is in full production (status ‘Production’),
the Absolute Maximum Rating System (IEC 60134). Stress above one or relevant changes will be communicated via a Customer Product/Process
more of the limiting values may cause permanent damage to the device. Change Notification (CPCN). Philips Semiconductors assumes no
These are stress ratings only and operation of the device at these or at any responsibility or liability for the use of any of these products, conveys no
other conditions above those given in the Characteristics sections of the license or title under any patent, copyright, or mask work right to these
specification is not implied. Exposure to limiting values for extended periods products, and makes no representations or warranties that these products are
may affect device reliability. free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Trademarks
Notice — All referenced brands, product names, service names and
17. Disclaimers trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information

For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Standby regulators . . . . . . . . . . . . . . . . . . . . . . 6
7.2 Switched regulators . . . . . . . . . . . . . . . . . . . . . 6
7.3 Power switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.4 Enable and mode inputs . . . . . . . . . . . . . . . . . . 7
7.5 Storage capacitor . . . . . . . . . . . . . . . . . . . . . . . 8
7.6 Reset delay capacitors . . . . . . . . . . . . . . . . . . . 8
7.7 Reset outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.8 Hold output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.9 Ignition buffer . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.10 Supply voltage inputs . . . . . . . . . . . . . . . . . . . 11
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
9 Thermal characteristics. . . . . . . . . . . . . . . . . . 14
10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14
11 Application information. . . . . . . . . . . . . . . . . . 23
11.1 Application notes . . . . . . . . . . . . . . . . . . . . . . 24
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26
13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1 Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.2 Soldering by dipping or by solder wave . . . . . 28
13.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 28
13.4 Package related soldering information . . . . . . 28
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29
15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 30
16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
19 Contact information . . . . . . . . . . . . . . . . . . . . 30
© Koninklijke Philips Electronics N.V. 2005

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 7 October 2005
Document number: TDA3683_2
Published in The Netherlands

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TDA3683

Multiple voltage regulator with switch and ignition buffer

■ A hold output (3-state) which can be used to communicate to a microcontroller in the

3. Quick reference data

Product data sheet Rev. 02 — 7 October 2005 2 of 31

Table 1: Quick reference data …continued

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 3 of 31

Fig 1. Block diagram

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 4 of 31

Fig 2. Pin configuration

6.2 Pin description

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 5 of 31

Table 3: Pin description …continued

[1] The heat tab is internally connected to pin GND.

7.1 Standby regulators

7.2 Switched regulators

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 6 of 31

7.3 Power switch

7.4 Enable and mode inputs

Table 4: Enable and mode pin dependencies

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 7 of 31

7.5 Storage capacitor

7.6 Reset delay capacitors

7.7 Reset outputs

7.8 Hold output

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 8 of 31

The HOLD output will be active HIGH when:

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 9 of 31

Fig 3. Schematic diagram of the HOLD function

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 10 of 31

7.9 Ignition buffer

7.10 Supply voltage inputs

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 11 of 31

EN1 > 1.8 V

reset behaviour for regulator 1

EN2/3 > 1.8 V

reset behaviour for regulators 2 and 3

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 12 of 31

VP1 = VP2 > 9V

T (°C) > 150

EN1 > 1.8 V

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 7 October 2005 13 of 31

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Product data sheet Rev. 02 — 7 October 2005 14 of 31

Table 7: Characteristics …continued

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Product data sheet Rev. 02 — 7 October 2005 15 of 31

Table 7: Characteristics …continued

TDA3683_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.