2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT-2019), MAY 17th &

18th 2019

A brief overview of Test Solution Development for

Semiconductor Testing.
Mahesh Nagaraj
N Sameeksha Rai Namita Palecha
Senior Manager Test Engineering
Student Assistant Profesor
Cypress Semiconductor Technology
Dept. of ECE, RVCE Dept. of ECE, RVCE
India Pvt. Ltd.
Bangalore, India Bangalore, India
Bangalore, India
nsameeksharai.ec15@rvce.edu.in namitapalecha@rvce.edu.in

Abstract— Semiconductor industries perform testing to time-consuming and error-prone process. Traditional testing
ensure good performance of the device under different operating equipment are ineffective in testing integrated circuits (ICs) at
conditions. The time consumed in testing the device by traditional package level. As ICs become more complex, testing such
testing methods using multimeter is considerably high and the circuits also becomes more complex. Such circuits may
results are subject to manual errors. Thus, an automatic test
require hundreds of voltages, current and timing tests. To
equipment (ATE), which is a compact complex circuitry
involving current/voltage forcing and measuring units, is used to ensure complete functionality of complex circuits, millions of
reduce the test time and obtain accurate results. The paper functional steps may require to be performed. Thus,
presents a test solution development for a cable controller Automated Test Equipment (ATE) is used to perform such
generation 3 (CCG3) wafer which is a type-C universal serial bus complex testing. ATE can perform testing both at package
(USB). The first step is development of the test requirements level as well as at wafer level. Simple ATE designs perform
document (TRD). Next, a TRD parser is developed which is a voltage, current, power and resistance measurements.
java-based tool that automatically generates the test program by Complex ATE designs perform boundary scan testing and
using the TRD as an input. Finally, the generated test program is different logic testing. ATE not only performs measurements
validated on an Advantest V93000 tester based on the Smartest8
but also analyses the results to indicate if a device has passed
(SMT8) platform. The TRD parser automatically generates the
complete test program in 3.168s and 100% test coverage is the test or not. The device which is tested is known as Unit
achieved on the V93000 tester for the continuity tests. The paper Under Test (UUT) or Device Under Test (DUT). ATE also
thus covers the entire flow of testing a device under test (DUT) creates a data log of the test measurements and results. ATE
using an ATE at wafer level. also performs stress testing, i.e., tests the DUT’s performance
at different operating conditions (E.g. temperature).
Keywords—Advantest V93000 tester, Automatic Test Equipment
(ATE), Cable Controller Generation 3 (CCG3), Device Under Test Summarizing, ATE is a computer-controlled equipment that is
(DUT), test coverage, Universal Serial Bus (USB). used to test the functionality and performance of electronic
devices with minimal human interference and within the least
I. INTRODUCTION time possible.
The transition towards smaller dimensions and finer Testing is an important part of the semiconductor
geometries has resulted in IC designs becoming more complex manufacturing cycle. All semiconductor devices must be
and expensive. The chipmakers must ensure that the devices tested before release into the market. Testing ensures that the
released into the market are fault free, reliable and meet the device meets all specifications as mentioned in the datasheet
specifications at all operating conditions throughout the life of and guarantees device life time. Untested devices may fail
the device. In case of critical applications such as medical or during use and hence cause loss of credibility to the company
automotive, the reliability of devices becomes more important. along with monetary losses. Testing adds to the device cost as
Failure of devices in such applications may lead to well as impacts the time to market. In a competitive market,
catastrophic results. Hence, chipmakers employ a procedure increased time to market and increased prices are
known as ‘testing’ which is used to assure the quality of the disadvantages. Chipmakers are hence faced with a dilemma –
device. Test engineers perform testing using an Automatic ‘how much testing is required?’. However, the answer to this
Test Equipment (ATE). is not so simple. This is because different applications have
different requirements and hence different metrics to
Traditional testing equipment include multimeter,
determine the effectiveness of the testing process. Cost, test
voltmeter, ammeter, etc. Such equipment is connected across
coverage, test times, number of testers used, etc. are some
the device terminals and necessary measurements are made.
examples of the metrics involved. For companies who
However, once a circuit has been fabricated onto the Printed
manufacture devices in bulk, the key metric is defective parts
Circuit Board (PCB), use of traditional testing equipment
per million (DPPM). Hence chipmakers must boost test
becomes increasingly hard. The connection of such equipment
coverage and reduce test time to meet desired levels of DPPM
to the conductive tracks of the PCB poses a big challenge. In
and must achieve this without adding too much test cost to the
the circuits that are densely packed, accessing individual
overall manufacturing costs. Achieving this balance is of
components and testing them one by one is a cumbersome,
prime importance to semiconductor manufacturers.

978-1-7281-0630-4/19/$31.00 ©2019 IEEE

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 Thus, the primary purpose of the paper is to develop a test
solution to be used at production level using the V93000
tester. The test solution is developed to attain test time
reduction, modular approach to testing and acceptable test
coverage. The V93000 tester is based on the java- based
Smartest8 platform. SmarTest8 features a host of new
capabilities that will enable engineers who must deal with
highly complex test programs to achieve superior parallelism
To be Controller
and throughput. The new software’s benefits include - faster placed
test program development, efficient debug and over DUT

characterization, faster time to market and ease of test-block

reuse.
Fig. 1. A temperature forcing unit
The paper is organised as follows – Section 2 presents the
basic components of an ATE, introduction to continuity test B. Introduction to the continuity test
and the test solution development on the Smartest8 platform. The continuity test is also known as the open-shorts test or
Section 3 presents the results of the project. Section 4 presents contact test. The test is one of the most basic tests performed
the conclusion and future scope of the project. Finally, on a DUT and ensures that during testing, all the DUT signal
references are presented. pins are electrically connected to the tester. The test also
II. DESIGN AND IMPLEMENTATION ensures that no signal pin is shorted to another signal pin or to
the power or ground. Test time reduction demands that bad
The section presents the basic components of the ATE, devices be rejected at the earliest. The continuity test is used
introduction to continuity test and the test solution for the same purpose. A bad device with shorted pins, open
development on the Smartest8 platform. wires, damaged pins and manufacturing defects can be
A. Basic components of an ATE rejected at the initial stages by using continuity test.
Continuity test also detects defects in the test system such as
An ATE is a test system that is a result of merging of a
probe card or test sockets. Defects in the test system prevent
computer system with test instruments. The test instruments
proper electrical contact between the tester and the DUT
are controlled by the computer by executing a set of
which is detected by the continuity test.
instructions called the test program. Test instruments include
forcing and measuring instruments. Consistent test results are
produced by a test system, hence the test actions can be
repeated reliably and quickly. The test systems are periodically
calibrated to verify the accuracy of the test instruments. A
probe card is used to verify correct operation of a die within a
wafer when a wafer level testing is carried out. A load board
or a performance board is an interface circuit board that
connects the instruments in the test system to the probe card.
Once wafer testing is complete, the dies are cut from the
wafer and packaged separately. The packaged dies must be Fig. 2. Continuity test on VDD pin [1].
tested again. The packages circuits are inserted into a device VDD pin is a power supply pin in the CCG3 device.
socket on the loadboard and tested. This is called hand test. An The continuity test on VDD pin is presented in Fig. 2. The
automatic device handler can be used to test the packaged tester forces a specified current on the VDD pin. The voltage
circuits faster. A handler automatically picks an untested clamp should be set to a maximum voltage limit since current
device, place it at the test site and move it to appropriate test is being forced during the test. A short across the VDD diode
bins based on the pass/fail results of the device. Similarly, the implies that the voltage measured across the diode is close to
handler tests all the untested devices and groups them to ground voltage. Thus, a voltage close to zero across the diode
appropriate test bins. Many handlers offer environmental indicates a pin short failure. As indicated by the test limits, a
chambers. The environmental chambers are used to test the voltage less than 0.2V across the diode indicates that the VDD
devices at extreme temperatures. This is called stress testing. pin is shorted by default. Similarly, if the VDD diode is open,
Temperature forcing units are used for stress testing. Fig. 1 then no current can be forced on the VDD pin. Hence, the
depicts a temperature forcing unit. Spring loaded contacts are voltage across the diode starts increasing gradually to sustain
used to provide spring force to maintain positive electrical the required current. The voltage clamps at a value set by the
contact between the tester and the DUT. A pogo pin is an voltage clamp and the device is protected against over voltage.
example of a spring-loaded contact with high durability in Thus, as indicated by the test limits, a high voltage, i.e.,
terms of the number of attach-detach cycles. greater than 1.5V across the diode indicates a pin open failure.
Similarly, all device pins are tested for short or open failure.

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C. Test solution development on Smartest8 platform digital pins since the specifications and levels differ for both
The first step in a test solution development is the the pins.
development of a test requirements document (TRD). The test The Verigy 93k tester or the V93000 tester is developed by
requirements document (TRD) is an excel sheet that contains Advantest. The tester is used to perform high frequency testing
the list of all the tests to be performed on the device. The tests and incorporates parallelism during testing. V93000 supports
are grouped in separate sheets according to the test flow. The digital testing, analog testing, memory testing as well as high
TRD guides the tester regarding which pins are to be tested, voltage testing. Fig. 4 presents the V93000 tester.
what are the currents and voltages to be forced, which relays
need to be turned on and off, what waveform formats are used,
what IPs are used, binning requirements, etc. Fig. 3 presents
the TRD. The TRD is filled up by the test engineer and
represents all the test requirements in the form of an excel
sheet.

Contents of the TRD

Fig. 4. The V93000 tester.

Fig. 3. Contents of the TRD.
The following section presents the results of the project.
A test program must be generated which guides the tester to
perform the testing. The test program must follow a syntax III. RESULTS
which is specific to Smartest8 platform which is supported by The section presents the implementation results of the
the V93000 tester. Testing also requires many files such as the project.
test flow file, the DUT board description file, the relay set file
and so on to be generated. The DUT board descripton file A. The TRD parser
contains information about the DUT pns and their mapping to The time required for the execution of the TRD parser is
the tester channels. Similarly the relay set file contins highlighted in Fig.5. The TRD parser generates all the files
information on the relays that need to be turned on or off and required to perform testing in 3.168s which is much lesser
so on. All the files must be in Smartest8 specific syntax. compared to the time required to generate a test program
However, manual generation of the files has drawbacks. One manually.
drawback is that the user must write a test program for each
test as well as write specific codes for proper level set, timing
set, relay set and DUT board description file. The process is
time consuming when the number of tests to be performed is
large. Also, the method requires that the user knows the
Smartest8 syntax and hence is not user-friendly.
To overcome the drawbacks, a TRD parser tool is
developed. The TRD is a transparent document that contains
the list of tests along with all the parameters required to
perform the test. The TRD can be filled by the user based on
the device datasheet. The TRD parser is a java-based tool that
accepts the TRD as an input. The parser generates the test flow
files in the Smartest8 specific format. The TRD parser tool
considers all the test requirements and generates a test
program which can be loaded on the tester and the tests can be
run. The TRD parser tool operates on the TRD which is an Fig. 5. TRD parser execution.
excel file and extracts each cell information from different
sheets. The extracted information is used to generate a test The offline verification of the test is performed to identify
program in the Smartest8 syntax. Duplicate test names and any setup errors in the test flow. Syntax errors present in the
duplicate test numbers are identified as errors by the TRD test program as well as logical errors in the test methodology
parser. A type check is also implemented in the TRD parser can be debugged during offline verification. However, no
which throws an error message when the user enters wrong actual electrical levels are forced or measured during offline
parameters in the TRD. The TRD parser also identifies errors testing. Fig. 6 presents the results of offline verification of the
in pin grouping, i.e., analog pins cannot be grouped with

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continuity tests and indicated that all the continuity tests have
passed. The output voltages measured for different continuity tests
using the V93000 tester are presented in Table 1. Tester
accuracy and environmental factor affect the measured output
voltage values.

TABLE I. OUTPUT VOLTAGE MEASURED USING V93000 TESTER

V93000 Tester measurements
Nextest Magnum Teste
Test Conducted
measurements (in mV
(in mV)

Pin opens test on

configuration channel pin -484.95 -501
CC2

Pin opens test on auxillary

Fig. 6. Results of offline verification of continuity tests. -628.39 -637
pin AUXP

Online testing of the DUT is the final step in the Pin opens test on external
-551.22 -562
semiconductor testing. The tester has a mother board with reset pin

various pogo pins. The daughter board, which contains the test Pin open shorts test on GPIO
-623.28 -633
socket with the DUT, is mounted or docked on the mother pin P2.4

board of the tester. The tester setup is presented in Fig. 7. Pin open shorts test on
-444.398 -452
supply pin (VDDD)

Pin opens test on gate driver

-502.29 -503
pin VBUS_P_CTRL

Pin opens test on gate driver

-503.62 -504
pin VBUS_C_CTRL

Pin opens test at high voltage

-500.39 -500
pin VBUS_P

Pin open shorts test on

-534.8 -546
supply pin VSYS

Pin open shorts test on input

-505.48 -508
voltage supply pin V5V

IV. CONCLUSION AND FUTURE SCOPE

The development of the TRD helps in a more transparent
testing process. The TRD parser tool developed automatically
Fig. 7. Tester setup. generates the test program and includes built in error check
The DUT is tested in site 2 of the daughter board. Fig. 8 features. Thus, the user need not be aware of the test program
indicates that all the continuity tests have passed successfully. syntax and yet can generate a test program and perform testing
Fig. 9 presents the data log of the tests indicating that all the on any given device. The TRD can be developed for any
continuity tests have passed. device and test program can be generated based on the TRD.
Thus, the development of the TRD parser removes the
restriction that a user must know the SMT8 test program
syntax to perform tests and generates all files required for
testing in a short period of time, i.e., 3.168s. Therefore, the use
of TRD parser is user-friendly, improves reusability and
reduces the time spent in generating test programs manually.
Offline verification of tests is always done before online
verification of tests to ensure that proper level and timing sets
are provided during testing. However, electrical parameter
limits are not verified during offline verification since no
Fig. 8. Continuity tests pass for the DUT at site 2 of the daughter board. electrical levels are forced or measured. Online verification of
the tests is used to verify both functionality as well as
electrical parameter limits and the results are stored in a data
log. Thus, all the continuity tests in the TRD are run for the
CCG3 device and finally, the DUT is binned as a good device.
Hence, 100% test coverage is obtained ith respect to th
continuity tests.
Fig. 9. Continuity tests data log indicating that the tests have passed.

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 Future enhancements include optimisation of existing test
methods and development of new test methods to conduct the
tests, for increased test coverage with reduced test time. Also,
in the future other ATE can be used to conduct testing and the
results may be compared to the V93000 tester. All the future
work is based on achieving one common goal of testing, i.e.,
to reduce test time and test cost without compromising on the
test coverage.
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