Jayawantrao Sawant Polytechnic: Micro Project Report ON

MAHARASHTRA STATE BOARD OF TECHNICAL
EDUCATION, MUMBAI
JAYAWANTRAO SAWANT POLYTECHNIC

MICRO PROJECT REPORT
ON
Project Name : Half Adder
Academic year: 2023-24

Submitted By
1. ISHA KUTE
2. VAIBHAVI HOLE
3. VAISHNAVI KARLE
4. SHANTI RATHOD
5. SHAMIT KARDE
Guided By
Mrs. Ashlesha Kulkarni
DEPARTMENT OF ELECTRONICS AND
TELECOMMUNICATION ENGINEERING
1
MAHARASHTRA STATE
BOARD OF TECHNICAL
EDUCATION
Certificate
This is to certify that Isha kute , Shanti rathod , Vaishnavi karle and Vaibhavi hole,
Shamit Karde. Roll No: 40,66,69,53,33 of Semester third of Diploma in Electronics and
Telecommunication Engineering of Institute, JAYAWANTRAO SAWANT
POLYTECHNIC (Code:0711) has completed the Micro Project satisfactorily in Subject
Electric Circuit Network (22330) for the academic year 2023- 2024 as prescribed in the
curriculum.
Place: Hadapsar. Enrollment No:

2207110561
2207110234
2207110557
2207110525
2207110220
Date: …………… Exam Seat No:
Subject Teacher Head of the Department Principal

2
JAYAWANTRAO SAWANT POLYTECHNIC,
Handewadi Road, Hadapsar, Pune-
28 Academic Year 2023-2024
INDEX
SR.NO. CONTENT PAGE NO.
Brief Description (Introduction) 4

1
4
Aim of Micro Project (Proposed System)
2
4
Course Outcome Integrated (Technology )
3
4. Teacher evalution sheet 7
3
Introduction:
. A half adder is a type of adder, an electronic circuit that
performs the addition of numbers. The half adder is able to add
two single binary digits and provide the output plus a carry
value. It has two inputs, called A and B, and two outputs S
(sum) and C (carry)
Half adder is an adder which adds two binary digits
together, resulting in a sum and a carry. Why is it called a
half adder? Because this adder can only be used to add two binary
digits, it cannot form a part of an adder circuit that can add two n-
bit binary numbers.
Aim of Project :
Add two single binary digits and provide the output plus a carry value.
It has two inputs, called A and B, and two outputs S (sum) and C (carry).
Course Outcome Integrated (Technology ) :

We can conclude that half adders are one of the basic arithmetic
circuits used in different electronic devices to perform addition of two
binary digits. The major drawback of a half adder is that it cannot add
the carry obtained from the addition of the previous stage.
Information About Project :

Block diagram
A half adder is a digital logic circuit that performs binary addition of two
single-bit binary numbers. It has two inputs, A and B, and two outputs, SUM
and CARRY. The SUM output is the least significant bit (LSB) of the result,
while the CARRY output is the most significant bit (MSB) of the result,
indicating whether there was a carry-over from the addition of the two
inputs. The half adder can be implemented using basic gates such as XOR
and AND gates.
Sure, here’s a more in-depth explanation of the half adder circuit:
4
The half adder is a basic building block for more complex adder circuits such
as full adders and multiple-bit adders. It performs binary addition of two
single-bit inputs, A and B, and provides two outputs, SUM and CARRY.
The SUM output is the least significant bit (LSB) of the result, which is the
XOR of the two inputs A and B. The XOR gate implements the addition
operation for binary digits, where a “1” is generated in the SUM output only
when one of the inputs is “1”
The CARRY output is the most significant bit (MSB) of the result, indicating
whether there was a carry-over from the addition of the two inputs. The
CARRY output is the AND of the two inputs A and B. The AND gate generates
a “1” in the CARRY output only when both inputs are “1”.
Half Adder (HA):
Half adder is the simplest of all adder circuits. Half adder is a combinational
arithmetic circuit that adds two numbers and produces a sum bit (s) and
carry bit (c) both as output. The addition of 2 bits is done using a
combination circuit called a Half adder. The input variables are augend and
addend bits and output variables are sum & carry bits. A and B are the two
input bits.
let us consider two input bits A and B, then sum bit (s) is the X-OR of A and
B. it is evident from the function of a half adder that it requires one X-OR
gate and one AND gate for its construction
Truth Table:
Truth Table
In the above table,
1. 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
2. The carry output is 0 in case where both the inputs are not 1.
3. The least significant bit of the sum is defined by the 'sum' bit.
5
Here we perform two operations Sum and Carry, thus we need two K-maps
one for each to derive the expression.
Logical Expression:
For Sum:
Sum = A XOR B
For Carry:
Carry = A AND B
Implementation:
6
Note: Half adder has only two inputs and there is no provision to add
a carry coming from the lower order bits when multi addition is
performed.
Advantages and disadvantages of Half Adder in Digital Logic :

Advantages of Half Adder in Digital Logic :
1.Simplicity: A half viper is a straightforward circuit that requires a

couple of fundamental parts like XOR AND entryways. It is not difficult
to carry out and can be utilized in numerous advanced frameworks.
2.Speed: The half viper works at an extremely rapid, making it

reasonable for use in fast computerized circuits.
Disadvantages of Half Adder in Digital Logic :
1.Limited Usefulness: The half viper can add two single-piece

numbers and produce a total and a convey bit. It can’t perform
expansion of multi-bit numbers, which requires the utilization of
additional intricate circuits like full adders.
2.Lack of Convey Info: The half snake doesn’t have a convey input,
which restricts its value in more mind boggling expansion tasks. A
convey input is important to perform expansion of multi-bit numbers
and to chain numerous adders together.
7
References:
https://www.javatpoint.com/half-adder-in-digital-electronics;
https://www.geeksforgeeks.org/half-adder-in-digital-logic/
https://www.gatevidyalay.com/half-adder/
8
JSPM’s
Handewadi Road, Hadapsar, Pune-28
Department of Electronics and
Telecommunication Engineering
Academic Year 2023-24
Teacher Evaluation Sheet
Name of student: Isha Vikas Kute
Enrollment No: 2207110234
Semester: Third
Course Title: E&TC Code: 22320
Title of Micro Project: Half Adder
Course Outcomes Achieved:
Evaluation as per suggested Rubric for Assessment of Micro Project

Sr. Characteristic to be Poor Average Good Excellent
No assessed (Marks1- 3) (Marks 4-5) (Marks6-8) (Marks 9-10)
1 Relevance to the course
2 Literature Survey /
Information collection
3 Project Proposal
4 Completion of the Target as
per Project Proposal
5 Analysis of data and
representation
6 Quality of Prototype/ Model
7 Report preparation
8 Presentation
9 Defense
9
Micro Project Evaluation Sheet
Process Assessment Product Assessment Total

Marks
Part A - Project Project Part B - Project Individual
Proposal Methodology Report/ working Presentation/ Viva 10
(2 Marks) (2 Marks) Model (4 Marks)
(2 Marks)
Note: Every course teacher is expected to assign marks for group evaluation in first 3
columns and individual evaluation 4th column
Comment/suggestion about team work/leadership/interpersonal communication (If any)

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Any other comment:
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Name and Designation of the Faculty Member:
Signature:
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JSPM’s
Name of student: Vaibhavi Prakash Hole

Semester: Third

3 Project Proposal
representation
8 Presentation
9 Defense

11
Marks
(2 Marks)

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Any other comment:
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Signature:
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JSPM’s

Name of student: Shanti Laxman Rathod
Semester: Third

3 Project Proposal
representation
8 Presentation
9 Defense
13
Marks
(2 Marks)

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Any other comment:
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Signature:
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JSPM’s

Name of student: Shamit Sachin Karde
Semester: Third

3 Project Proposal
representation
8 Presentation
9 Defense
15
Marks
(2 Marks)

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Any other comment:
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Signature:
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JSPM’s

Name of student: Vaishnavi Sanjay Karle
Semester: Third

3 Project Proposal
representation
8 Presentation
9 Defense
17
Marks
(2 Marks)

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Any other comment:
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Signature:
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MAHARASHTRA STATE BOARD OF TECHNICAL

JAYAWANTRAO SAWANT POLYTECHNIC

Academic year: 2023-24

Place: Hadapsar. Enrollment No:

Date: …………… Exam Seat No:

Subject Teacher Head of the Department Principal

SR.NO. CONTENT PAGE NO.

Brief Description (Introduction) 4

Course Outcome Integrated (Technology ) :

Information About Project :

In the above table,

Advantages and disadvantages of Half Adder in Digital Logic :

1.Simplicity: A half viper is a straightforward circuit that requires a

2.Speed: The half viper works at an extremely rapid, making it

Disadvantages of Half Adder in Digital Logic :

1.Limited Usefulness: The half viper can add two single-piece

Course Outcomes Achieved:

Evaluation as per suggested Rubric for Assessment of Micro Project

Process Assessment Product Assessment Total

Comment/suggestion about team work/leadership/interpersonal communication (If any)

Name and Designation of the Faculty Member:

Teacher Evaluation Sheet

Name of student: Vaibhavi Prakash Hole

Evaluation as per suggested Rubric for Assessment of Micro Project

Micro Project Evaluation Sheet

Comment/suggestion about team work/leadership/interpersonal communication (If any)

Name and Designation of the Faculty Member:

Teacher Evaluation Sheet

Evaluation as per suggested Rubric for Assessment of Micro Project

Comment/suggestion about team work/leadership/interpersonal communication (If any)

Name and Designation of the Faculty Member:

Teacher Evaluation Sheet

Evaluation as per suggested Rubric for Assessment of Micro Project

Comment/suggestion about team work/leadership/interpersonal communication (If any)

Name and Designation of the Faculty Member:

Teacher Evaluation Sheet

Evaluation as per suggested Rubric for Assessment of Micro Project

Comment/suggestion about team work/leadership/interpersonal communication (If any)

Name and Designation of the Faculty Member:

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