NANDHA ENGINEERING COLLEGE

(Autonomous Institution)
Erode-638 052

LABORATORY MANUAL
22ECP01- BASICS OF ELECTRONICS ENGINEERING
LABORATORY
I – Semester

B.E – Computer Science and Engineering

Department of Computer Science and Engineering

NANDHA ENGINEERING COLLEGE, ERODE-52

Name : …………………………………………………………………………………

Reg.No : …………………………………………. …… Year : ………………….

Branch : ………………………………………… Semester : …………………

NANDHA ENGINEERING COLLEGE
(Autonomous Institution)
Erode-638 052

BONAFIDE CERTIFICATE

REGISTER NUMBER:

Certified that this is the Bonafide Record of work done

by.………………………………………………….. of the First Semester
B.E./. Computer Science and Engineering branch during the
Academic Year 2024-2025 in the 22ECP01- BASICS OF
ELECTRONICS ENGINEERING LABORATORY

……………………….. ………………………
Staff-in-charge Head of the Department

Submitted for the End Semester Practical ExaminationHeld

on…………………………………………….

……………………….. ……………………..
Internal Examiner External Examiner
 INDEX

Ex. PAGE
No. DATE NAMEOFTHEEXPERIMENTS MARKS SIGN
No.
V-I Characteristics of PN junction diode
and forward and reverse resistance
1.
V-I Characteristics of Zener diode and
Forward and reverse resistance
2.
Input-Output characteristics
Of CommonEmitter Configuration(CE)
3. using BJT
Characteristics of FET and drain and
4. transfer characteristics

V-I Characteristics of UJT

5.
Half wave Rectifier& Full wave Rectifier
6.
Verification Kirchoff’s Voltage Law
7. (KVL), Kirchoff’s Current Law(KCL)

Verification of Thevenin’sTheorem
8.
Verification of Norton’sTheorem
9.
Verification Of logic gates
10.

AVERAGEMARKSAWARDED

CONTENTBEYONDSYLLABUS
Characteristics of Photodiode and phototransistor
Design UJT relaxation Oscillators.

TotalMarks
Total Average Marks (40)
CIRCUITDIAGRAM:
FORWARD BIAS:

REVERSE BIAS:
EX.NO. 1 CHARACTERISTICS OF PN JUNCTION DIODE
DATE:

AIM:
 To determine and plot the V&I characteristics of the PN junction diode

APPARATUSREQUIRED:

S.NO ITEM RANGE QUANTITY

1. Resistor 560Ώ 1
(0-1)V 1
2. DC Voltmeter
(0-10)V 1
3. DC Ammeter (0-100)mA 1
4. PN diode IN4007/1A 1
Regulated Power 1
5. (0-30)V
Supply
6. Bread board 1

THEORY:
 In a piece of semiconductor material one half is doped by the P type impurity and

theother half is doped by N type impurity, a PN junction is formed.

 The N type material has high concentration of free electrons while the p type material

has a high concentration of holes.

 Size and doping concentration of both p type material and n type materials should be

same
MODELGRAPH

TABULATION:

FORWARD BIAS REVERSE BIAS

Voltage(v) Current(mA) Voltage(v) Current(mA)

  Further increase in reverse bias voltage, temperature increases at the junction and avalanche
multiplication process starts.
 At particular voltage, junction breaks down due to avalanche break down process.

PROCEDURE:

 Give the connections as per the circuit diagram in the breadboard.

 Vary the power supply voltage and tabulate the output voltage and current readings.
 Repeat the same Procedure for reverse bias connection of PN junction diode.
 Plot the Forward and reverse Bias readings in the graph.
 Calculate the resistance of the diode at forward bias connection.
 Calculate the Cut-in voltage.
 Calculate the resistance of the diode at reverse bias connection.
 Calculate the reverse Break down voltage of P-N Junction diode.

Maxi Marks
mum Awarded
Marks
Preparation&
Conduct of 50
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:

Thus the VI characteristics of PN junction diode were determined and the graphs were
plotted for its forward and reverse bias.
CIRCUIT DIAGRAM:
FORWARD BIAS:

REVERSE BIAS:
EX.NO.2 CHARACTERISTICS OF ZENER DIODE
DATE:

AIM:
 To draw the V-I characteristic of Zener diode and find the parameter

COMPONENTS REQUIRED:

S.No Components Range Quantity

1 Zener Diode - 1

2 RPS (0-30)V 1

3 Resistor 1KΩ, 1

4 Ammeter (0-50)mA 1

5 Voltmeter (0-1)V 1

6 Breadboard - 1

7 Connecting wires - Few

PROCEDURE:

Forward bias characteristic:

1. The circuit connections are made as per the circuit diagram

2. Keep the RPS connected in a minimum value and switch ON the power supply
gradually increase voltage in step of .1V.
3. Note down the corresponding ammeter and voltmeter readings.

4. Plot the forward V-I curve.

5. Calculate forward resistance Rf=(V/I)
Reverse bias characteristic:

1. Connect the circuit as per the circuit diagram.

2. Keep the RPS connected in a minimum value and switch ON the power supply.

3. Gradually increase voltage in step of.1V.

TABULATION:

FORWARD BIAS:

S.No Forward voltage(V) Forward current I(mA)

REVERSE BIAS:

S.No Reverse voltage (V) Reverse current I (μA)

MODEL GRAPH:
 4. Vary the power supply in step by 1V.
5. Note down corresponding reverse voltage and current.
6. Plot the graph current Vs voltage.
7. Plot the reverse V-I curve.

Maximu Marks
m Awarded
Marks
Preparation&
Conduct of 50
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:
Thus the VI characteristics of Zener diode were determined and the graphs were plotted for its
forward and reverse bias.
EX.NO.3 INPUT – OUTPUT CHARACTERISTICS OF COMMON
DATE: EMITTER CONFIGURATION

AIM:
 To plot the input and output characteristics of a Transistor in CE configuration and also
calculate the H – Parameters

APPARATUS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY

1 Transistor BC107 1

2. Resistor 1kΏ 2

(0-1 mA 1
3. DC Ammeter
(0-10)mA 1

4. Voltmeter (0-30)V 1

5. RPS (0-30)V 1

THEORY:

 The BJT consists of a silicon crystal in which the thin layer of N type silicon in which
sandwiched between two layers of P type silicon this transistor is PNP.
 In NPN transistor is a layer of P type silicon in which sandwiched between two layers
of N type silicon this transistor is NPN.
 The three regions of the transistor are emitter base and collector.
 Emitter is highly doped. In CE configuration input is applied between base and
emitter.
 Output is taken from the collector and emitter. Here emitter terminal is common to
both input and output circuit.
 The ratio of change in collector current to the change in base current is known as base
current

∆IB
The amplification factor is β= ---------- = hfe (Forward current gain)
∆Ic
Where β is the current gain for CE configuration of a transistor.
TABULATION:
INPUT CHARACTERISTICS:
VCE -------------- V VCE -------------- V
VBE(V) IB(mA) VBE(V) IB(mA)

OUTPUT CHARACTERISTICS:
IB ---------- (mA) IB -------- (mA)
VCE(V) IC(mA) VCE(V) IC(mA)
INPUT CHARACTERISTICS:

 It is curve between base current IBand base emitter voltage VBEat constant collector
emitter voltage VCE. When VCE= 0 voltage the emitter – base junction is forward
biased and the junction behaves like a forward biased diode hence the input
characteristic for VCE =0 voltage is similar to that of a forward biased diode.

 When Vce increased the width of the depletion layer at the reverse biased collector
junction will increase. Hence the effective width of the base will decrease.

 This effect causes a decrease in the basecurrentIB. Hence to get the same value of IBas
that of VCE= o voltage Vbe should be increased.

 Therefore the curve shifts to right as Vce increases.

 Input resistance of CE is higher than of CB circuit.

∆VBE
RI= ----------- =hie
∆IB

Input resistance is of the order of few hundred.

OUTPUT CHARACTERISTICS

• To determine the output characteristics, the base current Ib is kept constant at a suitable value
by adjusting base emitter voltage.

• The magnitude of collector emitter voltage VCEis increased in suitable equal steps from zero
and the collector current ICis noted for eachsetting VCE.

• Now the curves of ICverses Vce are plotted for different constant values of Ib.

• Output Admittance is defined as the ratio of change in the output collector current to the
corresponding change in the output collector voltage with the base current Ib kept constant.
 ∆IC
hoe =--------
∆VCE

 Reverse voltage gain is defined as the ratio of change in the input base voltage and the
corresponding change in output collector voltage with constant input base current.
∆VBE
Hre= ----------
∆VCE

PROCEDURE:
• Give the connections as per the circuit diagram in the bread board.

• To measure the input characteristics, keep the output voltage (VCE) is constant, vary
the input voltage (VBE) and note the input current (IB).
• Repeat the above procedure for various output constant voltages.

• To measure the output characteristics, keep the input current (IB) is constant, vary
the output voltage (VCE) and note the output current (IC).

• Repeat the above procedure for various input constant currents.

Plot the input and output characteristics.

• Calculate the input impedance (hie) from input curve & output admittance (hoe)and reverse
voltage gain (hre) from output characteristics.
• Verify the final results with the data sheet given to that particular transistor.
CALCULATION :
 Maximu Marks
m Awarded
Marks
Preparation
& 50
Conductof
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:
Thus the characteristics of common emitter configuration were determined and
H –parameters were calculated.

Input impedance of the transistor hie= ---------

Output admittance of a transistor hoe = ---------
Forward current gain hfe =---------
Reverse voltage gain hre =----------
CIRCUITDIAGRAM:
EX.NO.4 CHARACTERISTICS OF FET
DATE:

AIM:
To determine the drain and transfer characteristics of Field Effect Transistor (FET).

APPARATUSREQUIRED:

S.NO ITEM RANGE QUANTITY

1. Resistor 1kΏ 1

2. DCAmmeter (0-100)mA 1

3. DCVoltmeter (0-30)v,(0-10)v 1

4. FET BFW-10 1

5. RPS (0-30)v,(0-5)v 1each

6. Breadboard - 1
THEORY:
 FET consists of a N–type bar made of silicon, ohmic contents are made on two ends of
the bar called source and drain.

 Source is connected to negative terminal of battery, electrons which are majority carriers
in the N–type bar, enters the bar through this terminal.

 Gate is heavily doped P–type silicon bar, which is diffused on both sides of N–type
silicon bar by which PN junction is formed.

 These layers are joined together called gate.

 FET is basically a voltage controlled device. Input voltage is controlling the output
current. When the voltage is applied between source and drain a constant amount of
drain current flow is takes place.
 When the input reverse bias voltage applied betweengate and source the P-N junction
grows inside the N channel. Due to this channel width is modified and the amount of
drain current is changed.
 Further increase in Vgs both the P-N junction grows further and correspondingly
channel width is decreased.
 At one particular voltage both the junctions are touching each other.
 At that voltage a constant amount of current flow is taking place.
 This voltage is called pinch off voltage. Then the output current is constant even there is
an increase in Vds.
MODELGRAPH:
DRAINCHARACTERISTICS: TRANSFERCHARACTERISTICS:

TABULATION:
DRAINCHARACTERISTICS: TRANSFERCHARACTERISTICS:
VGS= (V) VGS= (V) VDS= (V) VDS= (V)
VDS
ID (v) VDS (v) ID(mA) VGS (v) ID (v) VGS (v) ID(mA)
(v)
  Input impedance of the FET is more than BJT and there is no minority current flow so that
it is less noise. It is operating based on voltage control, so if any small changes in theinput
will not reflect on the output. So it is less sensitivity than BJT. It is normally used as an
amplifier and switching device.

PROCEDURE:

DRAINCHARACTERISTICS:

 Give the connections as per the circuit diagram in the breadboard.

 Keep the Gate to Source voltage VGS constant and by varying VDS in steps, then tabulate
the corresponding Drain current ID
 Repeat the same steps for different values of VGS.
 Calculate the pinch off voltage.

TRANSFERCHARACTERISTICS:

 Give the connections as per the circuit diagram in the bread board.
 Keep the drain to Source voltage VDS constant and by varying Gate to Source voltage, VGS in steps,
note and tabulate the corresponding Drain current ID
 Repeat the above steps for different values VDS.

Maxim Marks
um Awarded
Mark
s
Preparation&
Conduct of 50
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:

Thus the drain transfer characteristics of FET was determined and the graph was plotted pinch off
voltage is determined and verified
 CIRCUITDIAGRAM:

SYMBOL:

BASE2(B2
BASE2(B2)

EMITTER(E)

EMITTER(E)
2N26-46

BASE1(B1)
EX.NO:5 CHARACTERISTICS OF UJT
DATE:
AIM:
 To construct and determine the characteristics curve of Uni Junction Transistor (UJT)

APPARATUS REQUIRED:

S.NO EQUIPMENTS RANGE QUANTITY

1 Regulated PowerSupply(RPS) (0-30)V 2
2 D.Cammeter (0-100)mA 1
3 D.CVoltmeter (0-10)V 1
4 D.CVoltmeter (0-30)V 1
5 Resistor 1KΩ 2
6 UJT(2N26-46) 2N26-46 1

THEORY:

 A unijunction transistor (abbreviated as UJT) is a three terminal semiconductor

switching device. It is used in switching circuits requiring rapid discharge of a

capacitor.Fig.(2) shows the structure of UJT.

 It consists of a lightly doped N-type silicon bar with a heavily doped P-type material

alloyed to its one side for producing single P-N junction.

 At the ends of silicon bar electrical connections are made. The leads at these

connections are called as base1(B1)andbase2(B2).

 The terminal brought out from P-type material is called emitter (E). Fig.(3) shows the

symbolic representation of UJT. In symbolic representatio n, the arrow in the emitter

points in the direction of forward current through the junction and inclined towards B1

terminal.

 The characteristics curve of UJT at different voltage between base is shown in Fig

(4). Initially when VEB1< η VB1B2 + VB (where VB-barrier voltage of P-N junction, η(=VA /

VB )- intrinsic standoff ratio, where VA–voltage drop between Emitter terminal and

base1terminal).The emitter junction is reverse biased resulting in a small reverse emitter

current.
CHARACTERISTICSCURVEOFUJT:

TABULATION

VB1B2=5volts VB1B2=10volts VB1B2=15volts

VBE1(V) IE(mA) VBE1(V) IE(mA) VBE1(V) IE(mA)

  However, if VEB1> η VB1B2+VB, the emitter junction gets forward biased and emitter current
flows. The current increases until the peak voltage Vp and peak current Ipare reached at point
P. Now holes are injected into N-region, which are repelled by base2 (B2) while they are
attached by base1 (B1).

 These holes increase the conductivity of the region between emitter (E) and base B1.Thus
voltage VEB1drops. This drop in voltage between the junction point and B1 further more
heavily forward biases the junction thereby further increasing the current.This process
continues until valley point is reached.

 At valley point, the current is increased to such an extent that no further increase in
conductivity can take place. Beyond valley point, the device behaves as a conventional
forward biased P-N junction diode. Between the peak point (P) and valley point on the
characteristics, the UJT exhibits a dynamic negative resistance.

PROCEDURE:
 Circuit connections are given as per the circuit diagram.
 The voltage VB1B2is first kept at constant value say 5V.
 The voltage VEB1is varied in steps and corresponding current IEis noted.
 The voltage VB1B2 is varied in steps of 5volts and the step-2 is repeated.The readings are
tabulated and the graph is drawn.

Maxim Marks
um Awarded
Marks
Preparation&
Conduct of 50
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:

Thus, the characteristics of UJT is determined and verified.

CIRCUITDIAGRAM:

HalfWave Rectifier:

Full WaveRectifier:

TABULATION
WithoutFilter WithFilter
Rectifier T(mS)
Vm(V) T(mS) Vm(V)
Charging Discharging
HalfWave
Rectifier
FullWave
Rectifier
EX.NO:6 HALF WAVE AND FULL WAVE RECTIFIER
DATE:

AIM:
To obtain the output of Half wave and Full Wave rectifier and to plot the characteristics.

APPARATUSREQUIRED:
S.N NAMEOFTHE TYPE RANGE QUANTIT
O EQUIPMENT Y

1 Diode
IN4001 - 2
2 Resistor - 1KΩ 1
3 Capacitor - 100μF 1
230V/(12–
Transformer Step-
4 0–12)V 1
down
5 CRO Analog 30MHz 1

6 BreadBoard - - 1
7 Connectingwires - - AsRequired

THEORY:

 Half wave rectifier converts alternating voltage into unidirectional pulsating voltage.
The half wave rectifier circuit using a diode with a load resistance R.
 The diode is connected in series with the secondary of the transformer and the load
resistance R, the primary of the transformer is being connected to the supply mains.
 The AC voltage across the secondary winding changes polarities after every half
cycle.
 During the positive half cycles of the input AC voltage i.e. when upper end of the
secondary winding is positive with respect to its lower end, the diode is forward
biased and therefore current conducts.
 During the negative half cycles of the input AC voltage i.e. when lower end of the
secondary winding is positive with respect to its upper end, the diode is reverse biased
and doesnot conduct.
 Thus for the negative half cycles no power is delivered to the load. Since only one
half cycles of the input wave is converted as output, it is called as Half WaveRectifier.
  In FullWave Rectifier thediode D1 will conduct during the positive half ofthe input
signal and during the negative half cycle of the input signal the diode D2 conducts.
Hence both the half cycles are converted into output and the efficiency is high
compared with the half wave rectifier.

PROCEDURE:

1. Circuit connections were given as per the circuit diagram.

2. Input wave form’s magnitude and frequency was measured with the help of CRO.
3. Supply is switched ON and the output wave form was obtained in the CRO.
4. Output wave form’s magnitude and time period was measured.
5. Graphs were plotted for Half wave and Full wave rectifier outputs.

Maximu Marks
m Awarded
Marks
Preparation&
Conduct of 50
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:
The output of half wave and full wave rectifier is verified and plotted the characteristics of the
rectifier which is determined and verified.
VERIFICATIONOFKCL

CIRCUIT DIAGRAM:

TOPROVE I=I1+I2

THEORETICAL PROOF:

V=5V

R=

=6.367 KΩ

I = =

=0.785mA

I1= =0.6024mA

I2= = 0.1826mA
EX.NO.7
VERIFICATION OF KCL AND KVL
DATE:

AIM:
To verify Kirchoff’s Current law and voltage law for the given electrical network

APPARATUSREQUIRED:

S.No. Components Range Quantity

1 Resistor 5.6KΩ 1

2 Resistor 1KΩ 2

3 Resistor 3.3KΩ 1

4 Resistor 2.7KΩ 1

5 Resistor 1.5KΩ 1

6 RegulatedPowerSupply (0–30)V 1

7 Ammeter (0–1)mA 3

8 Voltmeter (0-10)V 1

9 Breadboard - 1

10 ConnectingWires - Required
TABULATIONFORKCL

VOLTAGE(V) I (mA) I1(mA) I2(mA) I=I1+I2

Theoretical
5.0 0.785 0.60 0.1826 0.7850
Value
Practical
Value
THEORY:

Kirchoff’s Current Law (KCL) deals with the currents flowing into and out of a given node. KCL
states that the sum of all currents at a node must equal zero.

Theequation obtained by KCL for the node0.

Or
I1=I2+I3

In the case of KCL the passive sign convention deals with the direction of currents with respect to
the node. Currents entering the node must have opposite signs as thoseexiting the node. The
passive sign convention with respect to KVL can also be applied to KCL. On many schematics the
polarities of resistors are already assigned, so the directions of the currents should be assigned such
that the current is entering the positive terminal.
VERIFICATION OF KVL

CIRCUIT DIAGRAM:

TO PROVE

V=V1+V2+V3

THEORETICAL PROOF:

V =5V

R =R1+R2+R3

=5.2KΩ

I=

=
=0.961mA

V1 =I =2.596V
V2 =I =0.961V
V3 =I =1.442V
THEORY:

 Kirchoff’s Voltage Law (KVL) states that the sum of all voltages in a closed
loopmustbezero.Aclosedloopisapathinacircuitthatdoesn’tcontainanyotherclosedloops.
Loops 1 and 2 in Figure 1 are examples of closed loops.

 The perimeter of the circuit is also a closed loop, but since it includes loops 1 and 2 it
would be repetitive to include a KVL equation for it.
 If loop1 is followed clockwise the KVL equation is

 This equation holds true only if the passive sign convention is satisfied.
 In the case of KVL the passive sign convention states that when a positive node is
encountered while following a loop the voltage across the element is positive.
 If a negative node is encountered the corresponding element voltage is negative.
 In order to simplify the KVL equations, the polarities should be assigned to satisfy the
passive sign convention whenever possible.
TABULATION FOR KVL:

VOLTAG
V1(V) V2(V) V3(V) V=V1+V2+V3
E (V)
Theoretical
5.0 2.596 0.961 1.44 4.9
Value
Practical
Value
PROCEDURE:

1. Give the connections as per the circuit diagram in the bread board.
2. Switch ON the power supply and set the input voltage to particular level.
3. Observe the readings of various meters and note down the values.
4. Same steps are repeated for various voltage and the corresponding readings are tabulated.
5. The validity of the laws is verified with the tabulated readings.

Maximu Marks
m Awarded
Marks
Preparation
& 50
Conductof
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:

Thus, the KCL and KVL was verified and the values are tabulated as follows are

KCL: THEORETICAL VALUE :

PRACTICAL VALUE :

KVL: THEORETICAL VALUE :

PRACTICAL VALUE:
 CIRCUIT DIAGRAM: (EXPERIMENTALSETUP)

Vin=20V

∆ = =21.36

∆2 = =20

I2 = =0.936mA

DETERMINATION OF TOTAL RESISTANCERAB

EX.NO.8 VERIFICATION OF THEVENIN’S THEOREM
DATE:

AIM:

To verify Thevenin’s theorem for the given circuit and calculate current flowing
through the load Resistor

APPARATUSREQUIRED:

S.No. Components Range Quantity

1 Resistor 3.3KΩ 1

2 Resistor 2.7KΩ 1

3 Resistor 1KΩ 1

4 Resistor 1.5KΩ 1

5 RegulatedPowerSupply (0–30)V 1

6 Ammeter (0–1)mA 1

7 voltmeter (0-10)V 1

8 Breadboard - Required

THEORY:

 This theorem was first formulated for resistive network and later it was enunciatedfor
all type of loads. It may be stated as follows:

 Any two terminal networks consisting of resistance and generators may be replaced
by e.m.f acting in series with resistance.

 The e.m.f is the open circuited voltage at the terminals, and the resistance is the
resistance viewed at the terminals when all the generators in the network have been
replaced by resistances equal to their internal resistances.

 Consider a general network consisting of generators and resistance shown in Figure

5.1 (a). RL is the load resistance connected across terminals A and B.

 According to Thevenin’s theorem this network can be replaced by an e.m.f VOCin

series with resistance RABas shown in Figure 5.1 (b).
ZAB = +2.7

=3.47K Ω

OPENCIRCUITVOLTAGE(Voc)

Voltage across the terminal AB (i.e) 1KΩ is VOC.The current flowing through 1KΩ is I.
Consider V= 20v

20 =
I =4.65mA

VOC.=IR=4.65 X3
=4.65V

TABULATION:

Theoretical
PracticalValue
Value

vin(V) 20.0

THEVENIN’S
VOC(v) 4.65
THEOREM

IL(mA) 0.936
Figure5.1(a) Figure5.1(b)

 VOCis the open circuited voltage, that is, it is the voltage measured at the terminals A andB
with load RL removed. While RABis the resistance viewed at the terminals when all the
generators in the network have been replaced by resistances equal to their internal
resistance.
 Thatis, RAB is simply the resistance looking in to the terminals A and B with load RL
removed with of course all generator replaced by their internal resistances.
 The only restriction imposed on this theorem is that the network is not magnetically coupled
to external circuits.
THEVENIN’S EQUIVALENT CIRCUIT

THEVENIN’S EQUIVALENT CIRCUIT (PracticalCircuit)

THEORETICALPROOF:

4.65 = (3.47 + 1.5)

ILIL

= 0.936m A
PROCEDURE:

 Give the connections as per the circuit diagram in the bread board.
 Switch ON the power supply and set the particular voltages mentioned in the circuit
diagram.
 Note down the current through the load resistor.
 Open the load terminal after removing the load resistor and measure the voltage at the output
terminal using voltmeter.
 Calculate the Thevenin’s equivalent resistance after replacing the entire source by their
internal resistance.
 Draw theThevenin’s equivalent circuit using calculated Vth and RAB.
 Compare the values with the theoretical one and tabulate it.

Maximu Marks
m Awarded
Marks
Preparation
& 50
Conductof
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:

Thus Thevenin’s theorem was verified and the values were tabulated.

Theoretical value : mA

Practical Value : mA
CIRCUIT DIAGRAM:

(EXPERIMENTAL SETUP)

TO FIND IL:

Δ =

= 10.122

Δ3 =

=14.4

I3 =
=1.423mA
EX.NO.9 VERIFICATION OF NORTON’S THEOREM
DATE:

AIM:
To verify Norton’s Theorem for the given circuit and calculate current flowing through
RL Resistor

APPARATUSREQUIRED:

S.No. Components Range Quantity

1 Resistor 1KΩ 3

2 Resistor 1.2KΩ 2

3 Regulated Power Supply (0–30)V 1

4 Breadboard 1

5 Ammeter (0-10)mA 1

6 ConnectingWires - Required
To FIND Isc:

TO FIND Rth:

NORTON’S EQUIVALENT CIRCUIT

THEORY:

 This theorem was formulated by E.I. Norton of the Bell Telephone Laboratories and
can be stated as follows:

 Any two terminal linear networks consisting of generators and resistances can be
replaced with an equivalent circuit consisting of current source ISC in parallel with
resistance RAB.

 The ISC is the short circuit current between the terminals of the network and RAB is the
resistance measured between the terminals with all energy sources replaced bytheir
internal resistances.

 Consider a general network consisting of generators and linear resistance shown in

figure 4.1 (a). RLis the load resistance connected across terminals A and B.

 According to Norton’s Theorem this network can be replacedby a constant current

source ISC in parallel withresistance RABas shown in figure 4.1(b).

Figure4.1(a) Figure4.1(b)

 ISC will be the current flowing through the terminal A and B with load RL removed and AB
shorted , while RABwill be the impedance looking into the terminals A and B with load
RLremoved.
DETERMINATION OF SHORT CIRCUIT CURRENT (ISC)

(ISC)= I2

Δ= =3.4

Δ2= =12

I2= =3.53mA

IL =ISCXRAB/RAB+RL =1.424mA

NORTON’S EQUIVALENT CIRCUIT (practical circuit)

Convert current source in to voltage source. To determine voltage value Use

ohm’s law.
V =I R

=3.53 0.676

=2.39V
THEORETICALPROOF:

ConsidertheLoop

2.39 =680IL+1000ILIL=

1.4 mA

PROCEDURE:

 Give the connections as per the circuit diagram in the breadboard.

 Switch ON the power supply and set the particular voltages mentioned in the circuit diagram.

 Note down the current through the load resistor.

 Short the load terminal after removing the load resistor and measure the current at the output

terminal using ammeter.

 Calculate the Thevenin’s equivalent resistance after replacing the entire source bytheir

internal resistance.

 Draw the Norton’s equivalent circuit using calculated ISC and ZAB.

 Compare the values with the theoretical one and tabulate it.
TABULATION :

S.NO Theoretical Value PracticalValue

INPUT VOLTAGE V(v) 10.0

LOAD CURRENT IN ISC(mA) 3.53

mA
IL(mA) 0.978

SHORT CIRCUIT V(v) 2.39

CURRENT IN mA

IL(mA) 2.4
 Maximu Marks
m Awarded
Marks
Preparation
& 50
Conductof
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:

Thus Norton’s theorem was verified and the values were tabulated.

Theoreticalvalue : mA

PracticalValue : mA
EX NO: 10 VERFICATION OF LOGIC GATES
DATE:

AIM:

To verify the truth table of basic logic gates of AND,OR,NOT, NAND,NOR,EX-OR gates.

APPARATUSREQUIRED:

S.No Nameofthe Apparatus Range Quantity

1. DigitalICtrainerkit 1

2. ANDgate IC7408 1

3. ORgate IC7432 1

4. NOTgate IC7404 1

5. NANDgate IC7400 1

6. NORgate IC7402 1

7. EX-ORgate IC7486 1

8. Connectingwires As required

THEORY:

a. ANDgate:

An AND gate is the physical realization of logical multiplication operation .It is an electronic
circuit which generates an output signal of ‘1’ only if all the input signals are ‘1’.

b. ORgate:

An OR gate is the physical realization of the logical addition operation. It is an electronic

circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.
 c. NOT gate:

A NOT gate is the physical realization of the complementation operation. It is an electronic circuit
which generates an output signal which is the reverse of the input signal. A NOT gate is also
known as an inverter because it inverts the input.

d. NANDgate:

A NAND gate is a complemented AND gate. The output of the NAND gate will be ‘0’ ifall the
input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.

e. NORgate:

A NOR gate is a complemented OR gate.The output of the OR gate will be‘1’if all the inputs are
‘0’ and will be ‘0’ if any one of the input signal is ‘1’.

f. EX-ORgate:

An Ex-OR gate performs the following Boolean function,

A B=(A.B’)+(A’.B)

It is similar to OR gate but excludes the combination of both A and B being equal to one.
TheexclusiveORisafunctionthatgiveanoutputsignal‘0’whenthetwoinputsignalsare equal either ‘0’
or ‘1’.

PROCEDURE:

1. Connections are given as per the circuit diagram

Th

2. For all the ICs 7 pin is grounded and14th pin is given +5V supply.

3. Apply the inputs and verify the truth table for all gates.
 Maximu Marks
m Awarded
Marks
Preparation&
Conduct of 50
Experiments
Observation&
30
Results
Record 10
Viva voce 10
Total 100

RESULT:

The logic gates are determined and verified.

 CHARACTERISTICSOFPHOTODIODEANDPHOTOTRANSISTOR

CIRCUITDIAGRAM

V-I Characteristics:

Vce(V) Ic(mA)

MODELGRAPH:
 CONTENT BEYOND THE SYLLABUS

EX NO: 1
CHARACTERISTICS OF PHOTO DIODE AND
DATE PHOTO TRANSISTOR

AIM:
 To obtain the V-I characteristics of the given phototransistor and photodiode

APPARATUSREQUIRED:

S.NO. APPARATUS RANGE QUANTITY

1 RPS (0-30)V 2
2 Ammeter (0-100)mA 1
3 (0-30)V 1
Voltmeter (0-10)V 1
4 1K 2
Resistor 10K 1

5 MOSFET IRF840 1
6 Breadboard ---- 1
7 ConnectingWires ---- Few

THEORY:
 The photo transistor is a 3 terminal device which gives an electrical current as output if an input
light excitation is provided. Itworks inreverse bias. When reverse biased along with the reverse
bias current ICO, the light current IL is also added to the total output current.
 The amount of current flow depends on the input light intensity given as excitation.
Phototransistor is basically a photodiode with amplification and operates by exposing its base
region to the light source.
 Phototransistor light sensors operate the sameas photodiodes except that they can provide current
gain and are much more sensitive than the photodiode with currents are 50 - 100 times greater
than that of the standard photodiode.
 Phototransistors consist mainly of bipolar NPN transistor with the collector-base PN-junction
reverse- biased. The phototransistor’s large base region is left electrically unconnected and uses
photons of light to generate a base current which in turn causes a collector to emitter current to
flow

PROCEDURE:

 Connectthecircuitasperthecircuitdiagram.

 Keep the input light excitation fixed. Then vary the Vce in steps of 1V till the maximum voltage
rating of the transistor is reached and then note down the corresponding values of Ic.

 Tabulate the readings. For various values of input excitation record the values of Vce and Ic and
plot the characteristics of the photo transistor.
DIAGRAM:

PHOTODIODE Distance-constant,VL-Constant

S.No VD(V) IR(mA)

PHOTODIODE

• A silicon photo diode is a solid state light detector that consists of a shallow
diffused P-N junction with connections provided to the outside world. When the
top surface is illuminated, photons of light penetrate into the silicon to a depth
determined by the photon energy and are absorbed by the silicon generating
electron-hole pairs.
• It is formed by the voltage potential that exists at the P-N junction.
• Those light generated carriers that wander into contact with this field are swept
across the junction.
• If an external connection is made to both sides of the junction a photo induced
current will flow as long as light falls upon the photodiode. In addition to the
photocurrent, a voltage is produced across the diode. In effect, the photodiode
functions exactly like a solar cell by generating a current and voltage when
exposed to light.

PROCEDURE:
• Connect circuit as shown in figure
• Maintain a known distance between the bulb and photo diode is 5cm
• Set the voltage of the bulb, vary the voltage of the diode in steps of 1volt and
note down the diode current Ir.
• Repeat above procedure for.VL=4V,6V,etc Plot the graph:Vd vs Ir for constantVL

Maximum Marks
Components
Marks Awarded
Preparation&
Conduct of 50
Experiments
Observation&
30
Results
Record 10
Vivavoce 10
Total 100

RESULT:

Thus the V-I characteristics of the given photo transistor and photo diode were plotted
 CHARACTERISTICS OF UNIJUNCTION RELAXATION TRANSISTOR

CIRCUIT DIAGRAM:

PINDIAGRAM:

BOTTOM VIEW OF 2N2646:

SPECIFICATION FOR 2N2646:

Inter base resistance RBB=4.7to9.1KΩ

Minimum Valley current = 4 mA

Maximun Peak point emitter current 5μA

Maximum emitter reverse current 12 μA

 CONTENT BEYOND SYLLABUS

EX NO: 2 CHARACTERISTICS OF UNIJUNCTION

RELAXATION TRANSISTOR
DATE

AIM:

To construct a UJT relaxation oscillator and plot the waveform

APPARATUSREQUIRED:

S.NO APPARATUS RANGE QUANTITY

1 RPS (0-30)V 2
2 Ammeter (0-100)mA 1

3 (0-30)V 1
Voltmeter (0-10)V 1
4 1K 2
Resistor 10K 1
5 UJT 2N2646 1
6 Breadboard ---- 1
7 ---- Few
ConnectingWires

THEORY:

 UJT is a unipolar device. It is constructed using an N type silicon bar on which a

P type silicon material is doped. It has three terminals namely base1 (B1), base2
(B2) and emitter (E). The RC circuit associated with UJT will function as a
relaxation oscillator.Once the power supply is switched ON, Capacitor C charges
through R towards VBB.

 Then the voltage across the capacitor reachesVp (= ηVBB+ Vd), where η = 0.63,
Vd = 0.7VUJT turns ON and it enters a negative resistance region. The capacitor
rapidly discharges through UJT, since it then offers very low resistance. This
sudden discharge develops a sharp pulse at B1. When the capacitor voltage
reaches valley voltage (Vv) of UJT it turns OFF. This enables the capacitor to
charge again and repeat the cycle.
Waveform
 PROCEDURE:

• Give the circuit connections as per the circuit diagram.

• The dc input voltage is set to 20VinRPS.

• The output sweep wave for measured using CRO.

• The graph of output sweep wave form is plotted

Maximum Marks
Components
Marks Awarded

Preparation &
Conduct of 50
Experiments

Observation &
30
Results

Record 10
Viva voce 10
Total 100

RESULT:

Thus the characteristics of unijunction relaxation transistor were

plotted.