Power PMAC MACRO User Manual

^1 USER MANUAL
^2 Power PMAC MACRO

^2
^3 Power PMAC MACRO Software Setup

^4
^5February 5, 2014
Single Source Machine Control Power // Flexibility // Ease of Use

21314 Lassen Street, Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 //
www.deltatau.com
Power PMAC MACRO User Manual
Copyright Information
© 2012 Delta Tau Data Systems, Inc. All rights reserved.
This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are
unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained in this
manual may be updated from time-to-time due to product improvements, etc., and may not conform in
every respect to former issues.
To report errors or inconsistencies, call or email:
Delta Tau Data Systems, Inc. Technical Support
Phone: (818) 717-5656
Fax: (818) 998-7807
Email: support@deltatau.com
Website: http://www.deltatau.com
Operating Conditions
All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain static
sensitive components that can be damaged by incorrect handling. When installing or handling Delta Tau
Data Systems, Inc. products, avoid contact with highly insulated materials. Only qualified personnel
should be allowed to handle this equipment.
In the case of industrial applications, we expect our products to be protected from hazardous or
conductive materials and/or environments that could cause harm to the controller by damaging
components or causing electrical shorts. When our products are used in an industrial environment, install
them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive
moisture, abnormal ambient temperatures, and conductive materials. If Delta Tau Data Systems, Inc.
products are directly exposed to hazardous or conductive materials and/or environments, we cannot
guarantee their operation.
A Warning identifies hazards that could result in personal injury

or death. It precedes the discussion of interest.
WARNING
A Caution identifies hazards that could result in equipment damage. It

precedes the discussion of interest.
Caution
A Note identifies information critical to the user’s understanding or

use of the equipment. It follows the discussion of interest.
Note
REVISION HISTORY
REV. DESCRIPTION DATE CHG APPVD
0 Manual Creation 12/21/2012 DCDP SS
1 Corrected mistakes in Gate2 Clock Example 10/16/13 DCDP SM
Added new MACRO commands to Quick
2 1/15/14 DCDP EL
Reference
Table of Contents
INTRODUCTION......................................................................................................................... 1
CONFIGURING GATE3 MACRO WITH POWER PMAC ................................................... 2
Clock Signals .................................................................................................................................. 2
Phase and Servo Clock Direction .............................................................................................. 2
Phase Clock Frequency.............................................................................................................. 2
Servo Clock Frequency .............................................................................................................. 3
Hardware Clock Frequencies .................................................................................................... 4
Example Clock Settings .............................................................................................................. 4
MACRO Communication Registers ............................................................................................... 5
Nodes and Addressing ................................................................................................................ 5
Input Registers ........................................................................................................................... 6
Output Registers ......................................................................................................................... 6
Data Organization within Servo Nodes ..................................................................................... 7
MACRO Communication Setup Instructions ................................................................................. 9
Enabling MACRO Nodes ........................................................................................................... 9
Configuring MACRO Modes .................................................................................................... 11
MACRO Error Testing Variables ............................................................................................ 14
Example MACRO Communication Setup................................................................................. 14
CONFIGURING GATE2 MACRO WITH POWER PMAC ................................................. 15
Clock Signals ................................................................................................................................ 15
Gate2[i].PwmPeriod: MaxPhase Clock Frequency Control ................................................... 15
Gate2[i].PhaseClockDiv: Phase Clock Frequency Control .................................................... 15
Gate2[i].ServoClockDiv: Servo Clock Frequency Control ..................................................... 16
Sys.ServoPeriod ....................................................................................................................... 16
Sys.PhaseOverServoPeriod...................................................................................................... 16
Example Clock Settings ............................................................................................................ 16
MACRO Communication Registers ............................................................................................. 17
Nodes and Addressing .............................................................................................................. 17
Data Organization within Servo Nodes ................................................................................... 19
MACRO Communication Setup Instructions ............................................................................... 21
Enabling MACRO Nodes ......................................................................................................... 21
Configuring MACRO Modes .................................................................................................... 22
MACRO Error Testing Variables ............................................................................................ 24
Example MACRO Communication Setup................................................................................. 24
POWER PMAC MACRO COMMANDS ................................................................................ 25
Online MACRO Commands Quick Reference ............................................................................. 25
Examples of Commands Using Symbolic Variables ................................................................ 30
Supported Power PMAC MACRO Registers ............................................................................... 31
1
INTRODUCTION
This is the User Manual for the software setup of all Power PMAC MACRO Ring Controllers. It is
divided into two sections, Gate2 and Gate3.
The following Power PMAC Ring Controllers use Gate3 technology:

 Power UMAC with ACC-5E3
 Power PMAC EtherLite
The following Power PMAC Ring Controllers use Gate2 technology:

 Power UMAC with ACC-5E
Introduction 1
CONFIGURING GATE3 MACRO WITH POWER PMAC

Clock Signals
Phase and Servo Clock Direction

In a Power PMAC UMAC system, only one machine interface IC, such as the IC in ACC-5E3, is the
source of phase and servo clock signals for the entire system. This IC generates its own phase and servo
clock signals and outputs them to the rest of the system over the UBUS backplane. The Power PMAC
CPU uses these signals as interrupts to drive its phase-commutation and servo-loop algorithms,
respectively. Other machine interface ICs use these clock signals to drive their own input and output
functions.
Upon reinitialization of a Power PMAC UMAC system (by means of the $$$*** command most
typically), the CPU will automatically set up the lowest-numbered DSPGATE3 IC found as the source of
the system clock signals. It does this by setting Gate3[i].PhaseServoDir for this IC to 0, indicating that
this IC is the clock source. It sets Gate3[i].PhaseServoDir for all of the other ICs it finds to 3, so that
they will receive their phase and servo clock signals from the source IC.
Phase Clock Frequency

Gate3[i].PhaseFreq sets the frequency of the phase clock signal that this IC generates. It is a floating-
point number, with units of hertz (Hz). For the IC that is generating the system clock signals, this element
determines the phase clock frequency for the entire system. The default value of 9035 specifies a phase
clock frequency of 9.035 kHz.
For ICs that are receiving external phase clock signals, it is best to set Gate3[i].PhaseFreq to the same
value as the system clock frequency (i.e. the source IC’s phase clock frequency), or as close as possible.
These ICs are locked to the received system clock frequency by a digital phase-locked loop inside the IC,
but this circuit works best if the internal frequency is as close as possible to the received frequency.
It is possible to divide down the received phase clock frequency by a factor of 2, 3, or 4 by setting
Gate3[i].PhaseClockDiv to 1, 2, or 3, respectively. This is rarely done, however – the only real reason is
that doing so supports lower PWM frequencies on this IC.
Similarly, for the IC that is outputting its phase clock signal to the system, it is possible to multiply the
output phase clock frequency by a factor of 2, 3, or 4 by setting Gate3[i].PhaseClockMult to 1, 2, or 3,
respectively. This also is rarely done, and is done only for reasons of providing more flexibility in the
setting of PWM frequencies.
Configuring Gate3 MACRO with Power PMAC 2

Servo Clock Frequency

Gate3[i].ServoClockDiv sets the internally generated servo clock frequency for the IC by specifying how
many times the frequency is divided down from the phase clock frequency. It has a range of 0 to 15,
specifying a division factor of 1 to 16, respectively. The default value is 3, specifying a times-4 division.
With the default phase-clock frequency of 9.035 kHz, this yields a servo-clock frequency of 2.259 kHz.
The equation for Gate3[i].ServoClockDiv is
( )[ ]
[]
( )[ ]
or,
( )[ ]
( )[ ]
( [] )
For ICs receiving an external servo clock signal, the setting of this element does not really matter, but
users should set it to the same value as on the IC that is generating the system clock signals.
The global setup element Sys.ServoPeriod (in milliseconds) must be set to the inverse of the system
servo-clock frequency expressed in kHz. This parameter tells the trajectory interpolation algorithms how
far to advance the commanded motion equations each servo cycle. It can be set as follows:
( [] )
[]
The global setup element Sys.PhaseOverServoPeriod must be set to indicate the ratio between phase and
servo periods according to the following formula:
[]

Hardware Clock Frequencies

Each DSPGATE3 has six internal clock signals that control its own hardware features. These clock
signals are not shared between ICs, and do not need to be the same on different ICs. Each of these clock
signals has a saved setup element that determines its frequency:
 Gate3[i].AdcAmpClockDiv — Bit clock for amplifier A/D converters

 Gate3[i].AdcEncClockDiv — Bit clock for encoder A/D converters
 Gate3[i].DacClockDiv — Bit clock for D/A converters
 Gate3[i].PfmClockDiv — Clock for PFM pulse-generation circuits
 Gate3[i].EncClockDiv — Sampling clock for encoder and discrete-input circuits
 Gate3[i].FiltClockDiv — Secondary filtering clock for discrete inputs
Each of these parameters can take a value “n” from 0 to 15, specifying a frequency division factor of 2n
from the source clock frequency. For the first five of the listed clock frequencies, the source clock
frequency is 100 MHz, so the possible frequencies are 100 MHz, 50 MHz, 25 MHz, 12.5 MHz, etc.,
down to about 3 kHz. These parameters each have a default value of 5 (except for Gate3[i].FiltClockDiv,
which has a default setting of 4, which yields 6.25 MHz) for a division factor of 32, yielding a 3.125 MHz
frequency for their clock signal. This frequency is suitable for most applications. For these five clock
signals, the following table shows the possible settings of Gate3[i].xxxClockDiv and the frequencies they
produce:
Gate3[i].xxxClockDiv Divisor Frequency Setting Divisor Frequency

Setting
0 1 100 MHz 8 256 390.6 kHz
1 2 50 MHz 9 512 195.3 kHz
2 4 25 MHz 10 1,024 97.65 kHz
3 8 12.5 MHz 11 2,048 48.82 kHz
4 16 6.25 MHz 12 4,096 24.41 kHz
5 32 3.125 MHz 13 8,192 12.21 kHz
6 64 1.562 MHz 14 16,384 6.104 kHz
7 128 781.2 kHz 15 32,768 3.052 kHz
For the secondary filtering clock, the source frequency is the encoder sampling clock, which has already
performed a primary filtering function. This parameter has a default value of 4 for a division factor of 32,
yielding a default 195.3 kHz frequency for the secondary digital delay filter.
Example Clock Settings

// ----- Clock Settings for ACC-5E3 at Gate3 Index 0 ----- //
// Phase and Servo Clocks
Gate3[0].PhaseServoDir=0; // This Gate3 transmits clocks; set =3 to receive clocks
Gate3[0].PhaseFreq=9035.69161891937256; // Phase Clock: 9.035 kHz
Gate3[0].PhaseClockMult=0; // Do not multiply output phase clock
Gate3[0].PhaseClockDiv=0; // Do not divide down internal phase clock
Gate3[0].ServoClockDiv=3; // Servo Clock: 2.259 kHz
Sys.ServoPeriod=1000*(Gate3[0].ServoClockDiv+1)/Gate3[0].PhaseFreq;
Sys.PhaseOverServoPeriod=1/(Gate3[0].ServoClockDiv+1);
// Hardware Clocks
Gate3[0].AdcAmpClockDiv=5; // Bit clock for amplifier A/D converters, 3.125 MHz
Gate3[0].AdcEncClockDiv=5; // Bit clock for encoder A/D converters, 3.125 MHz
Gate3[0].DacClockDiv=5; // Bit clock for D/A converters, 3.125 MHz
Gate3[0].PfmClockDiv=5; // Clock for PFM pulse-generation circuits, 3.125 MHz
Gate3[0].EncClockDiv=5; // Sampling clock for encoder and discrete-input circuits, 3.125 MHz
Gate3[0].FiltClockDiv=4; // Secondary filtering clock for discrete inputs, 6.25 MHz

MACRO Communication Registers
Nodes and Addressing

ACC-5E3 has 2 sets of MACRO banks: an “A” bank and a “B” bank. Each bank functions much like
individual, separate MACRO gates as in Turbo PMAC MACRO products. Each MACRO bank consists
of 16 nodes: 2 auxiliary, 8 servo, and 6 I/O nodes:
 Auxiliary nodes are Master/Control registers and are for internal firmware use.
 Servo nodes carry information such as feedback, commands, and flags for motor
control.
 I/O nodes are by default unoccupied and are user configurable for transferring
miscellaneous data.
Each motor that the ring controller controls requires one servo node, and therefore one ACC-5E3 can
control a maximum of 16 motors. The number of I/O nodes used depends on what I/O devices ACC-5E3
is controlling over the MACRO ring. A visual representation of the nodes’ individual functionality is
given below:
I/O Nodes
Node 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Auxiliary
Nodes Servo Nodes
Each node consists of 8 registers: four 32-bit “Input” registers, which can be accessed by the structure
Gate3[i].MacroInA[j][k] for bank A and Gate3[i].MacroInB[j][k] for bank B, and four 32-bit “Output”
registers, which can be accessed by the Power PMAC structures Gate3[i].MacroOutA[j][k] for bank A
and Gate3[i].MacroOutB[j][k] for bank B.

Input Registers
Gate3[i].MacroInA[j][k] accesses input data register k of node j of MACRO bank A in the IC. The data
register index k has a range of 0 to 3. The node index j has a range of 0 to 15. This bank has a master
number on the MACRO ring that is set by bits 28 – 31 of the saved setup element
Gate3[i].MacroEnableA. The input data in all four registers for the node j is automatically received and
latched every phase cycle if bit (j + 8) of Gate3[i].MacroEnableA is set to 1.
In the original MACRO protocol, only the high 24 bits of Gate3[i].MacroInA[j][0] are received over the
ring, and only the high 16 bits of Gate3[i].MacroInA[j][1], Gate3[i].MacroInA[j][2], and
Gate3[i].MacroInA[j][3] are received over the ring. In the new MACRO2 protocol, all 32 bits of all 4
node registers are received over the ring. However, as of this manual’s revision date, no MACRO Station
products yet utilize the MACRO2 protocol.
When the node is used for automatic servo control, saved setup element EncTable[i].pEnc will probably
be set to Gate3[i].MacroInA[j][0].a, and Motor[x].pEncStatus (and other associated address variables)
will be probably be set to Gate3[i].MacroInA[j][3].a. In this case, automatic Power PMAC tasks will
read from these registers, and in general, user application code does not need to read from these registers.
In the DSPGATE3 IC, these are separately addressed registers from the corresponding output values in
Gate3[i].MacroOutA, so it is not possible to write to these elements. In the older DSPGATE2 ICs, the
separate output and input values share a register.
Gate3[i].MacroInB[j][k] is just like Gate3[i].MacroInA[j][k] but for MACRO bank “B.”
Output Registers
Gate3[i].MacroOutA[j][k] is the output data register k of node j of MACRO bank A in the IC. The data
number on the MACRO ring that is set by bits 28 – 31 of saved setup element Gate3[i].MacroEnableA.
The output data in all four registers for the node j is automatically transmitted every phase cycle if bit (j +
8) of Gate3[i].MacroEnableA is set to 1.
In the original MACRO protocol, only the high 24 bits of Gate3[i].MacroOutA[j][0] are transmitted
over the ring, and only the high 16 bits of Gate3[i].MacroOutA[j][1], Gate3[i].MacroOutA[j][2], and
Gate3[i].MacroOutA[j][3] are transmitted over the ring. In the new MACRO2 protocol, all 32 bits of all
4 node registers are transmitted over the ring. However, as of this manual’s revision date, no MACRO
Station products yet utilize the MACRO2 protocol.
When the node is used for automatic servo control, saved setup element Motor[x].pDac will probably be
set to Gate3[i].MacroOutA[j][0].a, and Motor[x].pEncCtrl will be probably be set to
Gate3[i].MacroOutA[j][3].a. In this case, automatic Power PMAC tasks will write to these registers, and
in general, user application code should not write to these registers.
In the DSPGATE3 IC, it is possible to read back what has been written to these registers, as the
corresponding inputs are in separate registers Gate3[i].MacroInA[j][k]. In the older DSPGATE2 ICs, the
separate output and input values share a register, so it is not possible to read back the output values
written to the registers.
Gate3[i].MacroOutB[j][k] is just like Gate3[i].MacroOutA[j][k] but for MACRO bank “B.”

Data Organization within Servo Nodes

When controlling non-Gate3 MACRO Stations, ACC-5E3 will have its servo node information split up
differently within each node j depending on the commutation method being used. The three modes
involved are:
Analog Output Mode

Motor[x].PhaseCtrl = 0
Motor[x].pAdc = 0
UV Commutation Mode (a.k.a. Sinusoidal Commutation Mode)

Motor[x].PhaseCtrl > 0
Motor[x].pAdc = 0
Direct PWM Mode

Motor[x].pAdc > 0 (= Gate3[i].MacroInA[j][1].a for MACRO motors)
Then, the contents of each servo node are arranged in each MACRO bank as follows:
MACRO Bank A
Node Structure Bit 31 Bit 0
Gate3[i].MacroInA[j][0] 24 bits of feedback information 8 bits of 0
Not Used in Analog Output Mode/

Gate3[i].MacroInA[j][1] Not Used in UV Commutation Mode/ 16 bits of 0
16 bits of current sensor ADCA in Direct PWM Mode
Gate3[i].MacroInA[j][2] Not Used in UV Commutation Mode/ 16 bits of 0
16 bits of current sensor ADCB in Direct PWM Mode
Gate3[i].MacroInA[j][3] 16 bits of channel status/flag information 16 bits of 0
24 bits of servo output command in Analog Output Mode/

Gate3[i].MacroOutA[j][0] 24 bits of DACA output in UV Commutation Mode/ 8 bits of 0
24 bits of PWMA command in Direct PWM Mode
Gate3[i].MacroOutA[j][1] 16 bits of DACB command in UV Commutation Mode/ 16 bits of 0
16 bits of PWMB command in Direct PWM Mode
Gate3[i].MacroOutA[j][2] Not Used in UV Commutation Mode/ 16 bits of 0
16 bits of PWMC command in Direct PWM Mode
Gate3[i].MacroOutA[j][3] 16 bits of channel control commands/flag commands 16 bits of 0

MACRO Bank B
Gate3[i].MacroInB[j][0] 24 bits of feedback information 8 bits of 0

Gate3[i].MacroInB[j][1] Not Used in UV Commutation Mode/ 16 bits of 0
Gate3[i].MacroInB[j][2] Not Used in UV Commutation Mode/ 16 bits of 0
Gate3[i].MacroInB[j][3] 16 bits of channel status/flag information 16 bits of 0

Gate3[i].MacroOutB[j][0] 24 bits of DACA output in UV Commutation Mode/ 8 bits of 0
Gate3[i].MacroOutB[j][1] 16 bits of DACB command in UV Commutation Mode/ 16 bits of 0
Gate3[i].MacroOutB[j][2] Not Used in UV Commutation Mode/ 16 bits of 0
Gate3[i].MacroOutB[j][3] 16 bits of channel control commands/flag commands 16 bits of 0
Since no Gate3-style MACRO Station products have yet been developed, this is the only node
arrangement available until future developments.
I/O Nodes can be arranged in any way desired, and as such, this
manual does not have any section describing any specific data
arrangement structure within I/O nodes.
Note

MACRO Communication Setup Instructions

In order to communicate with other devices on the MACRO ring, the user must configure (on ACC-5E3)
the master address, the sync packet node number, and then activate (on ACC-5E3) whatever nodes that
the Slave devices will use. There are two structures for configuring these quantities, one structure per
MACRO bank.
Enabling MACRO Nodes

Gate3[i].MacroEnableA is a 32-bit word that configures the master address, the sync packet node
number, and the active nodes for the first set of MACRO interfaces (“A”) for the IC. It is composed of the
following components (which cannot be accessed as independent elements):
Component Bits Hex Digit # Functionality

MacroMasterNumA 31 – 28 1 MACRO A master address
MacroSyncNodeA 27 – 24 2 MACRO A sync packet node number
MacroNodeEnaA 23 – 08 3–6 MACRO A node enable bits
(Reserved) 07 – 00 7–8 (Reserved for future use)
The 4-bit component MacroMasterNumA specifies the number of the master address for all 16 “A” nodes
in the IC. This 4-bit value, along with the 4-bit node number, will be transmitted as part of the header byte
for each node packet.
The 4-bit component MacroSyncNodeA specifies the number of the “sync packet” node. If this IC is not
acting as the synchronizing master for the ring, and is not receiving the phase clock signal directly from
another IC in the same device, receipt of a data packet for this node will cause an internal synchronizing
signal to be generated, keeping this IC properly locked to the ring timing.
The 16-bit component MacroNodeEnaA specifies which “A” nodes are enabled on the ring. Bit n controls
node n; a value of 0 in the bit disables the node; a value of 1 in the bit enables the node.

Gate3[i].MacroEnableB is a 32-bit word that configures the master address, the sync packet node
number, and the active nodes for the first set of MACRO interfaces (“B”) for the IC. It is composed of the
following components (which cannot be accessed as independent elements):

MacroMasterNumB 31 – 28 1 MACRO B master address
MacroSyncNodeB 27 – 24 2 MACRO B sync packet node number
MacroNodeEnaB 23 – 08 3–6 MACRO B node enable bits
The 4-bit component MacroMasterNumB specifies the number of the master address for all 16 “B” nodes
in the IC. This 4-bit value, along with the 4-bit node number, will be transmitted as part of the header byte
for each node packet.
The 4-bit component MacroSyncNodeB specifies the number of the “sync packet” node. If this IC is not
acting as the synchronizing master for the ring, and is not receiving the phase clock signal directly from
another IC in the same device, receipt of a data packet for this node will cause an internal synchronizing
signal to be generated, keeping this IC properly locked to the ring timing.
The 16-bit component MacroNodeEnaB specifies which “B” nodes are enabled on the ring. Bit n controls
node n; a value of 0 in the bit disables the node; a value of 1 in the bit enables the node.

Configuring MACRO Modes

Gate3[i].MacroModeA is the full-word element that comprises the control and status components for the
first set of MACRO interfaces (“A”) for the IC. It is composed of the following components (which
cannot be accessed as independent elements):

MacroMasterChkDisA 23 – 16 3–4 MACRO A master check disable
MacroSyncEnaA 15 5 MACRO A phase clock sync enable
MacroSyncRcvdA 14 5 MACRO A sync packet received status
MacroStationTypeA 13 – 12 5 MACRO A station type
MacroUnderrunErrA 11 6 MACRO A data underrun error status
MacroParityErrA 10 6 MACRO A parity/CRC error status
MacroCodeErrA 09 6 MACRO A byte coding error status
MacroOverrunErrA 08 6 MACRO A data overrun error status
The 8-bit component MacroMasterChkDisA specifies whether the IC will check the master number for
the highest-numbered eight “A” nodes on the IC. Bit n of the component (which is bit n+8 of the full-
word element) controls Node n+8 of the IC. If the bit is 0, the IC will check the master number of the
incoming packet for the matching node number, so the packet can be used for point-to-point
communication across the ring. If the bit is 1, the IC will not check the master number of the incoming
packet for the matching node number, so the packet can be used for “broadcast” purposes.
The 1-bit component MacroSyncEnaA specifies whether the IC’s phase clock will be synchronized by the
receipt of the specified “sync packet” or not. If it is set to 0, no synchronization will be performed; if it is
set to 1, the IC’s phase clock timer will be synchronized to the timing of the receipt of the sync packet on
the ring. This bit is not used if the IC is the synchronizing master for the ring, or if it is receiving the
phase clock from another IC in the same device.
The 1-bit component MacroSyncRcvdA is a read-only status bit that is set to 1 when the specified sync
packet is received. It is automatically set to 0 when this register is read, so it indicates to the processor
whether a sync packet has been received since the last time the register was read. The 2-bit component
MacroStationTypeA specifies the function of the station containing this IC on the MACRO ring. Its
possible values specify the following frequencies:
 0: Slave
 1: Master
 2: (Reserved for future use)
 3: Synchronizing master
The 1-bit component MacroUnderrunErrA is a read-only status bit that is set to 1 when the IC receives a
data packet with too few bytes in it. It is automatically set to 0 when this register is read, so it indicates to
the processor whether an underrun error has occurred since the last time the register was read.
The 1-bit component MacroParityErrA is a read-only status bit that is set to 1 when the IC receives a data
packet with a parity or CRC check error. It is automatically set to 0 when this register is read, so it
indicates to the processor whether a parity/CRC error has occurred since the last time the register was
read.

The 1-bit component MacroCodeErrA is a read-only status bit that is set to 1 when the IC receives a data
packet with an illegally coded byte in it. It is automatically set to 0 when this register is read, so it
indicates to the processor whether a coding error has occurred since the last time the register was read.
The 1-bit component MacroOverrunErrA is a read-only status bit that is set to 1 when the IC receives a
data packet with too many bytes in it. It is automatically set to 0 when this register is read, so it indicates
to the processor whether an overrun error has occurred since the last time the register was read.

Gate3[i].MacroModeB is the full-word element that comprises the control and status components for the
first set of MACRO interfaces (“B”) for the IC. It is composed of the following components (which
cannot be accessed as independent elements):

MacroMasterChkDisB 23 – 16 3–4 MACRO B master check disable
MacroSyncEnaB 15 5 MACRO B phase clock sync enable
MacroSyncRcvdB 14 5 MACRO B sync packet received status
MacroStationTypeB 13 – 12 5 MACRO B station type
MacroUnderrunErrB 11 6 MACRO B data underrun error status
MacroParityErrB 10 6 MACRO B parity/CRC error status
MacroCodeErrB 09 6 MACRO B byte coding error status
MacroOverrunErrB 08 6 MACRO B data overrun error status
The 8-bit component MacroMasterChkDisB specifies whether the IC will check the master number for
the highest-numbered eight “B” nodes on the IC. Bit n of the component (which is bit n+8 of the full-
word element) controls Node n+8 of the IC. If the bit is 0, the IC will check the master number of the
incoming packet for the matching node number, so the packet can be used for point-to-point
communication across the ring. If the bit is 1, the IC will not check the master number of the incoming
packet for the matching node number, so the packet can be used for “broadcast” purposes.
The 1-bit component MacroSyncEnaB specifies whether the IC’s phase clock will be synchronized by the
receipt of the specified “sync packet” or not. If it is set to 0, no synchronization will be performed; if it is
set to 1, the IC’s phase clock timer will be synchronized to the timing of the receipt of the sync packet on
the ring. This bit is not used if the IC is the synchronizing master for the ring, or if it is receiving the
phase clock from another IC in the same device.
The 1-bit component MacroSyncRcvdB is a read-only status bit that is set to 1 when the specified sync
packet is received. It is automatically set to 0 when this register is read, so it indicates to the processor
whether a sync packet has been received since the last time the register was read. The 2-bit component
MacroStationTypeB specifies the function of the station containing this IC on the MACRO ring. Its
possible values specify the following frequencies:
 0: Slave
 1: Master
 2: (Reserved for future use)
 3: Synchronizing master
The 1-bit component MacroUnderrunErrB is a read-only status bit that is set to 1 when the IC receives a
data packet with too few bytes in it. It is automatically set to 0 when this register is read, so it indicates to
the processor whether an underrun error has occurred since the last time the register was read.
The 1-bit component MacroParityErrB is a read-only status bit that is set to 1 when the IC receives a data
packet with a parity or CRC check error. It is automatically set to 0 when this register is read, so it
indicates to the processor whether a parity/CRC error has occurred since the last time the register was
read.

The 1-bit component MacroCodeErrB is a read-only status bit that is set to 1 when the IC receives a data
packet with an illegally coded byte in it. It is automatically set to 0 when this register is read, so it
indicates to the processor whether a coding error has occurred since the last time the register was read.
The 1-bit component MacroOverrunErrB is a read-only status bit that is set to 1 when the IC receives a
data packet with too many bytes in it. It is automatically set to 0 when this register is read, so it indicates
to the processor whether an overrun error has occurred since the last time the register was read.
MACRO Error Testing Variables

Power PMAC MACRO has three variables for error checking:
Macro.TestPeriod
This is the period in servo cycles at which PMAC checks for errors on the MACRO ring. The
recommended value for this variable is 10/Sys.ServoPeriod, which produces a period of 10 milliseconds.
Macro.TestMaxErrors
This is the maximum error count PMAC can receive in one test period (whose duration is specified by
Macro.TestPeriod) before triggering a fault. The formula for computing this variable is as follows:
Macro.TestReqdSynchs
This is the number of sync packets in one period (whose duration is specified by Macro.TestPeriod) that
PMAC must receive before triggering an error. The formula for computing this variable is as follows:
- .
Example MACRO Communication Setup

Sys.WpKey=$AAAAAAAA;
//MACRO Communication Setup

Gate3[0].MacroEnableA=$0FFFFF00; // Activate 8 Servo Nodes and 6 IO Nodes of MACRO A
// & 2 auxiliary nodes 14 and 15.
// The sync packet node is set to 15.
Gate3[0].MacroModeA=$403000; // Set MACRO A as master
Gate3[0].MacroEnableB=$1FBFFF00; // Activate 8 Servo Nodes and 6 IO Nodes of MACRO B
// & 1 auxiliary node, 15. The synch packet node is set to 15.
Gate3[0].MacroModeB=$001000; // Set MACRO B as master to synchronize clock
Macro.TestPeriod=10/Sys.ServoPeriod; // MACRO Ring Check Period [servo cycles]

// (Related to I80 in Turbo)
Macro.TestMaxErrors=Macro.TestPeriod/10; // MACRO Maximum Ring Error Count (Related to I81 in Turbo)
Macro.TestReqdSynchs=Macro.TestPeriod - Macro.TestMaxErrors; // MACRO Minimum Sync Packet Count
Sys.WpKey=0;

CONFIGURING GATE2 MACRO WITH POWER PMAC

Clock Signals
In a PMAC2-style Servo or MACRO IC, the internally generated phase and servo clock frequencies are
determined by the setting of three saved setup elements for the IC:
 Gate2[i].PwmPeriod
 Gate2[i].PhaseClockDiv
 Gate2[i].ServoClockDiv
Gate2[i].PwmPeriod: MaxPhase Clock Frequency Control

As the name suggests, Gate2[i].PwmPeriod sets the period of the PWM cycle in the IC, to a time
proportional to its value. The frequency is, of course, inversely proportional to the period. But it
also sets the period of the internal “MaxPhase” clock signal, which is always ½ of the PWM cycle
period – so its frequency is twice the PWM frequency. Even if you are not using PWM signals
from the IC, the setting of this element is important.
To set Gate2[i].PwmPeriod for a desired “MaxPhase” clock frequency, the following formula
can be used:
[ ]
[]
[ ]
Gate2[i].PhaseClockDiv: Phase Clock Frequency Control

From the internal “MaxPhase” clock signal, the phase clock signal is generated with a frequency
divider circuit that is controlled by Gate2[i].PhaseClockDiv. The phase clock frequency is equal
to the “MaxPhase” clock frequency divided by (Gate2[i].PhaseClockDiv + 1).
The equation for Gate2[i].PhaseClockDiv is:
[ ]
[]
[ ]
At the default value of 0 (divide by 1) and the default MaxPhase frequency of 9.04 kHz, this sets
a phase clock frequency of 9.04 kHz (110 μsec period).

Gate2[i].ServoClockDiv: Servo Clock Frequency Control

From the phase clock signal, the servo clock signal is generated with a frequency divider circuit
that is controlled by Gate2[i].ServoClockDiv. The servo clock frequency is equal to the phase
clock frequency divided by (Gate2[i].ServoClockDiv + 1).
The equation for Gate2[i].ServoClockDiv is:
[ ]
[]
[ ]
At the default value of 3 (divide by 4) and the default phase clock frequency of 9.04 kHz, this
sets a servo clock frequency of 2.26 kHz (442 μsec period).
The following diagram shows the relationship between the PWM counter, whose
period/frequency is set by the Gate2[i].PwmPeriod parameter, the resulting MaxPhase clock
signal, and the phase and servo clock signals that are derived from MaxPhase.
Sys.ServoPeriod
You must set Sys.ServoPeriod according to the following formula:
( [] )( [] )( [] )
Sys.PhaseOverServoPeriod
Set Sys.PhaseOverServoPeriod according to the following formula:
[]
Example Clock Settings

// ----- Clock Settings for ACC-5E at Gate2 Index 0 ----- //
// Phase and Servo Clocks
Gate2[0].PhaseServoDir=0; // This Gate transmits clocks; set =3 to receive clocks
Gate2[0].PwmPeriod=117964.8/(2.0*9035.69161891937256)-1.0; // PWM Clock: 9.035 kHz
Gate2[0].PhaseClockMult=0; // Do not multiply output phase clock-->9 kHz
Gate2[0].PhaseClockDiv=0; // Do not divide down internal phase clock
Gate2[0].ServoClockDiv=3; // Servo Clock: 2.259 kHz
Sys.ServoPeriod=1000*(Gate2[0].ServoClockDiv+1)/Gate2[0].PhaseFreq;
Sys.PhaseOverServoPeriod=1/(Gate2[0].ServoClockDiv+1);

MACRO Communication Registers
Nodes and Addressing

Each MACRO IC consists of 16 nodes: 2 auxiliary, 8 servo, and 6 I/O nodes.
 Auxiliary nodes are Master/Control registers and internal firmware use.

 Servo nodes carry information such as feedback, commands, and flags for motor control.
 I/O nodes are by default unoccupied and are user configurable for transferring miscellaneous data.
Each motor that the ring controller controls requires one servo node, and therefore one ACC-5E can
control a maximum of 16 motors. The number of I/O nodes used depends on what I/O devices ACC-5E is
controlling over the MACRO ring. A visual representation of the nodes’ individual functionality is given
below:
I/O Nodes
Node 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Auxiliary
Nodes Servo Nodes
The MACRO date is stored in the Gate2[i].Macro[j][k] set of registers.
Range: -223 to 223-1

Units: User-determined
Power-on default: $0
Gate2[i].Macro[j][k] is the input/output data register k of node j of the MACRO bank in the IC. The data
number on the MACRO ring that is set by bits 20 – 23 of saved setup element Gate2[i].MacroEnable.
The output data in all four registers for the node j is automatically sent, and the input data in all four
registers is received every phase cycle if bit j of Gate2[i].MacroEnable is set to 1.
These are 24-bit elements in the Script environment. Gate2[i].Macro[j][0] has real ring data in all 24
bits, while Gate2[i].Macro[j][1], Gate2[i].Macro[j][2], and Gate2[i].Macro[j][3] only have real ring
data in the high 16 bits.

Note that the output and input registers share an element – a write operation to the element accesses the
output register, and this value will be sent out across the ring; a read operation from the element accesses
the input register, getting a value that has been received from across the ring. This means that it is not
possible to read back an output value that has been written to one of these elements.
When the node is used for automatic servo control, saved setup element Motor[x].pDac will probably be
set to Gate2[i].Macro[j][0].a, and Motor[x].pEncCtrl will be probably be set to Gate2[i].Macro[j][3].a.
In this case, automatic Power PMAC tasks will write to these registers, and in general, user application
code should not write to these registers.
In the C-language environment, these are 32-bit elements, with the real data in the high 24 or 16 bits, so
you must be careful to appropriately mask and shift to read from or write to the appropriate bits in these
words.

Data Organization within Servo Nodes

When controlling non-Gate3 MACRO Stations, ACC-5E will have its servo node information split up
differently within each node j depending on the commutation method being used. The three modes
involved are:
Analog Output Mode

Motor[x].PhaseCtrl = 0
Motor[x].pAdc = 0
UV Commutation Mode (a.k.a. Sinusoidal Commutation Mode)

Motor[x].pAdc = 0
Direct PWM Mode

Motor[x].pAdc > 0 (= Gate2[i].Macro[j][1].a for MACRO motors)
Then, the contents of each servo node are arranged in each MACRO bank as follows when the Ring
Controller is receiving data from the rest of the Stations on the MACRO ring, as viewed in Script:
MACRO Input
Gate2[i].Macro[j][0] 24 bits of feedback information

Gate2[i].Macro[j][1] Not Used in UV Commutation Mode/ 8 bits of 0
Gate2[i].Macro[j][3] 16 bits of channel status/flag information 8 bits of 0
MACRO Output
Gate2[i].Macro[j][0] 24 bits of DACA output in UV Commutation Mode/
Gate2[i].Macro[j][1] 16 bits of DACB command in UV Commutation Mode/ 8 bits of 0
Gate2[i].Macro[j][3] 16 bits of channel control commands/flag commands 8 bits of 0

Since no Gate3-style MACRO Station products have yet been developed, this is the only node
arrangement available until future developments.
I/O Nodes can be arranged in any way desired, and as such, this
manual does not have any section describing any specific data
arrangement structure within I/O nodes.
Note
When viewed in C, these structures are 32 bits. Gate2[i].Macro[j][0]

uses bits [31:8]; Gate2[i].Macro[j][1], Gate2[i].Macro[j][2], and
Gate2[i].Macro[j][3] use bits [31:16].
Note

MACRO Communication Setup Instructions
Enabling MACRO Nodes

Gate2[i].MacroEnable controls which of the 16 MACRO nodes on the MACRO IC are activated. It also
controls the master station number of the IC, and the node number of the packet that creates a
synchronization signal. The bits are arranged as follows:
Bit # Value Type Function

0 1 ($1) Config Node 0 Activate
16–19 $X0000 Config Packet Sync Node Slave Address (X=0-
20–23 $X00000 Config Master Station Number (X=0-F)
Bits 0 to 15 are individual control bits for the matching node number 0 to 15. If the bit is set to 1, the node
is activated; if the bit is set to 0, the node is de-activated.
If the MACRO IC is a master station (likely) as determined by Gate2[i].MacroMode, it will send out a
packet for each activated node every ring cycle (every phase cycle). When it receives a packet for an
activated node, it will latch in that packet and not pass anything on.
If the MACRO IC is a slave station (unlikely but possible) as determined by Gate2[i].MacroMode, when
it receives a packet for an activated node, it will latch in the contents of that packet into its read registers
for that node address, and automatically substitute the contents of its write registers into the packet.
If a node is disabled, whether master or slave, it will still latch in the contents of a packet it receives, but it
will also pass on the packet unchanged. This feature is particularly useful for the MACRO broadcast
feature, in which multiple stations need to receive the same packet.
Bits 16–19 together specify the slave number part of the packet address (0–15) that will cause a sync lock
pulse on the card, if this function is enabled by Gate2[i].MacroMode. This function is useful for a Power
PMAC that is a slave or non-synchronizing master on the ring, to keep it locked to the synchronizing
master. If the master address check for this node is disabled with Gate2[i].MacroMode, only the slave
number must match to create the sync lock pulse. If the master address check is left enabled, the master
number part of the packet address must match the master number for the card, as set in bits 20–23 of
Gate2[i].MacroEnable.

Bit 15 of Gate2[i].MacroEnable is automatically set to 1 by the firmware at power-up/reset, regardless

of the saved value of Gate2[i].MacroEnable.
If this card is the synchronizing master, this function is not enabled, so the value of these bits does not
matter; they can be left at the default of 0.
Bits 20–23 specify the master number for the MACRO IC (0–15). Each MACRO IC on a ring must have
a separate master number, even multiple MACRO ICs on the same Turbo PMAC2 Ultralite. The number
must be specified whether the card is used as a master or a slave.
Configuring MACRO Modes

Gate2[i].MacroMode contains configuration and status bits for MACRO ring operation of the MACRO
IC on the Power PMAC. There are 11 configuration bits and 5 status bits, as follows:
Bit # Value Type Function

0 1($1) Status Data Overrun Error (cleared when read)
1 2($2) Status Byte Violation Error (cleared when read)
2 4($4) Status Packet Parity Error (cleared when read)
3 8($8) Status Packet Underrun Error (cleared when read)
4 16($10) Config Master Station Enable
5 32($20) Config Synchronizing Master Station Enable
6 64($40) Status Sync Node Packet Received (cleared when read)
7 128($80) Config Sync Node Phase Lock Enable
8 256($100) Config Node 8 Master Address Check Disable
In most applications, the only important configuration bits are bits 4, 5, and 7. In every MACRO ring,
there must be one and only one synchronizing master station (each MACRO IC counts as a separate
station; only one MACRO IC on any card in the ring can be a synchronizing master station). For this
MACRO IC, bits 4 and 5 should be set (1), but bit 7 should be clear (0). This results in a value of $30, or
$xx30 if any of the high bits are to be set.
If there are more than one MACRO ICs acting as masters on the ring, the others should not be
synchronizing masters, but they should be set up as regular (non-synchronizing) masters. If they are
receiving the phase clock signal directly from the synchronizing master IC, bit 4 should be set (1), and
bits 5 and 7 should be clear (0). This results in a value of $10, or $xx10 if any of the high bits are set.
If they are not receiving the phase clock signal directly from the synchronizing master IC, they should
enable “sync node phase lock” to stay synchronized with the synchronizing master by receipt of the “sync
packet”. For these MACRO ICs, bit 4 should be set (1), bit 5 should be clear (0), and bit 7 should be set
(1), resulting in a value of $90, or $xx90 if any of the high bits are to be set.
Bits 8–15 can be set individually to disable the “master address check” for their corresponding node
numbers. This capability is for multi-master broadcast and synchronization. If the master address check is
disabled, only the slave node number part of the packet address must match for a packet to be latched in.

In this way, the synchronizing master can send the same data packet to multiple other master and slave
stations. This common packet can be used to keep multiple stations synchronized using the sync lock
function enabled with bit 7 of Gate2[i].MacroMode; the packet number is specified in
Gate2[i].MacroEnable (packet 15 is suggested for this purpose).

MACRO Error Testing Variables

Power PMAC MACRO has three variables for error checking:
Macro.TestPeriod
This is the period in servo cycles at which PMAC checks for errors on the MACRO ring. The
recommended value for this variable is 10/Sys.ServoPeriod, which produces a period of 10 milliseconds.
Macro.TestMaxErrors
This is the maximum error count PMAC can receive in one test period (whose duration is specified by
Macro.TestPeriod) before triggering a fault. The formula for computing this variable is as follows:
Macro.TestReqdSynchs
This is the number of sync packets in one period (whose duration is specified by Macro.TestPeriod) that
PMAC must receive before triggering an error. The formula for computing this variable is as follows:
- .
Example MACRO Communication Setup

//MACRO Communication Setup
Gate2[0].MacroEnable=$0FFFFF; // Activate 8 Servo Nodes and 6 IO Nodes of MACRO IC 0
Gate2[0].MacroMode=$4030; // Set MACRO IC 0 as Synchronizing Master
Macro.TestPeriod=10/Sys.ServoPeriod; // MACRO Ring Check Period [servo cycles]

Macro.TestMaxErrors=Macro.TestPeriod/10; // MACRO Maximum Ring Error Count (Related to I81 in Turbo)
Macro.TestReqdSynchs=Macro.TestPeriod - Macro.TestMaxErrors; // MACRO Minimum Sync Packet Count

POWER PMAC MACRO COMMANDS

The following commands are available in Power PMAC Firmware 1.6.0.9 and above.
Online MACRO Commands Quick Reference

The following commands can be used in the Power PMAC IDE’s Terminal Window (online) and also can
be called from synchronous (motion) script programs and asynchronous (PLC) script programs using the
cmd command (e.g. cmd"MacroSlave0,MI5=1").
Command Syntax Comment

MacroSlave {{node},{ MI, MM, or MP Master reads or writes an MI, MM, or MP
Variable}{=expression}} variable from/to the Slave at node {node} and
gets the response. If {=expression} is present,
Shorthand: write to the variable; if absent, read from the
MS{{node},{ MI, MM, or MP variable.
Variable}{=expression}}
MacroSlaveRead{{node}, {MI, MM, or MP Read an MI, MM or MP variable from the
Variable} , {Global Var}} Slave Station on {node} and put its value in
{Global Var} on the Master.
MacroSlaveWrite{{node}, {MI, MM, or MP Write (from the Master) the result of
Variable}, {expression}} {expression} to an MI, MM or MP variable on
the Slave Station at node {node}.
MacroSlaveCLRF{node} Master to Slave Clear Faults at node {node}.
MacroSlaveDATE {node} Display the Firmware Date of the Slave at
node {node}.
MacroSlaveSAVE {node} Issues a SAVE command from the Master to
the Slave at node {node}.
MacroSlaveVERS{node} Display the Firmware Version of the Slave at
node {node}.
MacroSlave$$${node} Issues a $$$ command to the Slave at node
{node}.
MacroSlave$$$***{node} Issues a $$$*** to the Slave at node {node}.
MacroAuxiliary{{node},{MI, MM, MP or MQ Master to Auxiliary Slave (i.e. a Turbo PMAC
Variable}{=constant}} Slave) at node {node}. If {=constant} is
present, write it to the MI, MM, MP, or MQ
Shorthand: variable on the Slave at node {node}. If not
MX{{node},{MI, MM, MP or MQ present, read the MI, MM, MP, or MQ
Variable}{=constant}} variable’s value.
MacroAuxiliaryRead{{node}, {MI, MM, MP, Read an MI, MM, MP or MQ variable from
or MQ Variable},{ Global Var}} {node} and put its value into {Global Var}.
MacroAuxiliaryWrite{{node}, {MI, MM, MP, Write the result of {expression} to an MI, MM,
or MQ Variable} , {expression}} MP or MQ variable on Auxiliary Slave at
{node}.
MacroMaster{{mst}, {MI, MM, MP, or MQ Synchronizing Master to Master {mst}
Variable}{=constant}} read/write an MI, MM, MP, or MQ variable. If
{=constant} is present, write it to the specified
Shorthand: MI, MM, MP, or MQ variable on Master
MM{{mst}, {MI, MM, MP, or MQ Station number {mst}. If not present, read the
Variable}{=constant}} MI, MM, MP, or MQ variable’s value.
Power PMAC MACRO Commands 25


MacroMasterRead{{mst},{MI, MM, MP, or Read an MI, MM, MP or MQ variable from
MQ Variable}, {Global Var}} Master number {mst} into {Global Var} on the
Synchronizing Master.
MacroMasterWrite{{mst}, {MI, MM, MP, or Write (from the Synchronizing Master) the
MQ Variable},{expression}} result of {expression} to the specified MI,
MM, MP or MQ variable on Master number
{mst}.
MacroPort Displays the current communication thread’s
Macro Port number.
MacroPortClose {constant} Close the selected Macro Port Number
specified by {constant}, or if no port number is
specified, the current thread’s Port Number.
MacroPortState Displays the state of all the Macro Ports.
MacroRingMasterSlave{{Ring Number}, Read/Write an MI, MM or MP variable
{Master Number},{Node Number},{MI, MM from/to the Slave Station on the specified
or MP Variable}{=constant}} {Ring Number}, {Master Number}, and {Node
Number} (0–13). If {=constant} is present,
MRMS{{Ring Number}, {Master this commands sets the specified variable. If
Number},{Node Number},{MI, MM or MP not present, this command reads the specified
Variable}{=constant}} variable.
MacroRingMasterSlaveRead{{Ring Number}, Read an MI, MM or MP variable from the
{Master Number},{Node Number}, {MI, MM Slave Station on the specified {Ring Number},
or MP Variable}, {Global Var}} {Master Number}, and {Node Number} (0–
13), and put its value into {Global Var} on the
Master. This value can be an expression.
MacroRingMasterSlaveWrite{{Ring Number}, Write to an MI, MM or MP variable at the
{Master Number},{Node Number}, {MI, MM Slave Station on the specified {Ring Number},
or MP Variable},{Global Var}} {Master Number}, and {Node Number} (0–
13), using the value in {Global Var}. This
value can be an expression.
MacroRingMasterSlaveCLRF{{Ring Number}, Master to Slave Clear Faults at the specified
{Master Number},{Node Number}} {Ring Number}, {Master Number}, and {Node
Number} (0–13).
MacroRingMasterSlaveDATE{{Ring Display Master to Slave Firmware Date at the
Number}, {Master Number},{Node Number}} specified {Ring Number}, {Master Number},
and {Node Number} (0–13).
MacroRingMasterSlaveSAVE {{Ring Issue Master to Slave Save at the specified
Number},{Master Number},{Node Number}} {Ring Number}, {Master Number}, and {Node
Number} (0–13).
MacroRingMasterSlaveVERS{{Ring Display Master to Slave Firmware Version at
Number},{Master Number},{Node Number}} the specified {Ring Number}, {Master
Number}, and {Node Number} (0–13).
MacroRingMasterSlave$$$ {{Ring Number}, Issue Master to Slave $$$ at the specified
{Master Number},{Node Number}} {Ring Number}, {Master Number}, and {Node
Number} (0–13).
MacroRingMasterSlave$$$***{{Ring Issue Master to Slave $$$*** at the specified
Number},{Master Number},{Node Number}} Ring Number, Master Number, and {Node
Number} (0–13).


MacroRing{=num} Sets the Ring Controller’s ring number to
{num}. Note that the number of possible
settings this can take corresponds to the value
in Macro.Rings.
MacroRingOrderDetect Detects and gets the Ring Order data of the
Stations on the Ring, Saves it to the
“ringorder{n}.mro” file for the currently
addressed ring of Ring Number {n} and to the
SHM mro structure. Also displays the data to
the screen.
MacroRingOrderInit{stn} Resets the selected Station number {stn}, or if
the {stn} input is zero, resets all the Stations to
their Station Number according to their order
in the ring, and then performs a
MacroRingDetect command on the currently
addressed ring.
MacroRingOrderLoad Loads the “ringorder{n}.mro” file for the
currently addressed Ring of Ring Number {n}
into the SHM mro structure.
MacroRingOrderRepair Finds using “Verify” the Station(s) on the
currently addressed Ring Number ({n}) to
repair and restores it/them using the
“ring{n}stn{stn}.cfg” backup file for each
Station it finds of Station Number {stn}. It will
not repair a Turbo PMAC slave.
MacroRingOrderSave Issues a broadcast “save” command to all
Stations (except the Ring Controller).
MacroRingOrderVerify{stn} Verifies all (if {stn} is omitted) Stations or the
specified Ring Order Station {stn} against the
SHM mro Structure.
MacroRingOrderStations Displays the number of detected Stations on
the currently addressed ring.
MacroRingOrderStatus{stn} Display the status of Station {stn} (except the
Ring Controller).
MacroRingOrderType{stn} Display the TYPE of Station {stn}.
MacroRingOrder$$$ Issues a broadcast “$$$” (reset, loading saved
memory to active memory) to all Stations
($$$) (except to the Ring Controller) on the
currently addressed ring.
MacroRingOrder$$$*** Issues a broadcast “$$$***” (reset to factory
defaults) to all Stations (except to the Ring
Controller) on the currently addressed ring.
MacroRingOrderClrf Issues a broadcast “clrf” (Clear Faults) to all
Stations on the currently addressed ring,
including the Ring Controller.
MacroRingOrderSync Issues a broadcast synchronization request to
all Stations on the falling edge of the Servo
Clock on the currently addressed ring.


MacroRingOrderBackup{stn} Saves a backup of the Stations on the currently
addressed Ring Number ({n}) to the
“ring{n}stn{stn}.cfg” file. If {stn} = 0, this
command backs up all Stations except the Ring
Controller. It will not back up a Turbo PMAC
slave.
MacroRingOrderVerifyBackup{stn} Verifies the data in the ring{n}stn{stn}.cfg”file
for all Stations (if {stn}=0), or for only
theselected Ring Order Station specified by
{stn},against the Station values of the currently
addressed Ring Number ({n}). It will not
verify a backup of a Turbo PMAC slave.
MacroRingOrderRestore{stn} Restores Station from the
“ring{n}stn{stn}.cfg” backup file for the
currently addressed Ring Number ({n}). If
{stn} = 0, this command restores all Stations
except the Ring Controller.
MacroRingOrderRepair This command issues MacroRingOrderVerify
to see what Station(s) is/are missing, then it
issues a MacroRingOrderInit{stn} command to
that Station in the Ring Order, and then it
issues MacroRingOrderRestore{stn} using the
Backup file, “ring{n}stn{stn}.cfg”, for that
Station Number ({stn}) and the currently
addressed Ring Number ({n}). Then, it issues
MacroRingOrderVerify{stn} for a quick
verification of the Restore.
MacroStation{stn} Initiate Synchronizing Master to Slave Station
ASCII communication at Station Number
{stn}.
MacroStationErrors{stn} Displays Station {stn}’s MACRO error
information.
MacroStationClearErrors{stn} Sends a MACRO “CLRF” and “I5=0” to the
selected Station of the selected Ring.
<MacroStationClose Close Synchronizing Master to Station ASCII
communication. Note: the ‘<’ means send the
command from the Station to the Master.
Omitting it transmits MacroStationClose from
the Master to the Slave.
MacroStationEnable{{stn}, {Gate Index} Read/Write MACRO Station Node Enable
{=constant}} Register (e.g. from I996, I1996 I6841, I6891,
etc.) in Gate2 format for the Gate at the
specified {Gate Index}. If {=constant} is
specified, set the Node Enable Register with
the value of {constant}. If not, retrieve the
Node Enable Register’s value.


MacroStationFrequency{=num} Sets the MACRO Ring Frequency of all
Stations (including Ring Controller) if {num}
is not specified or display the Ring Controller’s
frequency if {num}=0. ({num} is in Gate2
Format, e.g., 6527 default value; =* sets to
default). Sets this value in all the local Gate1,
Gate2 and Gate3 Max Phase Frequencies.
MacroStationRingCheck {stn} {= Period, Read/Write MACRO Ring Check parameters
EaxErrors, MinSyncs} period [milliseconds), Max % Errors, and
Min % Sync Packets of the currently addressed
Ring and Station. If {stn} = 0 and you are
writing values, then this command will write to
all Rings and Stations. If you command
"MacroStationRingCheck{stn}= *", PMAC
will set default MACRO settings: Period = 10
msec, MaxErrors = 10%, MinSyncs = 90%.
MacroStationStatus{stn} Returns the ASCII names and value of each bit
of the status word for Station Number {stn}.
MacroStationType {stn} Display the TYPE of Station {stn} on the
currently addressed Ring.
MacroControllerInit Detects the number of valid MACRO rings,
and then initializes the Ring Sync Master and
the remaining Masters for each of the detected
rings. The node enable values are left
unchanged. The Sync Master is set to Master 0
and the remaining masters are incremented by
1 for each ring. The sync packet is set to 15.
MacroControllerDetect Detects the number of valid MACRO rings and
masters. The MacroMode and MacroEnable
values are left unchanged.
The mro file can be found on the Power PMAC in

var/ftp/userflash/Project/Configuration as “ringorder{n}.mro” where
{n} is the Ring Number (e.g. “ringorder0.mro” for Ring Number = 0).
The user can have up to four Rings with the 1st ring number as zero.
Note This file is used to quickly verify that all the stations in the Ring are in
the last saved configuration.

The aforementioned SHM mro structure is defined as follows in C:
typedef struct StnROData {

unsigned stn; ///< Station Number; should be the Ring Order
unsigned cid; ///< Station CID
unsigned char vid[32]; ///< Station VID
unsigned char sid[32]; ///< Station SID
unsigned char vers[16]; ///< Station VERS
unsigned char date[32]; ///< Station DATE
unsigned char type[32]; ///< Station TYPE
unsigned StationConfig; ///< Station MI3 (SW1-SW2 or Jumper Config)
unsigned TestPeriod; ///< Station MI8/I80
unsigned TestMaxErrors; ///< Station MI9/I81
unsigned TestReqdSynchs; ///< Station MI10/I82
unsigned MacroMode[4]; ///< Station MI995/I6840
signed MacroEnable[4]; ///< Station MI996/I6841
unsigned char MaxPhaseFreq[16]; ///< Station I992/I6800
}
Examples of Commands Using Symbolic Variables

Note that any cmd"" command must be placed in a program. If you are executing these commands from
the Terminal Window, you do not need to encapsulate the MACRO command within cmd"".
Global Variables
global mypvar, myparray(16);
cmd "MacroslaveRead 0, MI2, mypvar"

cmd "MacroslaveRead 0, MI2, myparray(2)"
cmd "MacroslaveWrite 0, MI2, myparray(0)"
CSGlobal Variables
csglobal myqvar, myqarray(16);
cmd "MacroslaveRead0, MI2, &1 myqvar"

cmd "MacroslaveRead0, MI2, &1 myqarray(2)"
cmd "MacroslaveWrite0, MI2, &1 myqarray(0)"
Ptr Variables
ptr mymvar->*, mymarray(16)-> u.user:200+;
cmd "MacroslaveRead 0, MI2, mymvar"

cmd "MacroslaveRead 0, MI2, mymarray(2)"
cmd "MacroslaveWrite 0, MI2, mymarray(0)"

Supported Power PMAC MACRO Registers

The following registers allow user to check for errors and statuses on Power PMAC.

Macro.TestPeriod MACRO Ring Check Period [servo cycles]
Macro.TestMaxErrors MACRO Maximum Ring Error Count
Macro.TestReqdSynchs MACRO Minimum Sync Packet Count
MACRO Error Count Since Last Power Up
Macro.RingTest[0–3].PwrOnErrCntr or $$$
Station number of where Ring Break
Macro.RingTest[0–3].RingBrkStationNum occurred
Macro.Station Macro Station Number
Macro.ICs Number of Macro ICs detected
Macro.IC3s Number of Macro IC3s detected
Communication timeout override value (real-
time interrupt cycles). Writing a value of 0 to
Macro.IOTimeout this sets to the default value of 100.
Macro.Rings Number of MACRO Rings detected
Macro.Status[0–3] MACRO Ring Status word

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^1 USER MANUAL

^2 Power PMAC MACRO

^3 Power PMAC MACRO Software Setup

Single Source Machine Control Power // Flexibility // Ease of Use

A Warning identifies hazards that could result in personal injury

A Caution identifies hazards that could result in equipment damage. It

A Note identifies information critical to the user’s understanding or

The following Power PMAC Ring Controllers use Gate3 technology:

The following Power PMAC Ring Controllers use Gate2 technology:

CONFIGURING GATE3 MACRO WITH POWER PMAC

Phase and Servo Clock Direction

Phase Clock Frequency

Configuring Gate3 MACRO with Power PMAC 2

Servo Clock Frequency

The equation for Gate3[i].ServoClockDiv is

Configuring Gate3 MACRO with Power PMAC 3

Hardware Clock Frequencies

 Gate3[i].AdcAmpClockDiv — Bit clock for amplifier A/D converters

Gate3[i].xxxClockDiv Divisor Frequency Setting Divisor Frequency

Example Clock Settings

Configuring Gate3 MACRO with Power PMAC 4

MACRO Communication Registers

Nodes and Addressing

Configuring Gate3 MACRO with Power PMAC 5

Gate3[i].MacroInB[j][k] is just like Gate3[i].MacroInA[j][k] but for MACRO bank “B.”

Gate3[i].MacroOutB[j][k] is just like Gate3[i].MacroOutA[j][k] but for MACRO bank “B.”

Configuring Gate3 MACRO with Power PMAC 6

Data Organization within Servo Nodes

Analog Output Mode

UV Commutation Mode (a.k.a. Sinusoidal Commutation Mode)

Direct PWM Mode

Gate3[i].MacroInA[j][0] 24 bits of feedback information 8 bits of 0

Not Used in Analog Output Mode/

Gate3[i].MacroInA[j][3] 16 bits of channel status/flag information 16 bits of 0

24 bits of servo output command in Analog Output Mode/

Gate3[i].MacroOutA[j][3] 16 bits of channel control commands/flag commands 16 bits of 0

Configuring Gate3 MACRO with Power PMAC 7

Gate3[i].MacroInB[j][0] 24 bits of feedback information 8 bits of 0

Not Used in Analog Output Mode/

Gate3[i].MacroInB[j][3] 16 bits of channel status/flag information 16 bits of 0

24 bits of servo output command in Analog Output Mode/

Gate3[i].MacroOutB[j][3] 16 bits of channel control commands/flag commands 16 bits of 0

Configuring Gate3 MACRO with Power PMAC 8

MACRO Communication Setup Instructions

Enabling MACRO Nodes

Component Bits Hex Digit # Functionality

Configuring Gate3 MACRO with Power PMAC 9

Component Bits Hex Digit # Functionality

Configuring Gate3 MACRO with Power PMAC 10

Configuring MACRO Modes

Component Bits Hex Digit # Functionality

Configuring Gate3 MACRO with Power PMAC 11

Configuring Gate3 MACRO with Power PMAC 12

Component Bits Hex Digit # Functionality

Configuring Gate3 MACRO with Power PMAC 13

MACRO Error Testing Variables

Example MACRO Communication Setup

//MACRO Communication Setup

Macro.TestPeriod=10/Sys.ServoPeriod; // MACRO Ring Check Period [servo cycles]

Configuring Gate3 MACRO with Power PMAC 14