Metal-gate FinFET and fully-depleted SO1 devices using total gate silicidation

Jakub Kedzierski, Edward Nowak", Thomas Kanarsky', Ying Zhang, Diane Boyd', Roy Carmthers, Cyril Cabral, Rick Amos,
Christian Lavoie, Ronnen Roy, Joseph N y b u r y , Elizabeth Sullivan, lo? Benedict, Philip Saunders, Keith y n i , D. Canaperi,
M. Krishnan, K:L. Lee, Beth A. Rainey ,David Fried", Peter Cottrell ,H . 3 . Philip Wong, Meikei leong , Wilfried Haensch

IBM Semiconductor Research and Development Center (SRDC)

Research Division, T J Watson Research Center Yorktown Heights NY 10598,
*Microelectronics Division, Hopewell Junction, NY 12533
**Microelectronics Division, Essex Junction VT, 05452; e-mail: jakub@us.ibm.com; phone: 9 14-945-3796

Abstract Poly-Si gated(PG) FinFETs had the same structure, except the
Metal-gate FinFET and FDSOI devices were fabricated using gate was formed from degenerately doped poly-Si[2]. FinFETs
total gate silicidation. Devices satisfy the following metal-gate were fabricated down to IOOnm gate lengths, with To, of
technology requirements: ideal mobility, low gate leakage, 1.6nm, and a fin thickness of 25nm. Both the PG and MG
high transconductance, competitive Ion/lo~,and adjustable Vt. FinFETs were oriented in the < I IO> direction, and had high tilt
Six silicide gate materials are presented, as well as two silicide extension implants. Fig. 1 shows a fin cross section TEM of a
workfunction engineering methods. MG FinFET with a conformal Nisi gate.
Long channel FDSOI devices with To, of 2.3nm were also
Introduction fabricated with poly-Si and silicide gates. Fig. 6 shows a
Thin body double-gated FinFETs[l,Z], and fully depleted TEM of a MG FDSOI device. Neither the MG nor the PG
silicon on insulator(FDSO1) devices[3] have been devices in this study had body, well, or halo implants to control
demonstrated to have better scalability than traditional bulk Vt. Vt control was achieved through silicide @, engineering.
transistors. Correct threshold voltage(Vt) in thin body FETs
can be achieved by using doped poly-Si gates, and body Electrical results
doping[4]. An alternative method of controlling Vt, Fig. 2, 3, and 4, show the Id-Vg, Id-Vd, and G, plots for the
demonstrated in this work, is to use metal gates with the proper CMOS MG FinFETs using Nisi as the gate material. The
workfunctions(@,) and leave the body undoped[5]. The metal FinFET drain currents are normalized by W=ZxHfi.. 0, is
gate approach eliminates poly-Si depletion, and increases given relative to poly-Si conduction and valance bands, as
effective carrier mobility by significantly reducing the Qmc and @ ", respectively, by measuring the threshold voltage
transverse field at the same gate overdrive. Both factors shift between doped poly-Si and silicide gated devices. If a
enhance on-current. single @, is achieved for the MG nFETs and pFETs then
In this work, metal gated FinFETs were fabricated using total
@,c+@,,,v=l.leV, However, for this device design, a single
gate silicidation[6]. High performance and the correct Vt were
midgap @ ,,, would give device threshold voltages that are too
achieved by combining a metal gate of the proper a,,,, with a
high. Different @, values were obtained for the MG FinFETs
selective epitaxy raised sourceidrain. FinFETs with poly-Si
gates were fabricated as controls. FDSOI devices were also by appropriately doping the poly-Si prior to silicidation. An
effect of silicon substitutional doping in the poly-Si gate on
fabricated with metal gates and an undoped body, using: CoSi2,
Nisi @, has been recently reported in [7]. Fig. 4 shows the
COS, NiSi2, Nisi, PdSi, and C O ( I . ~ ) N ~ ( ~
Universal
) S ~ ~ . electron
10% G,,, gain achieved by the elimination of poly depletion.
and hole mobility was measured for silicide gates, gate leakage
was generally lower than poly-Si controls, and an improvement Fig. 5 shows the gate leakage current of the MG and PG
FinFETs. The MG nFET gate leakage is lower than the PG
in Ti,, and G, was verified. Silicide gate workfunction
engineering was achieved using both metal and silicon control even though it has a smaller Tinv Table I lists the
substitutional impurities. This, to our knowledge, is the first important FinFET device parameters.
time metal gates have been successfully integrated into double- Table 2 compares the MG FinFETs vs. published
gate devices. It is also the first time that metal gates have been manufacturing technologies[8-12], using Vdd of 1.25V. The
integrated into scaled CMOS devices with thin gate oxides, devices presented here at an early state of development are
universal channel mobilities, low gate leakage, appropriate very competitive with fully optimized technologies.
threshold voltages, and lon/Io~that is competitive with fully In a separate experiment FDSOI devices with various silicide
optimized manufacturing technologies. gates were fabricated. Fig. 7 shows the Id-Vg characteristics of
FDSOI devices with CoSi2 and Nisi gates formed on undoped
Device structure poly-Si. The reported drain currents are normalized by WIL,
Metal-gated(MG) FinFET devices were fabricated with an giving the drive per square of the channel area. As expected
undoped body, selective Si epitaxy raised source/drain(RSD), @mc+@mv for both silicides is equal to I.leV, the band gap of
CoSi2 on source/drain, and a fully silicided Nisi gate. A CMP poly-Si. Many silicides were tested as gate materials in the
step was used to separate the RSD and gate silicidations[6]. FDSOI structure. Table 3 summarizes some of their properties.

10.1.1
0-7803-7462-2102/$17.0002002 lEEE IEDM 241

Authorized licensed use limited to: Indian Institute Of Technology (Banaras Hindu University) Varanasi. Downloaded on October 07,2024 at 08:36:27 UTC from IEEE Xplore. Restrictions apply.
 0.01 3 - Dual4 Nisi Gate

Phosphorous
and Arsenic doped
Nisi Ow= 0.41eV
Nisi 9_=0.26eV

TSi=25nm
1E-8
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
I

Fig. ,: FinFET TEM, Section is taken perpendicular

fin direction. Tsi is 25nm, and Tox is 1.6nrn. (Figure is a
Fig. 2: Id-Vg of Nisi gated 4IO> directed FinFETs. Id-Vg of PG
devices is also shown. Drain currents are normalized by W=2xH where
composite assembled from TEMs taken at 3 magnifications) W is the electrical device width and H is the fin height.

Fig. 3: Id-Vd ofNiSi gated <1 IO> directed Fig. 4: Linear transconductance of poly-Si Table 1: Comparison of Nisi gated
FinFETs. High performance is achieved with a and Nisi gated FinFETs. The elimination and doped polysilicon gated FinFET
Tox=l.6nm and Si epitaxy raised source-drain. of Poly depletion leads to higher characteristics. Lin values are give at
performance of the metal-gated devices. Vd=O.lV,satvaluesatVd=lSV.

FinFET gate leakage

# p . ,f
-"'-'
0.11. I ,

-0'' O'O
v- M-
Y -
, I , I

"O
, I

I.'
Table 2: Benchmarks of the FinFET devices with undoped body and Nisi
gates vs. optimized manufacturing technologies. Vdd is reduced for
FinFET from 1.5V to 1.25V to facilitate technolow. cornoarison. K
I, 1

Fig. 5: FinFET gate leakage plot for poly-Si and Nisi FinFET device is hampered by the (0 I I ) oxide plane, devices fabricated on
T~~ is I,6nm in both cases, however ~i~~ and the (001) plane are expected to have higher performance. Ion and loff are
are not the same. normalized by W=2xH, where H is fin height.

10.1.2
248-IEDM

Authorized licensed use limited to: Indian Institute Of Technology (Banaras Hindu University) Varanasi. Downloaded on October 07,2024 at 08:36:27 UTC from IEEE Xplore. Restrictions apply.
 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
vm(v) va
Fig. 6 FDSOI device E M ,showing the Fig. 7: Id-Vg plots of Single-Om Nisi and CoSiZ gated FDSOI devices, and poly-Si
gated(PG) FDSOI controls. Body and gate is undoped in all cases. As expected the
coxNi~si2 gate, the "ndoped FDSol body, threshold shifts from poly-Si gated FDSOI controls add up to I.1V the band-gap ofpoly-
and the nitride spacer. Tox is 2 . 3 m . Si. Indicating that a single workfunction is achieved by both nFET and pFETdevices.

0
E, (MV/crn)

Table 3: Table of measured silicide work- Fig. 8: CV plot ofFDSOI devices with poly- Fig. 9: Mobility comparison for poly-Si
functions (Omc), threshold variation(aVt), and Si and CoSi2 gates. Significant reduction in and CoSi2 gates. Universal mobilities are
the silicide reaction temperature(Tr). and gate Tinv is observed with the CoSi2. obtained in both cases.
phosphorous doping level (Nd).

The CV measurement in Fig. 8 shows the elimination of the *uolv ,

depletion in the metal gate FDSOI devices. Tlov decreased by
0.8nm and 0.5nm in NMOS and PMOS respectively with the use
of a silicide gate. However, gate doping was not optimized in the
FDSOI experiment. It is expected that a silicide gate will reduce
T,",, by -0.4~1 in an optimized process.
Fig. 9 is a plot of the electron and hole mobilities for CoSi2 gated
devices, no mobility degradation was observed for any of the
tested silicides when the maximum process temperature after
formation was smaller the silicide reaction temperature.
Fig. 10 shows the Ig-Vg plot for the PG and MG FDSOI devices
with Nisi and CoSiz gates. Gate currents for these silicide gates
-1.5 -1.0 4.5 0.0 0.5 1.0 1.5 show virtually no variation fiom device to device. At IV&l.ZV
",0 the primary conduction mechanism is the tunneling of the
inverted carrier from the inversion layer into the gate. The other
Fig. 1 0 Gate current for poly-Si, Nisi, and CoSiZ gates. Three
random metal gate devices arc plotted per each line, indicating mechanism seen at /Vg1>1.2Vis tunneling ofthe opposite polarity
high reproducibility ofthe low leakage currents. camer fiom the gate into the non-inverted band.

10.1.3
IEDM 249

Authorized licensed use limited to: Indian Institute Of Technology (Banaras Hindu University) Varanasi. Downloaded on October 07,2024 at 08:36:27 UTC from IEEE Xplore. Restrictions apply.
 0.9, ,0.9 0.0 0.2 0.4 0.6 0.8 1.0
J
..... ..
0.8- - 0.8 -H"
M ~ ~ D I E ~ ~ j ...... .

e+ E-0.3
0 ' 4 i o . 5 5 S
0.50 2
m - 0.7

-
f
0.7-
0.6:
* - 0.6
0.45

, S l ~ I W l i+
0.5- P
- 0.5
lpMosl P
- 0.4
0.4- P 0.50
>-
0 FinFET Nisi Gate
0.2'I.I.I.I.1.8.(., 0.6 0.40
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 0.0 0.2 0.4 0.6 0.8 1.0
Gate Na(1E20 CmJ) Gate N, (1E20 cm") x for C O ~ , . ~Cosputter
,N~~
Fig. 11: Correlation between apparent Nisi gate workfunction Fig. 12: Vt and Omc for a Co(l-x)Ni(x)Si2 alloy silicide gated
and the amount of Si substitutionalgate doping. FDSOI devices as a function of as Ni to COratio. X-Error bars
give intra die Vt variation. Y-error bars give uncertainty of EDS
measurement.
Silicide worfunction engineering
The apparent silicide workfunction, Qm, can be engineered by however the range does not extend significantly above the
either modifying the bulk silicide workfunction or changing the silicon mid-gap energy. Therefore it is difficult to engineer an
electrical properties of the silicide gate-dielectric interface. undoped thin-body PMOS device with a low threshold voltage.
Two of the silicide Qm engineering methods investigated in It is likely the shift observed with this method is a change
this experiment yielded interesting results. In one, silicon in the actual bulk workfunction.
substitutional dopants such as arsenic, boron, and phosphorous,
were implanted into the poly-Si gate prior to silicidatinn. In the Conclusion
other, metal substitutional impurities were used to change the Total gate silicidation was found to be an excellent method for
chemical composition of the silicide. Specifically the integration of a metal gate into thin-body devices. The silicide
gate thin-body structures were found to have many of the
dependence of Om on x i n , the Co(l.,)Ni(,)Si2 gate was
necessary requirements for a successful technology including:
measured. The Ni-Co disilicide system was chosen because
high mobility, appropriate and tunable V,, low gate leakage,
Nisi2 and CoSi2 have identical crystal structures and are
high gate capacitance, and nearly ideal swing. At the current
completely miscible[l3].
technology node bulk device performance is already
Fig. 11 shows the measured Nisi DmCas a function of poly-Si significantly degraded by poly-Si depletion, non-ideal swing,
doping concentration prior to silicidation. Significant Qmc and low mobility caused by the high transverse field. The thin-
shift is observed over a range that is very useful for undoped body silicide-gate structures presented in this work offer a
thin-body threshold voltage control. Slightly different shift is solution to these problems.
observed in the FinFETs vs. the FDSOI devices. This is
probably due to the differences in anneals prior to silicide Acknowledgements
formation, or the presence of As in the FinFET gate. It seems The authors would like to thank the Advanced Semiconductor
unlikely that a small percentage concentration of Si Technology Center (ASTC), for fabrication support, and the
substitutional impurities significantly changes the bulk silicide Advanced Semiconductor Technology Lab (ASTL), for silicide
workfunction. It is more likely that the impurities segregate at formation support.
the silicide-dielectric interface and affect the surface
workfunction. The homogeneity of local-@, obtained through References:
this method is not clear. Initial results indicate that a non- [ I ] Y:K. Choi, et al., IEDMZOOI, p . 421424,2001
[2] J. Kedzienki, et al., IEDM2001, p . 437-440,2001
uniform chemical doping profile in the poly-Si results in a non- [3] R.Chau et al., IEDMZOOI, p. 621-624, 2001
homogeneous local-@,. The dependence of @, on poly-Si 141F.-L. Yang, etai., vLsIzoo2,p. 104-105,2002
doping is probably not unique to Nisi, however Nisi with its [ 5 ] L. Chang, el al., IEDM2000, p. 719-722,2000
[6] B.Tavel, el al., IEDM2001, p. 825-828,2001
low temperature of formation and low resistance is an excellent [7] M. Qin, elal.,JElecr.-chem. Soc., V. 148(5), p. G271,200l
gate material candidate. [E] S. Thompson, et al., IEDM2001, p. 257-260,200l
Fig. 12 shows the control in the silicide Qmc that was achieved [9] S:F. Huang, etal., IEDM2001,p. 237-240,2001
[IO] S. Parihar, etal., IEDMZOOI, p. 249-252, 2001
by varying x in a C0(l.~)Ni(~pi2 alloy. Co-Ni alloy silicide [ I I ] S. T*gi, el al., IEDM 2000, p. 567-570,2000
was formed by the reaction of a sputtered film of Co(l.x)Ni(x). [I21 H. Asanga,etal.,IEDM2OOO,p.571-574,2000
[I)] J. Beek, et al. J. Alloys Compd., V. 297, p. 137,2000
Some Qrnc control was observed in the resultant alloy silicide,

10.1.4
250-IEDM

Authorized licensed use limited to: Indian Institute Of Technology (Banaras Hindu University) Varanasi. Downloaded on October 07,2024 at 08:36:27 UTC from IEEE Xplore. Restrictions apply.