DESIGN RULE CHECK

The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The detected errors are displayed on the layout editor window as error markers, and the corresponding rule is also displayed in a separate window. The designer must perform DRC (in a large design, DRC is usually performed frequently - before the entire design is completed), and make sure that all layout errors are eventually removed from the mask layout, before the final design is saved.

This step is important because the violation of any design rules would result in a higher probability, and in some cases an absolute certainty, that the fabricated chip does not work as desired.

TIMING ANALYSIS
Timing analysis is an essential step in all phases of development of integrated circuits. Among the most important of these phases are the design, optimization, and testing. One of the most useful results from timing analysis is the determination if a specific design will operate at a desired speed. To guarantee this the largest propagation delay of the circuit must be less than the system clock cycle time. Many timing analysis tools have used the longest structural path in a circuit as an estimate of this delay. Unfortunately, the longest structural path is often unsensitizable. That is, for these paths there is no set of inputs that can cause a transition to propagate from the input to the output. Tools that report the structural longest path can overestimate the delay of a circuit. Modern digital circuit design is marked by a rapid increase in performance accompanied by a decrease in cost and time-tomarket. To attain these opposing goals designers are forced to turn to design tools to assist in the development of integrated circuits. Higher performance is achieved through decreased clock cycle times and more aggressive timing constraints. As a result, timing analysis tools must be more accurate in estimating the circuit delay. Modern high performance circuits are noted for having many paths of nearly equal length. The exact delay of these paths is dependent on

manufacturing process parameters and the operating environment. It is often impossible to determine a single path which bounds the delay of the circuit. Any path whose delay may exceed the clock speed under some set of process parameters and operating environment must be tested.

Layout versus Schematic (LVS)

Once the layout fulfills all the design rules, the next verification step follows. The netlist behind the layout view is extracted and compared to that of the schematic view. This is the Layout Versus Schematic (LVS) Check. Circuit extraction is performed after the mask layout design is completed, in order to create a detailed netlist (or circuit description) for the LVS and the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections (on various layers), as well as (usually) the parasitic resistances and capacitances that are inevitably present between these layers. Thus, the "extracted netlist" can provide a very accurate estimation of the actual device dimensions and device parasitics that ultimately determine the circuit performance. The extracted netlist file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (post-layout simulation). After the mask layout design of the circuit is completed and the underlying design extracted, the design should be checked against the schematic circuit description created earlier. The tool called "Layout-versus-Schematic (LVS) Check" will compare the original network with the one extracted from the mask layout, and prove that the two networks are indeed equivalent. The LVS step provides an additional level of confidence for the integrity of the design, and ensures that the mask layout is a correct realization of the intended circuit topology. Note that the LVS check only guarantees topological match. A successful LVS will not guarantee that the extracted circuit will actually satisfy the performance requirements. Any errors that may show up during LVS (such as unintended connections between transistors, or missing connections/devices, etc.) should be corrected in the mask layout before proceeding to post-layout simulation. Also note that the

extraction step must be repeated every time you modify the mask layout. A successful DRC ensures that the layout passes through the rules designed for faultless fabrication. However, it does not guarantee if it really represents the circuit you desire to fabricate. In our case, for an inverter, we really need a tool than can compare the connectivities of our layout with that of the schematic and ensure that it is really a layout for an inverter. One way Cadence does this is by generating an Hspice netlist file from the layout and comparing it with the netlist for the schematic. This is the essence of the LVS tool Post-Layout Simulation The parasitic capacitances extracted according to how your layout is designed might be critical in affecting the actual performance of your design. In order to get an idea of how the design would work from your layout, you should perform a post-layout simulation from the extracted view. The procedure is identical to that for simulating from the schematic view. The electrical performance of a full-custom design can be best analyzed by performing a postlayout simulation on the extracted circuit net-list. At this point, the designer should have a complete mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no violations. The detailed (transistor-level) simulation performed using the extracted net-list will provide a clear assessment of the circuit speed, the influence of ircuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due o signal delay mismatches. As can be guessed, this step is particulary important in circuits very ensitive to parasitics, such as wideband or RF circuits. If the results of post-layout simulation are not satisfactory, the designer should modify some of the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics. This may require multiple iterations on the design, until the post-layout simulation results satisfy the original design requirements. Finally, note that a satisfactory result in post-layout

simulation is still no guarantee for a completely successful product; the actual performance of the chip can only be verified by testing the fabricated prototype. Even though the parasitic extraction step is used to identify the realistic circuit conditions to a large degree from the actual mask layout, most of the extraction routines and the simulation models used in modern design tools have inevitable numerical limitations. This should always be one of the main design considerations, from the very beginning. After a successful LVS you will have two main cell views for the same circuit. The first one is the schematic view, which is your initial (ideal) design. The second is the extracted view, that is based on the layout, and in addition to the basic circuit includes the layout associated parasitic effects (if the proper switches were activated during extraction, see Fig.22). Since both of these views refer to the same circuit they can be interchanged.