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    Comparison

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    SATYA TECH

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    Comparison

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    SATYA TECH
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    Comparison

    Uploaded by

    SATYA TECH

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    © All Rights Reserved
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    of 1

    Logic Family (Silicon Technology) Introduction Features Limitations

    1. RTL - In common use before the development - Low speed, high power dissipation
    First logic family, require minimum number
    of ICs. Common Emitter Configuration. of transistors. Low fan out, poor noise immunity
    (Resistor Transistor Logic)
    Logic 1: 1-3.6 V and Logic 0: 0.2V Operating speed <4MHz.
    2. DCTL Direct coupled transistors. Simpler than RTL, easy to fabricate. Small logic swing, poor noise margin.
    (Direct Coupled Transistor Logic) Base resistors of RTL are removed. Fewer components hence economical. Current hogging
    Use diodes and transistors.
    First circuit configuration designed into IC.
    3. DTL Very small in size and high reliability at No low and constant output impedance
    - Input is fed through diodes followed by in both states.
    (Diode Transistor Logic) very low price.
    transistor at the output side.
    Greater fan out and improved noise margins.
    4. TTL Use all transistors totem pole output. Fast switching time, larger fan out. Large current spike when switching
    Function of diodes in DTL is performed Reduced silicon chip area. from low to high.
    (Transistor-Transistor Logic) by multi-emitter transistor at input Easy to interface with other logic families. - Less noise immunity (0.4V)
    - Merged Transistor Logic (MTL). High component density, less power
    5. IIL Both PNP and NPN transistors are used. dissipation.
    (Integrated Injection Logic) Low metal interconnection.
    Poor noise immunity.
    Designed around multi-collector
    inverting transistors. Used in MSI and LSI designs.
    Non saturated logic/Current mode logic. Require large silicon area, high power
    Non-Saturated Logic 6.ECL - Compliment output/eliminates the need
    Fastest logic family
    dissipation (high cost).
    ON - Active Mode of inverter. Used in very high frequency applications.
    (Emitter Coupled Logic) Inconvenient voltage levels.
    OFF Cut Off Mode No noise spikes, large fan out. Low noise margins.
    Logic 1: -0.8 and Logic 0: -1.7
    7.MOS Logic Use pMOS, nMOS or both with high
    packaging density. Lower power dissipation. Larger propagation due to high output
    MOS Logic Families (Metal Oxide Semiconductor Shorter rise and fall times. impedance.
    Unipolar Transistor Technology) Logic) - Easy to design and fabricate Large fan-out. Noise margin is around 1V.
    Less power drawn due to gate dielectric.

    Parameter RTL IIL DTL HTL TTL ECL MOS CMOS


    Basic Gate NOR NOR NAND NAND NAND OR-NOR NAND NOR-NAND
    Fan Out 5 Depends on Injector Current 8 10 10-20 25 20 20-50
    Power Dissipation 12 mW 6 nW -70 uW 8-12 mW 55 mW 10 mW 40-55 mW 0.2-10 mW 0.025-1.01 mW
    Noise Immunity Nominal Poor Good Excellent Very Good Poor Good Very Good
    Propagation Delay 12 nSec 25-30 nSec 30 nSec 4 nSec 10 nSec 1-2 nSec 300 nSec 70 nSec
    Clock Rate 8 MHZ 72 MHz 4 MHz 35 MHz +60 MHz 2 MHz 10 MHZ
    Speed X Power 144 Less than 1 300 100 100 60 70

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