TI-SN75LVCP601

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SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
SN75LVCP601 Two-Channel 6-Gbps SATA Redriver

1 Features 3 Description
•
1 1.5-, 3-, or 6-Gbps Two-Channel Redriver The SN75LVCP601 device is a dual-channel, single-
lane SATA redriver and signal conditioner supporting
• Integrated Output Squelch data rates up to 6 Gbps. The device complies with
• Programmable RX and TX Equalization and SATA physical link 2m and 3i specifications. The
De-Emphasis Width Control SN75LVCP601 operates from one 3.3-V supply and
• Power-Save Feature Lowers Power by >80% has 100-Ω line termination with a self-biasing feature,
in Auto Low-Power Mode making the device suitable for ac coupling. The inputs
incorporate an out-of-band (OOB) detector, which
• Low Power automatically squelches the output while maintaining
– <220 mW (Typ) a stable common-mode voltage compliant to the
– <50 mW (in Auto Low-Power Mode) SATA link. The device design also handles spread-
spectrum clocking (SSC) transmission per the SATA
– <5 mW (in Standby Mode) specification.
• Excellent Jitter and Loss Compensation
Capability to Over 24-Inch (61-cm) FR4 Trace The SN75LVCP601 device handles interconnect
losses at both its input and output. The input stage of
• 20-Pin 4-mm × 4-mm QFN Package each channel offers selectable equalization settings
• High Protection Against ESD Transient that are programmable to match the loss in the
– HBM: 10,000 V channel. The differential outputs provide selectable
de-emphasis to compensate for the expected
– CDM: 1,500 V distortion that the SATA signal experiences. The level
– MM: 200 V of equalization and de-emphasis settings depends on
• Pin-Compatible With LVCP412A and MAX4951 the length of interconnect and its characteristics. The
setting of signal control pins EQ1, EQ2, DE1, and
2 Applications DE2 controls both equalization and de-emphasis
levels.
• Notebooks
This device is hot-plug capable (requires the use of
• Desktops ac-coupling capacitors at differential inputs and
• Docking Stations outputs), thus preventing device damage under
• Servers device hot-insertion, in such cases as: async signal
plug or removal, unpowered plug or removal,
• Workstations
powered plug or removal, surprise plug or removal
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN75LVCP601 WQFN (20) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
R = SN75LVCP601
HDD
PC/WS MB
ICH
HDD
Dock Connector
ICH iSATA
connector
R eSATA
R eSATA Cable HDD
connector SATA 6G Host
(2m)
PC/Workstation eSATA Notebook Dock DT MB R
eSATA
Motherboard connector Cable Notebook Dock Desktop Main Board
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 17
2 Applications ........................................................... 1 8.1 Overview ................................................................. 17
3 Description ............................................................. 1 8.2 Functional Block Diagram ....................................... 17
4 Revision History..................................................... 2 8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 18
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 5 9 Application and Implementation ........................ 19
9.1 Application Information............................................ 19
6.1 Absolute Maximum Ratings ...................................... 5
9.2 Typical Application ................................................. 19
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5 10 Power Supply Recommendations ..................... 25
6.4 Thermal Information .................................................. 5 11 Layout................................................................... 25
6.5 Electrical Characteristics........................................... 6 11.1 Layout Guidelines ................................................. 25
6.6 Power Dissipation Characteristics ............................ 7 11.2 Layout Example .................................................... 26
6.7 Timing Requirements ................................................ 8 12 Device and Documentation Support ................. 27
6.8 Switching Characteristics .......................................... 8 12.1 Community Resources.......................................... 27
6.9 Typical Characteristics ............................................ 10 12.2 Trademarks ........................................................... 27
7 Parameter Measurement Information ................ 11 12.3 Electrostatic Discharge Caution ............................ 27
7.1 Jitter and VOD Results: Case 1 at 6 Gbps ............. 12 12.4 Glossary ................................................................ 27
7.2 Jitter and VOD Results: Case 2 at 3 Gbps ............. 13 13 Mechanical, Packaging, and Orderable
7.3 Jitter and VOD Results: Case 3 at 1.5 Gbps .......... 15 Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2016) to Revision H Page
• Changed pin DE1 number From: 8 To: 9 in the Pin Functions table .................................................................................... 4
• Changed pin DE2 number From: 9 To: 8 in the Pin Functions table .................................................................................... 4
Changes from Revision F (June 2015) to Revision G Page
• Changed Pin 8 name To: DE2 and Pin 9 name To: DE1 in Figure 27 ............................................................................... 20
Changes from Revision E (January 2014) to Revision F Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Added Storage temperature to the Absolute Maximum Ratings table ................................................................................... 5
• Moved timing parameters out of Electrical Characteristics and into Timing Requirements .................................................. 8
• Moved switching parameters out of Electrical Characteristics and into Switching Characteristics ....................................... 8
Changes from Revision D (January 2013) to Revision E Page
• Changed DJTX (UI = 333 ps) From: Max = 0.19 To: Max = 0.07 ........................................................................................... 8
• Changed DJTX (UI = 167 ps) From: Max = 0.34 To: Max = 0.16 ........................................................................................... 8
Changes from Revision C (October 2012) to Revision D Page
• Corrected formatting of the Differential output-voltage swing dc level section of the Electrical Characteristics table ........... 7
2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601

SN75LVCP601
www.ti.com SLLSE41H – JUNE 2010 – REVISED MARCH 2016
Changes from Revision B (February 2012) to Revision C Page
• Deleted DiffVppTX row............................................................................................................................................................... 7

• Inserted DiffVppTX_DE row ......................................................................................................................................................... 7
• Changed Figure 5 caption .................................................................................................................................................... 10
• Revised text of the Output Ed-Emphasis section ................................................................................................................. 18
• Deleted setting recommendations on pulse durations for DEW1 and DEW2 ...................................................................... 18
Changes from Revision A (October 2011) to Revision B Page
• Changed pin type from CML to VML for pins 4, 5, 14, 15 in the Pin Functions table ............................................................ 4
Changes from Original (June 2010) to Revision A Page
• Changed pin EN number From: 4 To: 7 in the Pin Functions table ....................................................................................... 4
Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

SN75LVCP601
5 Pin Configuration and Functions
RTJ Package
16-Pin WQFN With Thermal Pad
Bottom View Top View
2 RX2N
111 RX2P
14 TX1N
15 TX1P
RX1N
RX1P
TX2N
TX2P
13 GND
GND
12
1
1
VCC 20 6 DEW 2 DEW 1 16 10 VCC
LVCP601RTJ
EQ 2 19 Thermal Pad must
7
EN EQ 1 17 9
DE 1
be soldered to PCB
GND 18
GND plane for
8
DE 2 GND 18 LVCP601RTJ 8 DE 2
efficient thermal
EQ 1 17 9
DE 1 EQ 2 19 7 EN
performance
DEW 1 16 10 VCC VCC 20 6 DEW 2
TX1P 15
TX1N 14
GND 13
RX2N 12
RX2P 11
5
RX1N
RX1P
GND
TX2N
TX2P
Pin Functions
PIN
PIN TYPE DESCRIPTION
NAME NO.
CONTROL PINS
DE1 (1) 9 Selects de-emphasis settings for CH 1 and CH 2 per Table 1.
I, LVCMOS
DE2 (1)
8 Internally tied to VCC / 2.
DEW1 16 De-emphasis width control for CH 1 and CH 2.
I, LVCMOS 0 = De-emphasis pulse duration, short
DEW2 6 1 = De-emphasis pulse duration, long (default)
Device enable and disable pin, internally pulled to VCC.
EN 7 I, LVCMOS 0 = Device in standby mode
1 = Device enabled (default)
EQ1 (1) 17 Selects equalization settings for CH 1 and CH 2 per Table 1.
I, LVCMOS
EQ2 (1)
19 Internally tied to VCC / 2.
HIGH-SPEED DIFFERENTIAL I/O
RX1N 2 I, CML
RX1P 1 I, CML Noninverting and inverting CML differential input for CH 1 and CH 2. These pins
RX2N 12 I, CML connect to an internal voltage bias via a dual-termination resistor circuit.
RX2P 11 I, CML
TX1N 14 O, VML
TX1P 15 O, VML Noninverting and inverting VML differential output for CH 1 and CH 2. These pins
TX2N 4 O, VML connect internally to voltage bias via termination resistors.
TX2P 5 O, VML
POWER
GND 3, 13, 18 Power Supply ground
VCC 10, 20 Power Positive supply must be 3.3 V ± 10%
(1) Internally biased to VCC / 2 with >200-kΩ pullup or pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be
<1 µA; otherwise, drive to VCC / 2 to assert mid-level state.

SN75LVCP601
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range (2) –0.5 4 V
Differential I/O –0.5 4 V
Voltage range
Control I/O –0.5 VCC + 0.5 V
See Power Dissipation
Continuous power dissipation
Characteristics
Tstg Storage temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±10000
Charged-device model (CDM), per JEDEC specification JESD22-
V(ESD) Electrostatic discharge ±1500 V
C101 (2)
(3)
Machine model ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Tested in accordance with JEDEC Standard 22, Test Method A115-A.
6.3 Recommended Operating Conditions

typical values for all parameters are VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
CCOUPLING Coupling capacitor 12 nF
Operating free-air temperature 0 85 °C
6.4 Thermal Information

SN75LVCP601
THERMAL METRIC (1) RTJ (WQFN) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 38 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 40 °C/W
RθJB Junction-to-board thermal resistance 10 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 0.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 15.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

SN75LVCP601
6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE PARAMETERS
DEWx = EN = VCC, EQx = DEx = NC, K28.5
PD Power dissipation in active mode 215 288 mW
pattern at 6 Gbps, VID = 700 mVp-p
Power dissipation in standby EN = 0 V, DEWx = EQx = DEx = NC, K28.5
PSD 5 mW
mode pattern at 6 Gbps, VID = 700 mVp-p
EN = 3.3 V, DEWx = 0 V, EQx = DEx = NC,
ICC Active-mode supply current 65 80 mA
K28.5 pattern at 6 Gbps, VID = 700 mVp-p
When device is enabled and auto low-power
ICC_ALP Acive power-save mode ICC 6.5 10 mA
conditions are met
ICC_STDBY Standby mode supply current EN = 0 V 1 mA
Maximum data rate 1 6 Gbps
OUT-OF-BAND (OOB)
VOOB Input OOB threshold f = 750 MHz 50 78 150 mVpp
DVdiffOOB OOB differential delta 25 mV
DVCMOOB OOB common-mode delta 50 mV
CONTROL LOGIC
VIH Input high voltage For all control pins 1.4 V
VIL Input low voltage 0.5 V
VINHYS Input hysteresis 115 mV
EQx, DEx = VCC 30
IIH High-level input current µA
EN, DEWx = VCC 1
EQx, DEx = GND –30
IIL Low-level input current µA
EN, DEWx = GND –10
RECEIVER AC/DC
ZDIFFRX Differential-input impedance 85 100 115 Ω
ZSERX Single-ended input impedance 40 Ω
VCMRX Common-mode voltage 1.8 V
f = 150 MHz to 300 MHz 18 28
f = 300 MHz to 600 MHz 14 17
RLDiffRX Differential-mode return loss (RL) f = 600 MHz to 1.2 GHz 10 12 dB
f = 1.2 GHz to 2.4 GHz 8 9
f = 2.4 GHz to 3 GHz 3 9
RXDiffRLSlope Differential-mode RL slope f = 300 MHz to 6 GHz (see Figure 1) –13 dB/dec
f = 150 MHz to 300 MHz 5 10
f = 300 MHz to 600 MHz 5 17
RLCMRX Common-mode return loss f = 600 MHz to 1.2 GHz 2 23 dB
f = 1.2 GHz to 2.4 GHz 1 16
f = 2.4 GHz to 3 GHz 1 12
VdiffRX Differential input voltage PP f = 1.5 GHz and 3 GHz 120 1600 mVppd
f = 150 MHz to 300 MHz 30 41
f = 300 MHz to 600 MHz 30 38
f = 600 MHz to 1.2 GHz 20 32
IBRX Impedance balance f = 1.2 GHz to 2.4 GHz 10 26 dB
f = 2.4 GHz to 3 GHz 10 25
f = 3 GHz to 5 GHz 4 20
f = 5 GHz to 6.5 GHz 4 17

SN75LVCP601
Electrical Characteristics (continued)

TRANSMITTER AC/DC
ZdiffTX Pair differential impedance 85 100 122 Ω
ZSETX Single-ended impedance 40 Ω
Transient voltages on the serial data bus
VTXtrans Sequencing transient voltage –1.2 1.2 V
during power sequencing (lab load)
f = 150 MHz to 300 MHz 14 24
f = 300 MHz to 600 MHz 8 19
RLDiffTX Differential-mode return loss f = 600 MHz to 1.2 GHz 6 14 dB
f = 1.2 GHz to 2.4 GHz 6 10
f = 2.4 GHz to 3 GHz 3 10
TXDiffRLSlope Differential-mode RL slope f = 300 MHz to 3 GHz (see Figure 1) –13 dB/dec
f = 150 MHz to 300 MHz 5 20
f = 300 MHz to 600 MHz 5 19
RLCMTX Common-mode return loss f = 600 MHz to 1.2 GHz 2 17 dB
f = 1.2 GHz to 2.4 GHz 1 12
f = 2.4 GHz to 3.0 GHz 1 11
f = 150 MHz to 300 MHz 30 41
f = 300 MHz to 600 MHz 30 38
f = 600 MHz to 1.2 GHz 20 33
IBTX Impedance balance f = 1.2 GHz to 2.4 GHz 10 24 dB
f = 2.4 GHz to 3 GHz 10 26
f = 3 GHz to 5 GHz 4 22
f = 5 GHz to 6.5 GHz 4 21
f = 3 GHz, DE1 or DE2 = 0 0
Output de-emphasis (relative to
DE f = 3 GHz, DE1 or DE2 = 1 –2 dB
transition bit)
f = 3 GHz, DE1 or DE2 = NC –4
f = 3 GHz, DE1 or DE2 = 0 550
Differential output-voltage swing
DiffVppTX_DE f = 3 GHz, DE1 or DE2 = 1 830 mV
dc level
f = 3 GHz, DE1or DE2 = NC 630
At 1.5 GHz 20 50 mVppd
VCMAC_TX TX AC CM voltage At 3 GHz 12 26 dBmV
At 6 GHz 13 30 (rms)
VCMTX Common-mode voltage 1.8 V
TxR/FImb TX rise-fall imbalance At 3 Gbps 6% 20%
TxAmpImb TX amplitude imbalance 2% 10%
6.6 Power Dissipation Characteristics

PARAMETER MIN MAX UNIT
PD Device power dissipation in active mode 215 288 mW
PSD Device power dissipation under standby mode 5 mW

SN75LVCP601
6.7 Timing Requirements

MIN NOM MAX UNIT
DEVICE PARAMETERS
AutoLPENTRY Auto low-power entry time Electrical idle at input (see Figure 4) 80 105 130 µs
AutoLPEXIT Auto low-power exit time After first signal activity (see Figure 4) 42 50 ns
TRANSMITTER AC/DC
DEW1 or DEW2 = 0 94
tDE De-emphasis duration ps
DEW1 or DEW2 = 1 215
OUT-OF-BAND (OOB)
tOOB1 OOB mode enter See Figure 4 3 5 ns
tOOB2 OOB mode exit See Figure 4 3 5 ns
6.8 Switching Characteristics

DEVICE PARAMETERS
tPDelay Propagation delay Measured using K28.5 pattern (see Figure 2) 323 400 ps
tENB Device enable time EN 0 → 1 5 µs
tDIS Device disable time EN 1 → 0 2 µs
RECEIVER AC/DC
Rise times and fall times measured between 20%
t20-80RX Rise/fall time and 80% of the signal. SATA 6-Gbps speed 62 75 ps
measured 1 in, (2.5 cm) from device pin.
Difference between the single-ended midpoint of
the RX+ signal rising or falling edge, and the
tskewRX Differential skew 30 ps
single-ended midpoint of the RX– signal falling or
rising edge.
TRANSMITTER AC/DC
Rise times and fall times measured between 20%
t20-80TX Rise/fall time and 80% of the signal. At 6 Gbps under no load 42 55 75 ps
conditions.
Difference between the single-ended mid-point of
the TX+ signal rising or falling edge, and the
tskewTX Differential skew 6 20 ps
single-ended mid-point of the TX– signal falling or
rising edge.
TRANSMITTER JITTER
Deterministic jitter (1) at CP in VID = 500 mVpp, UI = 333 ps,
DJTX 0.06 0.07 UIp-p
Figure 9 K28.5 control character
VID = 500 mVpp, UI = 333 ps,
RJTX Residual random jitter (1) 0.01 2 ps-rms
K28.7 control character
Deterministic jitter (1) at CP in VID = 500 mVpp, UI = 167 ps,
DJTX 0.08 0.16 UIp-p
Figure 9 K28.5 control character
VID = 500 mVpp, UI = 167 ps,
RJTX Residual random jitter (1) 0.09 2 ps-rms
K28.7 control character
(1) TJ = (14.1 × RJSD + DJ), where RJSD is one standard deviation value of RJ Gaussian distribution. Jitter measurement is at the SATA
connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect as shown
in Figure 9.

SN75LVCP601
IN+
50 mV Vcm
IN-
tOOB2 tOOB1
OUT+
Vcm
OUT-
Figure 1. TX, RX Differential Return Loss Limits Figure 2. OOB Enter and Exit Timing
IN
tPDelay tPDelay
OUT
Figure 3. Propagation Delay Timing Diagram
RX1,2P
VCMRX
RX1,2N
tOOB1
AutoLPEXIT
TX1,2P
VCMTX
TX1,2N
AutoLPENTRY Power Saving

Mode
Figure 4. Auto Low-Power Mode Enter and Exit Timing

SN75LVCP601
1-bit 1 to N bits 1-bit 1 to N bits

tDE
0 dB
-2 dB
-4 dB
DiffVppTX_DE
DiffVppTX
tDE
Figure 5. TX Differential Output
6.9 Typical Characteristics
14 0.8 40 0.8
Residual DJ 3Gbps
Residual DJ 6Gbps
12 0.7 35 Eye Opening 3Gbps 0.7
Eye Opening 6Gbps
30 0.6
10 0.6
Residual DJ (ps)
Eye Opening (V)

Residual DJ (ps)
Eye Opening (V)
25 0.5
8 0.5
20 0.4
6 0.4
15 0.3
4 0.3
10 0.2
Residual DJ 3Gbps
2 Residual DJ 6Gbps 0.2
5 0.1
Eye Opening 3Gbps
Eye Opening 6Gbps
0 0.1 0 0
2 4 6 8 10 12 14 16 18 20 22 2 4 6 8 10 12 14 16 18 20 22
Input Trace Length (in) Output Trace Length (in)
G001 G002
Figure 6. Residual DJ and Eye Opening Figure 7. Residual DJ and Eye Opening
vs Input Trace Length vs Output Trace Length

SN75LVCP601
7 Parameter Measurement Information

• Input signal characteristics
– Data rate = 6 Gbps, 3 Gbps, 1.5 Gbps
– Amplitude = 500 mVp-p
– Data pattern = K28.5
• SN75LVCP601 device setup
– Temperature = 25°C
– Voltage = 3.3 V
– De-emphasis duration = 117 ps (short)
– Equalization and de-emphasis set to optimize performance at 6 Gbps
With LVCP601
16-in., 4-mil (40.6-cm, 0.101-mm) 8-in., 4-mil (20.3-cm, 0.101-mm)
FR4 Trace + FR4 Trace +
2-in., 9.5-mil (5.05-cm, 0.241-mm) 2-in., 9.5-mil (5.05-cm, 0.241-mm)
Agilent FR4 Trace FR4 Trace Agilent
ParBERT LVCP601 DCA -J
TP1 TP2 TP3 TP4
EQ = 14 dB
DE = –2 dB
Without LVCP601
16-in., 4-mil (40.6-cm, 0.101-mm) FR4 Trace +
4-in., 9.5-mil (10.1-cm, 0.241-mm) FR4 Trace +
Agilent 8-in., 4-mil (20.3-cm, 0.101-mm) FR4 Trace Agilent
ParBERT DCA -J
TP1 TP4
Figure 8. Performance Curve Measurement Setup
Jitter
Measurement
CP
8" 6 mil Stripline
12" 6mil
Stripline
1
AWG*
2
CP AWG*
CP = Compliance point
Jitter
Measurement
Figure 9. Jitter Measurement Test Condition

SN75LVCP601
7.1 Jitter and VOD Results: Case 1 at 6 Gbps
TJ DJ RJ Eye Eye Eye TJ DJ RJ Eye Eye Eye

(1e-12) (σ-σ) (rms) Amplitude Width Opening (1e-12) (σ-σ) (rms) Amplitude Width Opening
ps ps ps mv ps mv ps ps ps mv ps mv
29.0 3.3 1.88 412.4 159.2 350.52 91.8 65.4 1.93 240 28.9 81.24
Figure 10. Test Point 1 Figure 11. Test Point 2

42.0 15.9 1.91 788.8 141.3 623.02 39.0 12.7 1.92 557.1 149.7 459.62
Figure 12. Test Point 3 Figure 13. Test Point 4 With LVCP601

SN75LVCP601
Jitter and VOD Results: Case 1 at 6 Gbps (continued)
TJ DJ RJ Eye Eye Eye

(1e-12) (σ-σ) (rms) Amplitude Width Opening
ps ps ps mv ps mv
56.7 29.8 2.00 165.4 101 13.24
Figure 14. Test Point 5 Without LVCP601
7.2 Jitter and VOD Results: Case 2 at 3 Gbps

29.7 3.8 1.89 430.9 326 392.84 72.7 46.8 1.89 314.9 237 222.36

SN75LVCP601
Jitter and VOD Results: Case 2 at 3 Gbps (continued)

39.6 12.8 1.96 714.5 321 611.62 47.9 20.3 1.99 615.3 305.0 463.42

ps ps ps mv ps mv
128.6 101.8 1.96 258.8 118 122.26

SN75LVCP601
7.3 Jitter and VOD Results: Case 3 at 1.5 Gbps

34.3 3.4 2.26 448 659 417.28 67.5 38.6 2.11 363.4 589 318.48

44.9 13.2 2.31 753.1 649 604.02 57.3 21.5 2.62 672.8 632.0 442.42

SN75LVCP601
Jitter and VOD Results: Case 3 at 1.5 Gbps (continued)

ps ps ps mv ps mv
113.3 81.9 2.30 322.8 493 217.46

SN75LVCP601
8 Detailed Description
8.1 Overview
The SN75LVCP601 device is a dual-channel, single-lane SATA redriver and signal conditioner supporting data
rates up to 6 Gbps.
This device complies with SATA physical link 2m and 3i specifications. The SN75LVCP601 device is designed to
handle interconnect losses at both its input and output. The input stage of each channel offers selectable
equalization settings that can be programmed to match the loss of the channel. The outputs provide selectable
de-emphasis to compensate for the distortion the SATA signal is expected to experience. The level of
equalization and de-emphasis settings depend on the length of interconnect and it’s characteristics. Equalization
for input trace and output trace are individually controlled by the setting of EQ1 and EQ2. De-emphasis levels for
input and output trace are individually controlled by the setting of DE1, DE2, DEW1 and DEW2 pins.
8.2 Functional Block Diagram
GND[3,13,18]
VBB = 1.7 V TYP

RT
RX1P [1] TX1P [15]
Equalizer
Driver
RT
RX1N [2] TX1N [14]
Detect
OOB
VBB
SN75LVCP601 RT
TX2N [4] RX2N [12]

Equalizer
Driver
RT
TX2P [5] RX2P [11]
Detect
OOB
DEW1 [16]
DEW2 [6] CTRL
EQ1[17] DE1[9] VCC[10,20]

EQ2[19] DE2[8]
EN[7]
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Data Flow Block Diagram

SN75LVCP601
8.3 Feature Description

8.3.1 Input Equalization
Each differential input of the SN75LVCP601 device has programmable equalization in its front stage. Table 1
lists the equalization. The input equalizer design recovers a signal even when no eye is present at the receiver,
and effectively supports FR4 trace at the input anywhere from 4 in. (10.2 cm) to 20 in. (50.8 cm) at SATA 6G
speed.
8.3.2 Output De-Emphasis

The SN75LVCP601 device provides the de-emphasis settings shown in Table 1. De-emphasis control is
independent for each channel, controlled by the DE1 and DE2 pin settings as shown in Table 1. The reference
for the de-emphasis settings available in the device is the transition bit amplitude for each given configuration;
this transition bit amplitude is different at 0 dB than the –2-dB and –4-dB settings by design. DEW1 and DEW2
control the DE durations for channels one and two, respectively. Table 1 lists the recommended settings for
these control pins. Output de-emphasis is capable of supporting FR4 trace at the output anywhere from
2 in. (5.1 cm) to 12 in. (30.5 cm) at SATA 3G/6G speed.
Table 1. TX and RX EQ and DE Pulse-Duration Settings

CH1 OR CH2
CH1 OR CH2 Equalization
DE1 OR DE2 DE-EMPHASIS EQ1 OR EQ2
dB (at 6 Gbps)
dB (at 6 Gbps)
NC (default) –4 NC (default) 0
0 0 0 7
1 –2 1 14
DEW1 OR DEW2 DEVICE FUNCTION → DE WIDTH FOR CH1/CH2
0 De-emphasis pulse duration, short
1 (default) De-emphasis pulse duration, long
8.3.3 Out-of-Band (OOB) Support

The squelch detector circuit within the device enables full detection of OOB signaling as specified in the SATA
specification. The device does not detect differential signal amplitude at the receiver input of 50 mVpp or less an
activity, and hence does not passed it to the output. The device detects differential signal amplitude of
150 mVp-p or more as an activity and therefore passes it to the output, providing an indication of the activity.
Squelch circuit ON or OFF time is 5 ns, maximum. While in squelch mode, outputs are held to VCM.
8.4 Device Functional Modes

8.4.1 Low-Power Mode
There are two low-power modes supported by the SN75LVCP601 device, listed as follows:
1. Standby mode (triggered by the EN pin, EN = 0 V)
– The enable (EN) pin controls th low-power mode. Pulling this pin LOW puts the device in standby mode
within 2 µs (max). In this mode, the device drives all its active components to their quiescent level, and
differential outputs Hi-Z (open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode
to normal operation requires a maximum latency of 5 µs.
2. Auto low-power mode (triggered when a given channel is in the electrically idle state for more than 100 µs
and EN = VCC)
– The device enters and exits low-power mode by actively monitoring the input signal (VIDp-p) level on
each of its channels independently. When the input signal on either or both channels is in the electrically
idle state, that is, VIDp-p < 50 mV and stays in this state for >100 µs, the associated channel enters into
the low-power state. In this state, output of the associated channel goes to VCM and the device
selectively shuts off some circuitry to lower power by >80% of its normal operating power. Exit time from
the auto low-power mode is <50 ns.

SN75LVCP601
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The SN75LVCP601 is a dual-channel SATA redriver and signal conditioner supporting data rates of 6 Gbps. The
inputs incorporate an OOB (out-of-band) detector, which automatically squelches the output while maintaining a
stable common-mode voltage compliant to the SATA link.
R = SN75LVCP601
HDD
Dock Connector
ICH
eSATA
R eSATA Cable
connector
(2m)
Notebook Dock
Notebook Dock
Figure 26. Typical SN75LVCP601 Placement in the System
9.2 Typical Application

This typical application describes how to configure the EQ, DE, and DEW configuration pins of the
SN75LVCP601 device based on board trace length between the SATA Host and the SN75LVCP601 and the
SN75LVCP601 and SATA Device. Actual configuration settings may differ due to additional factors such as
board layout, trace widths, and connectors used in the signal path.

SN75LVCP601
Typical Application (continued)
DEW1
EQ2
EQ1
3.3 V
1.0 mF
1.0 mF
1.0 mF
Vcc
20
17
16
19
18
10 nF
10 nF
SATA Host 1 RX1P TX1P 15
2 14
Connector
RX1N TX1N
10 nF
SATA
10 nF
3 LVCP 601 RTJ 13
10 nF 10 nF
4 TX2N RX2N 12
5 TX2P RX2P 11
10 nF 10 nF
Vcc 10
6
8
DE1 9
DE2
DEW2
EN Copyright © 2016, Texas Instruments Incorporated
(1) Place supply capacitors close to device pin.

(2) With no external control is implemented, one can leave EN open or tie it to the supply .
(3) Output de-emphasis setting is for –2 dB, EQ for 7 dB, and DE duration for SATA I/II/III operation for both channels.
(4) Actual EQ/DE duration settings depend on device placement relative to host and SATA connector.
Figure 27. Typical Device Implementation
9.2.1 Design Requirements

Typically, system trace length from the SATA host to the SN75LVCP601 device and trace length from the
SN75LVCP601 device to a SATA device differ and require different equalization and de-emphasis settings for
the host side and device side.
For example:
• A system with a 6-inch trace from the SN75LVCP601 device to a SATA host may set EQ1 (Rx1±) to 7 dB,
and DE2 (Tx2±) to –2 dB and DEW2 (Tx2±) to long pulse duration.
• The same system with a 1-inch trace from the SN75LVCP601 device to a SATA HDD may set EQ2 (Rx2±) to
0 dB, and DE1 (Tx1±) to 0 dB and DEW1 (Tx1±) to short pulse duration.
Refer to Application Curves for recommended EQ, DE and DEW settings based on trace length. It is highly
recommended to add both pullup- and pulldown-resistor options in the layout to fine-tune the settings if needed.
Input Signal Characteristics:
• Data Rate: 6 Gbps
• Pattern: PRBS7
• No pre-emphasis
• Signal amplitude: 500 mVp-p
• 18-inch SMA cable from test equipment to input and output trace

SN75LVCP601
Typical Application (continued)
Input Output
Lecroy PERT3 SN75LVCP601 25-GHz Scope
TP1 TP2 TP3 TP4
Figure 28. Measurement Set-up
9.2.2 Detailed Design Procedure
9.2.2.1 Equalization Configuration

Each differential input of the SN75LVCP601 device has programmable equalization in the front stage. The
equalization setting is shown in Table 2. The input equalizer is designed to recover a signal even when no eye is
present at the receiver and effectively supports FR4 trace input from 3 inches to greater than 24 inches at
SATA 6 Gbps speed.
Table 2. Equalization Settings

EQ1, EQ2 CH1, CH2 EQUALIZATION dB (AT 6 Gbps)
NC 0
0 7
1 14
9.2.2.2 De-emphasis Configuration

The SN75LVCP601 device provides the de-emphasis settings shown in Table 3. De-emphasis is controlled
independently for each channel and is set by the DE1, DE2, DEW1 and DEW2 pins of the SN75LVCP601
device. The recommended settings for these pins are listed in Application Curves. Output de-emphasis is
capable of supporting FR4 trace lengths at the output from 3 inches to 12+ inches at SATA 6 Gbps speed.
Table 3. De-emphasis Settings

DE1, DE2 CH1, CH2 DE-EMPHASIS dB (AT 6 Gbps)
0 0
1 –2
NC –4
Table 4. DE Width Control

DEW1, DEW2 DE-EMPHASIS WIDTH FOR CH1, CH2
0 Short de-emphasis pulse duration
1 Long de-emphasis pulse duration

SN75LVCP601
9.2.3 Application Curves
9.2.3.1 SN75LVCP601 Equalization Settings For Various Input Trace Lengths
Input Trace Length = 3 in. Input Trace Length = 3 in.

EQ1, EQ2 Setting = NC (0 dB) EQ1, EQ2 Setting = NC (0 dB)
Figure 29. Input Eye (TP2) Figure 30. Output Eye (TP4)

EQ1, EQ2 Setting = 0 (7 dB) EQ1, EQ2 Setting = 0 (7 dB)


SN75LVCP601




SN75LVCP601
9.2.3.2 SN75LVCP601 De-emphasis Settings For Various Output Trace Lengths
Output Trace Length = 0 in. Output Trace Length = 3 in.

DE1, DE2 Setting = 0 (0 dB) DE1, DE2 Setting = 0 (0 dB)
DEW1, DEW2 Setting = 0 (Short pulse duration) DEW1, DEW2 Setting = 0 (Short pulse duration)
Figure 41. Output Eye (TP4) Figure 42. Output Eye (TP4)
Output Trace Length = 6 in. Output Trace Length = 12 in.

DE1, DE2 Setting = 1 (–2 dB) DE1, DE2 Setting = 1 (–2 dB)
DEW1, DEW2 Setting = 1 (Long pulse duration) DEW1, DEW2 Setting = 1 (Long pulse duration)
Figure 43. Output Eye (TP4) Figure 44. Output Eye (TP4)
Output Trace Length = 12 in.

DE1, DE2 Setting = NC (–4 dB
DEW1, DEW2 Setting = 1 (Long pulse duration)
Figure 45. Output Eye (TP4)

SN75LVCP601
10 Power Supply Recommendations

The design of SN75LVCP601 device is for operation from one 3.3-V supply. Always practice proper power-
supply sequencing procedure. Apply VCC first, before application of any input signals to the device. The power-
down sequence is in reverse order.
11 Layout
11.1 Layout Guidelines

24 in. (61 cm)
SATA Host Redriver SATA

Connector
16 in. (40.6 cm) 8 in.

(20.3 cm)
Redriver on Motherboard
24 in. (61 cm)
SATA Host
Main Board
Redriver
SATA
Dock Board Connector
16 in. (40.6 cm) 8 in.

(20.3 cm)
Redriver on Dock Board
Example: Suggested trace-length values are values based on TI spice simulations (done over programmable limits of
input EQ and output de-emphasis) to meet SATA loss and jitter specification.
Actual trace length supported by the LVCP601 may be more or less than suggested values and depends on board
layout, trace widths, and number of connectors used in the SATA signal path.
Figure 46. Trace Length Example for LVCP601

SN75LVCP601
11.2 Layout Example
HIGH SPEED TRACES

LENGTH MATCHING
Figure 47. SN65LVCP601 EVM

SN75LVCP601
12 Device and Documentation Support
12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN75LVCP601RTJR ACTIVE QFN RTJ 20 3000 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR 0 to 85 LVC601
SN75LVCP601RTJT ACTIVE QFN RTJ 20 250 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR 0 to 85 LVC601
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75LVCP601RTJR QFN RTJ 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
SN75LVCP601RTJT QFN RTJ 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75LVCP601RTJR QFN RTJ 20 3000 367.0 367.0 35.0
SN75LVCP601RTJT QFN RTJ 20 250 210.0 185.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTJ 20 WQFN - 0.8 mm max height
4 x 4, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224842/A
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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SN75LVCP601 Two-Channel 6-Gbps SATA Redriver

Changes from Revision G (January 2016) to Revision H Page

Changes from Revision F (June 2015) to Revision G Page

Changes from Revision E (January 2014) to Revision F Page

Changes from Revision D (January 2013) to Revision E Page

Changes from Revision C (October 2012) to Revision D Page

2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated

Product Folder Links: SN75LVCP601

Changes from Revision B (February 2012) to Revision C Page

• Deleted DiffVppTX row............................................................................................................................................................... 7

Changes from Revision A (October 2011) to Revision B Page

Changes from Original (June 2010) to Revision A Page

Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Pin Configuration and Functions

4 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated

Product Folder Links: SN75LVCP601

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 5

6.5 Electrical Characteristics

6 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated

Product Folder Links: SN75LVCP601

Electrical Characteristics (continued)

6.6 Power Dissipation Characteristics

Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 7

6.7 Timing Requirements

6.8 Switching Characteristics

8 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated

Product Folder Links: SN75LVCP601

Figure 3. Propagation Delay Timing Diagram

AutoLPENTRY Power Saving

Figure 4. Auto Low-Power Mode Enter and Exit Timing

Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 9

1-bit 1 to N bits 1-bit 1 to N bits

Figure 5. TX Differential Output

6.9 Typical Characteristics

Eye Opening (V)

Eye Opening (V)

10 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated

Product Folder Links: SN75LVCP601

7 Parameter Measurement Information

TP1 TP2 TP3 TP4

Figure 8. Performance Curve Measurement Setup

Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 11

7.1 Jitter and VOD Results: Case 1 at 6 Gbps

TJ DJ RJ Eye Eye Eye TJ DJ RJ Eye Eye Eye

Figure 10. Test Point 1 Figure 11. Test Point 2

TJ DJ RJ Eye Eye Eye TJ DJ RJ Eye Eye Eye

12 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated

Product Folder Links: SN75LVCP601

Jitter and VOD Results: Case 1 at 6 Gbps (continued)

TJ DJ RJ Eye Eye Eye

Figure 14. Test Point 5 Without LVCP601

7.2 Jitter and VOD Results: Case 2 at 3 Gbps

TJ DJ RJ Eye Eye Eye TJ DJ RJ Eye Eye Eye

Figure 15. Test Point 1 Figure 16. Test Point 2

Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 13