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Assignment 10 Solutions

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Assignment 10 Solutions

Uploaded by

NAVEEN
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Week 10 Assignment 10

Solutions
____________________________________________________________________________

Question 1: Consider the statements below and select the correct option: [1]
Statement 1: Translation validation between the input C and RTL by HLS tool for few cases guarantees
the correctness of the HLS tool on any input.
Statement 2: Translation validation is a formal verification technique.
a. Statement 1 is true and Statement 2 is true
b. Statement 1 is true and Statement 2 is false
c. Statement 1 is false and Statement 2 is true
d. Statement 1 is false and Statement 2 is false
Answer c. Statement 1 is false and Statement 2 is true. Factual question

Question 2: To check the functional correctness of an HLS tool which of the following steps should be
performed [1]
Statement 1: Simulation based verification of the C input to HLS ensures the correctness of HLS.
Statement 2: Co-Simulation based verification of RTL generated by HLS ensures the correctness of HLS.

e. Statement 1 is true and Statement 2 is true


f. Statement 1 is true and Statement 2 is false
g. Statement 1 is false and Statement 2 is true
h. Statement 1 is false and Statement 2 is false
Answer c. Statement 1 is false and Statement 2 is true.
Explanation: Only verification of C input to HLS is not enough to ensure the correctness of HLS. Co-
simulation is required.

Question 3: Consider the two statements below and choose the correct option [1]
Statement 1: RTL co-simulation is slower compared to the corresponding C simulation for the same
implementation at RTL and C.
Statement 2: RTL co-simulation does analysis for each state of the design (at every clock).
a. Statement 1 is true and Statement 2 is the reason.
b. Statement 1 is false and Statement 2 is the reason.
c. Statement 1 is true and Statement 2 is not the reason.
d. Statement 1 is false and Statement 2 is not the reason.
Answer a. Statement 1 is true and Statement 2 is the reason.
Explanation: Since RTL Co-simulation analyses each state of the design and the corresponding C code it
is slower.

Question 4: RTL generated by HLS tools have a specific structure consisting of [1]
a. Only Datapath
b. Only Controller
c. Both datapath and controller
d. None of the above
Answer: c. Both a and b
Factual Question

Question 5: Answer true or false: [1]


If we replace the transitions in the controller state machine with the register-transfer operations for the
corresponding signals, we get a finite state machine with datapath (FSMD)
a. True
b. False
Answer: a. True. Factual Question

Question 6: Answer true or false: [1]


Formal methods can be used to guarantee that an HLS-generated RTL design is functionally equivalent to
its C source code.

a. True
b. False

Answer: a. True. Factual Question

Question 7: What are the challenges in the formal verification of HLS?


[1]
a. Difference in abstraction level of input C and output RTL.
b. Lot of optimizations are performed by HLS tool.
c. Both a and b
d. None of the above
Answer: c. Both a and b
Explanation: Due to the difference in abstraction levels at C and RTL and also the optimizations by HLS,
formal verification becomes difficult.

Question 8: Consider the following two Verilog code Snippets? Will the value of reg_A be the same in
both code snippets? [1]

Code Snippet 1 Code Snippet 2

reg [WIDTH_A - 1 : 0] reg_A; wire [(WIDTH_A - 1):0] temp_0,


reg [WIDTH_B - 1 : 0] reg_B; temp_1;
reg [WIDTH_C - 1 : 0] reg_C; assign temp_0 = reg_B << width_C;
assign reg_A = {{reg_B}, {reg_C}}; assign temp_1 = temp_0 | reg_C;
assign reg_A = temp_1;

a. Yes
b. No
Answer: a. Yes
Yes, the value of reg_A will be the same in both code snippets because in both cases reg_A is
effectively assigned the concatenation of reg_B and reg_C, with reg_B occupying the higher
bits and reg_C the lower bits.

9. Consider the Verilog code and its corresponding C code generated by reverse engineering.
Assume we sent the same value of x, y and m to the verilog module and C function. Which of
the following statements is correct? (2)

Verilog code C code

module func(x, y, m, a, c, clk); void func(int x, int y, int m) {


input [31:0] x, y, m; int a, c;
input clk; a = x + y;
output [31:0] a, c; c = a + m;
}
wire [31:0] b, d;

always @(posedge clk) begin


a <= b;
c <= d;
end

b = x + y;
d = a + m;

endmodule

a. The value of a and c will be the same in both code.


b. The value of a will match exactly but c will be different.
c. The value of a will not match but the value of c will be the same in both code.
d. The value of both a and c will be different in both codes.
Answer: b. The value of a will match but c will be different.

In the Verilog code, a and c are updated only on the rising edge of clk due to the always
@(posedge clk) block, which means their values are assigned after a clock cycle delay.
In the C code, a and c are computed sequentially without any delay.
Therefore, the value of a will match in both the Verilog and C code because it is directly
computed from x + y in both cases.
However, the value of c will differ because in Verilog, c is assigned the value of d (which
depends on a) only at the next clock cycle, whereas in C, c is computed immediately based on
the updated value of a. Thus, c will be different in the two implementations.

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