Processor Structure and

Function
CPE131-1: Computer Architecture and Organization

William Stallings
Computer Organization
and Architecture
8th Edition
CPU Structure
¤ CPU must:
▪ Fetch instructions
▪ Interpret instructions
▪ Fetch data
▪ Process data
▪ Write data
CPU With Systems Bus
CPU Internal Structure
Registers
¤ CPU must have some working space (temporary storage)
¤ Called registers
¤ Number and function vary between processor designs
¤ One of the major design decisions
¤ Top level of memory hierarchy
User Visible Registers
¤ General Purpose
¤ Data
¤ Address
¤ Condition Codes
General Purpose Registers
¤ May be true general purpose
¤ May be restricted
¤ May be used for data or addressing
¤ Data
▪ Accumulator
¤ Addressing
▪ Segment
General Purpose Registers
¤ Make them general purpose
▪ Increase flexibility and programmer options
▪ Increase instruction size & complexity
¤ Make them specialized
▪ Smaller (faster) instructions
▪ Less flexibility
How Many GP Registers?
¤ Between 8 - 32
¤ Fewer = more memory references
¤ More does not reduce memory references and takes up processor
real estate
How big?
¤ Large enough to hold full address
¤ Large enough to hold full word
¤ Often possible to combine two data registers
▪ C programming
▪ double int a;
▪ long int a;
Condition Code Registers
¤ Also called Status register or flag register
¤ Sets of individual bits
▪ e.g. result of last operation was zero
¤ Can be read (implicitly) by programs
▪ e.g. Jump if zero
¤ Can not (usually) be set by programs
Control & Status Registers
¤ Program Counter
¤ Instruction Decoding Register
¤ Memory Address Register
¤ Memory Buffer Register

¤ What do these all do?

Program Status Word
¤ A set of bits
¤ Includes Condition Codes
¤ Sign of last result
¤ Zero
¤ Carry
¤ Equal
¤ Overflow
¤ Interrupt enable/disable
¤ Supervisor
Supervisor Mode
¤ Intel ring zero
¤ Kernel mode
▪ Allows privileged instructions to execute
▪ Used by operating system
▪ Not available to user programs

Image from: By Hertzsprung at English Wikipedia, CC BY-SA 3.0,

https://commons.wikimedia.org/w/index.php?curid=8950144
Other Registers
¤ May have registers pointing to: (under Operating System)
▪ Process control blocks
▪ Interrupt Vectors

¤ Note: CPU design and operating system design are closely linked
Example Register Organizations
Instruction Cycle
¤ In a basic computer, each instruction cycle consists of the following
phases:
1. Fetch instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.

Image from:
https://www.javatpoint.com/instruction-cycle
Indirect Cycle
¤ May require memory access to fetch operands
¤ Indirect addressing requires more memory accesses
¤ Can be thought of as additional instruction subcycle
Instruction Cycle with Indirect
Instruction Cycle State Diagram
Data Flow (Instruction Fetch)
Sample MARIE program:
Input
Store X
¤ Depends on CPU design Input
Store Y
¤ In general:
Add X
Output
Halt
¤ Fetch
▪ PC contains address of next instruction X, DEC 0
▪ Address moved to MAR Y, DEC 0

▪ Address placed on address bus

▪ Control unit requests memory read
▪ Result placed on data bus, copied to MBR, then to IR
▪ Meanwhile PC incremented by 1
Data Flow (Data Fetch)
¤ IR is examined
¤ If indirect addressing, indirect cycle is performed
▪ Right most N bits of MBR transferred to MAR
▪ Control unit requests memory read
▪ Result (address of operand) moved to MBR
Data Flow (Fetch Diagram)
Data Flow (Indirect Diagram)
Data Flow (Execute)
¤ May take many forms
¤ Depends on instruction being executed
¤ May include
▪ Memory read/write
▪ Input/Output
▪ Register transfers
▪ ALU operations
Data Flow (Interrupt)
¤ Simple
¤ Predictable
¤ Current PC saved to allow resumption after interrupt
¤ Contents of PC copied to MBR
¤ Special memory location (e.g. stack pointer) loaded to MAR
¤ MBR written to memory
¤ PC loaded with address of interrupt handling routine
¤ Next instruction (first of interrupt handler) can be fetched
Data Flow (Interrupt Diagram)
Prefetch
¤ Fetch accessing main memory
¤ Execution usually does not access main memory
¤ Can fetch next instruction during execution of current instruction
¤ Called instruction prefetch
Improved Performance
¤ But not doubled:
▪ Fetch usually shorter than execution
▪ Prefetch more than one instruction?
▪ Any jump or branch means that prefetched instructions are not the required
instructions
¤ Add more stages to improve performance
Pipelining
¤ Fetch instruction
¤ Decode instruction
¤ Calculate operands (i.e. EAs)
¤ Fetch operands
¤ Execute instructions
¤ Write result

¤ Overlap these operations

Two Stage Instruction Pipeline
Timing Diagram for
Instruction Pipeline Operation
The Effect of a Conditional Branch on
Instruction Pipeline Operation
 Six Stage
Instruction Pipeline
Alternative Pipeline Depiction
Speedup Factors
with Instruction
Pipelining
Pipeline Hazards
¤ Pipeline, or some portion of pipeline, must stall
¤ Also called pipeline bubble
¤ Types of hazards
▪ Resource
▪ Data
▪ Control
Resource Hazards
¤ Two (or more) instructions in pipeline need same ¤ Ignore the cache
resource
¤ Operand read or write cannot be performed in
¤ Executed in serial rather than parallel for part of parallel with instruction fetch
pipeline
¤ Fetch instruction stage must idle for one cycle
¤ Also called structural hazard fetching I3
¤ E.g. Assume simplified five-stage pipeline
▪ Each stage takes one clock cycle ¤ E.g. multiple instructions ready to enter execute
¤ Ideal case is new instruction enters pipeline each instruction phase
clock cycle ¤ Single ALU
¤ Assume main memory has single port
¤ Assume instruction fetches and data reads and ¤ One solution: increase available resources
writes performed one at a time
▪ Multiple main memory ports
▪ Multiple ALUs
Data Hazards
¤ Conflict in access of an operand location ¤ ADD instruction does not update EAX
¤ Two instructions to be executed in sequence until end of stage 5, at clock cycle 5
¤ Both access a particular memory or register ¤ SUB instruction needs value at beginning
operand of its stage 2, at clock cycle 4
¤ If in strict sequence, no problem occurs ¤ Pipeline must stall for two clocks cycles
¤ If in a pipeline, operand value could be updated ¤ Without special hardware and specific
so as to produce different result from strict avoidance algorithms, results in
sequential execution
inefficient pipeline usage
¤ E.g. x86 machine instruction sequence:

¤ ADD EAX, EBX /* EAX = EAX + EBX

¤ SUB ECX, EAX /* ECX = ECX – EAX
Data Hazard Diagram
Types of Data Hazard
¤ Read after write (RAW), or true dependency ¤ Write after write (RAW), or output
▪ An instruction modifies a register or memory dependency
location ▪ Two instructions both write to same location
▪ Succeeding instruction reads data in that ▪ Hazard if writes take place in reverse of order
location intended sequence
▪ Hazard if read takes place before write complete
¤ Previous example is RAW hazard
¤ Write after read (RAW), or antidependency
▪ An instruction reads a register or memory
location
▪ Succeeding instruction writes to location
▪ Hazard if write completes before read takes
place
Resource Hazard
Diagram
Control Hazard
¤ Also known as branch hazard
¤ Pipeline makes wrong decision on branch prediction
¤ Brings instructions into pipeline that must subsequently be discarded
¤ Dealing with Branches
▪ Multiple Streams
▪ Prefetch Branch Target
▪ Loop buffer
▪ Branch prediction
▪ Delayed branching
Multiple Streams
¤ Have two pipelines
¤ Prefetch each branch into a separate pipeline
¤ Use appropriate pipeline

¤ Leads to bus & register contention

¤ Multiple branches lead to further pipelines being needed
Prefetch Branch Target
¤ Target of branch is prefetched in addition to instructions following
branch
¤ Keep target until branch is executed
¤ Used by IBM 360/91
Loop Buffer
¤ Very fast memory
¤ Maintained by fetch stage of pipeline
¤ Check buffer before fetching from memory
¤ Very good for small loops or jumps
¤ c.f. cache
¤ Used by CRAY-1
Loop Buffer Diagram
Branch Prediction
¤ Predict never taken
▪ Assume that jump will not happen
▪ Always fetch next instruction
▪ 68020 & VAX 11/780
▪ VAX will not prefetch after branch if a page fault would result (O/S v CPU
design)
¤ Predict always taken
▪ Assume that jump will happen
▪ Always fetch target instruction
Branch Prediction
¤ Predict by Opcode
▪ Some instructions are more likely to result in a jump than thers
▪ Can get up to 75% success
¤ Taken/Not taken switch
▪ Based on previous history
▪ Good for loops
▪ Refined by two-level or correlation-based branch history
¤ Correlation-based
▪ In loop-closing branches, history is good predictor
▪ In more complex structures, branch direction correlates with that of related branches
▪ Use recent branch history as well
Branch Prediction
¤ Delayed Branch
▪ Do not take jump until you have to
▪ Rearrange instructions
Branch Prediction Flowchart
Branch Prediction State Diagram
Dealing With
Branches
Intel 80486 Pipelining
¤ Fetch ¤ Decode stage 2
▪ From cache or external memory ▪ Expand opcode into control signals
▪ Put in one of two 16-byte prefetch buffers ▪ Computation of complex address modes
▪ Fill buffer with new data as soon as old data ¤ Execute
consumed
▪ ALU operations, cache access, register update
▪ Average 5 instructions fetched per load
▪ Independent of other stages to keep buffers ¤ Writeback
full ▪ Update registers & flags
¤ Decode stage 1 ▪ Results sent to cache & bus interface write
buffers
▪ Opcode & address-mode info
▪ At most first 3 bytes of instruction
▪ Can direct D2 stage to get rest of instruction
80486 Instruction Pipeline Examples
Pentium 4 Registers
EFLAGS Register
Control Registers
MMX Register Mapping
¤ MMX uses several 64 bit data types
¤ Use 3 bit register address fields
▪ 8 registers
¤ No MMX specific registers
▪ Aliasing to lower 64 bits of existing floating point registers
Mapping of MMX Registers to
Floating-Point Registers
Pentium Interrupt Processing
¤ Interrupts
▪ Maskable
▪ Nonmaskable
¤ Exceptions
▪ Processor detected
▪ Programmed
¤ Interrupt vector table
▪ Each interrupt type assigned a number
▪ Index to vector table
▪ 256 * 32 bit interrupt vectors
¤ 5 priority classes
ARM Attributes
¤ RISC ¤ Small number of addressing modes
¤ Moderate array of uniform registers ▪ All load/store addressees from registers
and instruction fields
▪ More than most CISC, less than many ▪ No indirect or indexed addressing
RISC involving values in memory
¤ Load/store model ¤ Auto-increment and auto-decrement
▪ Operations perform on operands in addressing
registers only
▪ Improve loops
¤ Uniform fixed-length instruction ¤ Conditional execution of instructions
▪ 32 bits standard set 16 bits Thumb minimizes conditional branches
¤ Shift or rotation can preprocess ▪ Pipeline flushing is reduced
source registers
▪ Separate ALU and shifter units
Simplified ARM Organization
ARM Processor Organization
¤ Many variations depending on ARM version
¤ Data exchanged between processor and memory through data bus
¤ Data item (load/store) or instruction (fetch)
¤ Instructions go through decoder before execution
¤ Pipeline and control signal generation in control unit
¤ Data goes to register file
▪ Set of 32 bit registers
▪ Byte & halfword twos complement data sign extended
¤ Typically two source and one result register
¤ Rotation or shift before ALU
ARM Processor Modes
¤ User
¤ Privileged
▪ 6 modes
▪ OS can tailor systems software use
▪ Some registers dedicated to each privileged mode
▪ Swifter context changes
¤ Exception
▪ 5 of privileged modes
▪ Entered on given exceptions
▪ Substitute some registers for user registers
▪ Avoid corruption
Privileged Modes
¤ System Mode ¤ Undefined mode
▪ Not exception ▪ Attempt instruction that is not supported by
▪ Uses same registers as User mode integer core coprocessors
▪ Can be interrupted by… ¤ Fast interrupt mode
¤ Supervisor mode ▪ Interrupt signal from designated fast interrupt
source
▪ OS
▪ Fast interrupt cannot be interrupted
▪ Software interrupt usedd to invoke operating
system services ▪ May interrupt normal interrupt

¤ Abort mode ¤ Interrupt mode

▪ memory faults ¤ Interrupt signal from any other interrupt
source
 Modes

Privileged modes

Exception modes

User System Supervisor Abort Undefined Interrupt Fast Interrupt

R0 R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2 R2
ARM R3 R3 R3 R3 R3 R3 R3
Register R4 R4 R4 R4 R4 R4 R4
Organization R5 R5 R5 R5 R5 R5 R5
Table R6 R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7 R7
R8 R8 R8 R8 R8 R8 R8_fiq
R9 R9 R9 R9 R9 R9 R9_fiq
R10 R10 R10 R10 R10 R10 R10_fiq
R11 R11 R11 R11 R11 R11 R11_fiq
R12 R12 R12 R12 R12 R12 R12_fiq
R13 (SP) R13 (SP) R13_svc R13_abt R13_und R13_irq R13_fiq
R14 (LR) R14 (LR) R14_svc R14_abt R14_und R14_irq R14_fiq
R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
CPSR CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq
ARM Register Organization
¤ 37 x 32-bit registers
¤ 31 general-purpose registers
▪ Some have special purposes
▪ E.g. program counters
¤ Six program status registers
¤ Registers in partially overlapping banks
▪ Processor mode determines bank
¤ 16 numbered registers and one or two program status registers visible
General Register Usage
¤ R13 normally stack pointer (SP)
▪ Each exception mode has its own R13
¤ R14 link register (LR)
▪ Subroutine and exception mode return address
¤ R15 program counter
CPSR
¤ CPSR process status register
▪ Exception modes have dedicated SPSR
¤ 16 msb are user flags
▪ Condition codes (N,Z,C,V)
▪ Q – overflow or saturation in some SMID instructions
▪ J – Jazelle (8 bit) instructions
▪ GEE[3:0] SMID use [19:16] as greater than or equal flag
¤ 16 lsb system flags for privilege modes
▪ E – endian
▪ Interrupt disable
▪ T – Normal or Thumb instruction
▪ Mode
ARM CPSR and SPSR
ARM Interrupt (Exception) Processing
¤ More than one exception allowed
¤ Seven types
¤ Execution forced from exception vectors
¤ Multiple exceptions handled in priority order
¤ Processor halts execution after current instruction
¤ Processor state preserved in SPSR for exception
▪ Address of instruction about to execute put in link register
▪ Return by moving SPSR to CPSR and R14 to PC
Foreground Reading
¤ Processor examples
¤ Stallings Chapter 12
¤ Manufacturer web sites & specs
Thank you for listening.