UNIT-II

COMBINATIONAL AND SEQUENTIAL CIRCUITS

INTRODUCTION:
The digital system consists of two types of circuits, namely
(i) Combinational circuits
(ii) Sequential circuits

Combinational circuit consists of logic gates whose output at any time is

determined from the present combination of inputs. The logic gate is the most basic
building block of combinational logic. The logical function performed by a
combinational circuit is fully defined by a set of Boolean expressions.
Sequential logic circuit comprises both logic gates and the state of storage
elements such as flip-flops. As a consequence, the output of a sequential circuit
depends not only on present value of inputs but also on the past state of inputs.
In the previous chapter, we have discussed binary numbers, codes, Boolean
algebra and simplification of Boolean function and logic gates. In this chapter,
formulation and analysis of various systematic designs of combinational circuits will
be discussed.
A combinational circuit consists of input variables, logic gates, and output
variables. The logic gates accept signals from inputs and output signals are
generated according to the logic circuits employed in it. Binary information from the
given data transforms to desired output data in this process. Both input and output
are obviously the binary signals, i.e., both the input and output signals are of two
possible states, logic 1 and logic 0.

Block diagram of a combinational logic circuit

For n number of input variables to a combinational circuit, 2 npossible

combinations of binary input states are possible. For each possible combination,
there is one and only one possible output combination. A combinational logic circuit
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can be described by m Boolean functions and each output can be expressed in terms
of n input variables.

DESIGN PROCEDURES:
Any combinational circuit can be designed by the following steps of design
procedure.
1. The problem is stated.
2. Identify the input and output variables.
3. The input and output variables are assigned letter symbols.
4. Construction of a truth table to meet input -output requirements.
5. Writing Boolean expressions for various output variables in terms of input
variables.
6. The simplified Boolean expression is obtained by any method of minimization—
algebraic method, Karnaugh map method, or tabulation method.
7. A logic diagram is realized from the simplified Boolean expression using logic
gates.

The following guidelines should be followed while choosing the preferred form
for hardware implementation:
1. The implementation should have the minimum number of gates, with the gates
used having the minimum number of inputs.
2. There should be a minimum number of interconnections.
3. Limitation on the driving capability of the gates should not be ignored.

Problems:
1. Design a combinational circuit with three inputs and one output. The output is 1
when the binary value of the inputs is less than 3. The output is 0 otherwise.
Solution:
Truth Table:
x y z F
0 0 0 1
0 0 1 1
2
 0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
K-map Simplification:

Logic Diagram:
The combinational circuit can be drawn as,

2. Design a combinational circuit with three inputs, x, y and z, and the three outputs,
A, B, and C. when the binary input is 0, 1, 2, or 3, the binary output is one greater
than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less
than the input.
Solution:
Truth Table:
Derive the truth table that defines the required relationship between inputs and
outputs.
x y z A B C
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 1 1
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 1 0 1 1 0 0
1 1 0 1 0 1
1 1 1 1 1 0

Obtain the simplified Boolean functions for each output as a function of the input
variables.
K-map for output A:

The simplified expression from the map is:A= xz+ xy+ yz

Logic Diagram:

K-map for output B:

The simplified expression from the map is: B= x’y’z+ x’yz’+ xy’z’+ xyz
Logic Diagram:

K-map for output C:

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The simplified expression from the map is:C=z’
Logic Diagram:

3. A majority circuit is a combinational circuit whose output is equal to 1 if the input

variables have more 1’s than 0’s. The output is 0 otherwise. Design a 3-input
majority circuit.
Solution:
Truth Table:
x y z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

K-map Simplification:

The simplified expression from the map is:xz+ yz+ xy

Logic Diagram:

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4. Design a combinational circuit that generates the 9's complement of a BCD digit.
Solution:
Truth Table:
Inputs Outputs
A B C D w x y z
0 0 0 0 1 0 0 1
0 0 0 1 1 0 0 0
0 0 1 0 0 1 1 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 0 0
0 1 1 0 0 0 1 1
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0

K-map Simplification:

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Logic Diagram:

ARITHMETIC CIRCUITS:
In this section, we will discuss those combinational logic building blocks that
can be used to perform addition and subtraction operations on binary numbers.
Addition and subtraction are the two most commonly used arithmetic operations, as
the other two, namely multiplication and division, are respectively the processes of
repeated addition and repeated subtraction.
The basic building blocks that form the basis of all hardware used to perform
the arithmetic operations on binary numbers are half-adder, full adder, half-
subtractor, full-subtractor.

Half-Adder:

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 A half-adder is a combinational circuit that can be used to add two binary bits.
It has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY.

Block schematic of half-adder

The truth table of a half-adder, showing all possible input combinations and the
corresponding outputs are shown below.
Truth Table:

Inputs Outputs
Sum Carry
A B
(S) (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
K-map simplification:

The Boolean expressions for the SUM and CARRY outputs are given by the
equations,
Sum, S = A’B+ AB’= AB
Carry, C = A.B
The first one representing the SUM output is that of an EX-OR gate, the second
one representing the CARRY output is that of an AND gate.
The logic diagram of the half adder is,

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 Logic Implementation of Half-adder

Full-Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three
input bits. It consists of three inputs and two outputs.
Two of the input variables, represent the significant bits to be added. The third
input represents the carry from previous lower significant position. The block
diagram of full adder is given by,

Block schematic of full-adder

The full adder circuit overcomes the limitation of the half-adder, which can be
used to add two bits only. As there are three input variables, eight different input
combinations are possible.

Truth Table:

Inputs Outputs
Sum
A B Cin Carry (Cout)
(S)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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K-map simplification:

The Boolean expressions for the SUM and CARRY outputs are given by the eqns.,

Carry, Cout= AB+ ACin + BCin .

Logic Diagram:

The logic diagram of the full adder can also be implemented with two half-
adders and one OR gate. The S output from the second half adder is the exclusive-
OR of Cin and the output of the first half-adder, giving
Sum =Cin(AB) [xy = x’y+ xy’]
=Cin (A’B+AB’)
= C’in (A’B+AB’) + Cin (A’B+AB’)’ [(x’y+xy’)’= (xy+x’y’)]
= C’in (A’B+AB’) + Cin (AB+A’B’)
= A’BC’in + AB’C’in + ABCin + A’B’Cin .

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and the carry output is,
Carry, Cout= AB+ Cin (A’B+AB’)
= AB+A’BCin+ AB’Cin
= B (A+A’Cin) + AB’Cin
= B (A+Cin) + AB’Cin
= AB + BCin+ AB’Cin
= AB + Cin (B + AB’)
= AB + Cin (A + B)
= AB+ ACin+ BCin.

Implementation of full adder with two half-adders and an OR gate

Half -Subtractor
A half-subtractoris a combinational circuit that can be used to subtract one
binary digit from another to produce a DIFFERENCE output and a BORROW output.
The BORROW output here specifies whether a ‘1’ has been borrowed to perform the
subtraction.

Block schematic of half-subtractor

The truth table of half-subtractor, showing all possible input combinations and
the corresponding outputs are shown below.

Inputs Outputs
Difference Borrow
A B
(D) (Bout)
0 0 0 0
0 1 1 1
1 0 1 0

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 1 1 0 0

K-map simplification:

The Boolean expressions for the DIFFERENCE and BORROW outputs are given
by the equations,
Difference, D = A’B+ AB’= AB
Borrow, Bout = A’ . B
The first one representing the DIFFERENCE (D)output is that of an exclusive-OR
gate, the expression for the BORROW output (Bout) is that of an AND gate with input
A complemented before it is fed to the gate.
The logic diagram of the half adder is,

Logic Implementation of Half-Subtractor

Comparing a half-subtractor with a half-adder, we find that the expressions for
the SUM and DIFFERENCE outputs are just the same. The expression for BORROW in
the case of the half-subtractor is also similar to what we have for CARRY in the case
of the half-adder. If the input A, ie., the minuend is complemented, an AND gate can
be used to implement the BORROW output.

Full Subtractor:
A full subtractorperforms subtraction operation on two bits, a minuend and a
subtrahend, and also takes into consideration whether a ‘1’ has already been
borrowed by the previous adjacent lower minuend bit or not.
As a result, there are three bits to be handled at the input of a full subtractor,
namely the two bits to be subtracted and a borrow bit designated as B in. There are

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two outputs, namely the DIFFERENCE output D and the BORROW output B o. The
BORROW output bit tells whether the minuend bit needs to borrow a ‘1’ from the
next possible higher minuend bit.

Block schematic of full- subtractor

The truth table for full-subtractor is,
Inputs Outputs
Difference( Borrow(Bo
A B Bin
D) ut)

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-map simplification:

The Boolean expressions for the DIFFERENCE and BORROW outputs are given
by the equations,

Borrow, Bout = A’B+ A’Bin + BBin .

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The logic diagram for the above functions is shown as,

Implementation of full- subtractor

The logic diagram of the full-subtractor can also be implemented with two half-
subtractors and one OR gate. The difference,D output from the second half
subtractor is the exclusive-OR of Bin and the output of the first half-subtractor, giving
Difference,D= Bin(AB) [x y = x’y+ xy’]
= Bin(A’B+AB’)
= B’in (A’B+AB’) + Bin (A’B+AB’)’ [(x’y+xy’)’= (xy+x’y’)]
= B’in (A’B+AB’) + Bin (AB+A’B’)
= A’BB’in + AB’B’in + ABBin + A’B’Bin .
and the borrow output is,
Borrow, Bout= A’B+ Bin (A’B+AB’)’ [(x’y+xy’)’= (xy+x’y’)]
= A’B+ Bin (AB+A’B’)
= A’B+ ABBin+ A’B’Bin
= B (A’+ABin) + A’B’Bin
= B (A’+Bin) + A’B’Bin
= A’B + BBin+ A’B’Bin
= A’B + Bin( B + A’B’)
= A’B + Bin (B+ A’)
= A’B+ BBin+ A’Bin.
Therefore,
We can implement full-subtractor using two half-subtractors and OR gate as,

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 Implementation of full-subtractor with two half-subtractors and an OR gate

Binary Adder (Parallel Adder)

The 4-bit binary adder using full adder circuits is capable of adding two 4-bit
numbers resulting in a 4-bit sum and a carry output as shown in figure below.

4-bit binary parallel Adder

Since all the bits of augend and addend are fed into the adder circuits
simultaneously and the additions in each position are taking place at the same time,
this circuit is known as parallel adder.

Let the 4-bit words to be added be represented by,

A3A2A1A0= 1111 and B3B2B1B0= 1011.

The bits are added with full adders, starting from the least significant position,
to form the sum it and carry bit. The input carry C 0 in the least significant position
must be 0. The carry output of the lower order stage is connected to the carry input
of the next higher order stage. Hence this type of adder is called ripple-carry adder.

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 In the least significant stage, A 0, B0 and C0 (which is 0) are added resulting in
sum S0 and carry C1. This carry C1 becomes the carry input to the second stage.
Similarly in the second stage, A1, B1 and C1 are added resulting in sum S1 and carry
C2, in the third stage, A2, B2 and C2 are added resulting in sum S 2 and carry C3, in the
third stage, A3, B3 and C3 are added resulting in sum S 3 and C4, which is the output
carry. Thus the circuit results in a sum (S 3S2S1S0) and a carry output (Cout).

Though the parallel binary adder is said to generate its output immediately
after the inputs are applied, its speed of operation is limited by the carry propagation
delay through all stages. However, there are several methods to reduce this delay.
One of the methods of speeding up this process is look-ahead carry addition
which eliminates the ripple-carry delay.

Carry Look Ahead Adder:

In Parallel adder, all the bits of the augend and the addend are available for
computation at the same time. The carry output of each full-adder stage is
connected to the carry input of the next high-order stage. Since each bit of the sum
output depends on the value of the input carry, time delay occurs in the addition
process. This time delay is called as carry propagation delay.
For example, addition of two numbers (1111+ 1011) gives the result as 1010.
Addition of the LSB position produces a carry into the second position. This carry
when added to the bits of the second position, produces a carry into the third
position. This carry when added to bits of the third position, produces a carry into the
last position. The sum bit generated in the last position (MSB) depends on the carry
that was generated by the addition in the previous position. i.e., the adder will not
produce correct result until LSB carry has propagated through the intermediate full-
adders. This represents a time delay that depends on the propagation delay
produced in an each full-adder. For example, if each full adder is considered to have
a propagation delay of 8nsec, then S 3 will not react its correct value until 24nsec
after LSB is generated. Therefore total time required to perform addition is 24+ 8 =
32nsec.

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 The method of speeding up this process by eliminating inter stage carry delay
is called look ahead-carry addition. This method utilizes logic gates to look at the
lower order bits of the augend and addend to see if a higher-order carry is to be
generated. It uses two functions: carry generate and carry propagate.

Full-Adder circuit
Consider the circuit of the full-adder shown above. Here we define two
functions: carry generate (Gi) and carry propagate (Pi) as,
Carry propagate, Pi = AiBi
Carry generate, Gi = Ai.Bi
the output sum and carry can be expressed as,
Si = PiCi
Ci+1 = Gi+Pi.Ci
Gi (carry generate), it produces a carry 1 when both Ai and Bi are 1, regardless of the
input carry Ci.Pi (carry propagate), is the term associated with the propagation of the
carry from Ci to Ci+1.
The Boolean functions for the carry outputs of each stage and substitute for
each Ci its value from the previous equation:
C0= input carry
C1= G0 + P0C0
C2= G1 + P1C1 = G1 + P1 (G0 + P0C0)
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 = G1 + P1G0 + P1P0C0
C3= G2 + P2C2 = G2 + P2 (G1 + P1G0 + P1P0C0)
= G2 + P2G1 + P2P1G0 + P2P1P0C0
Since the Boolean function for each output carry is expressed in sum of
products, each function can be implemented with one level of AND gates followed by
an OR gate. The three Boolean functions for C 1, C2 and C3 are implemented in the
carry look-ahead generator as shown below.

Logic diagram of Carry Look-ahead Generator

Note that C3 does not have to wait for C2 and C1 to propagate; in fact C3 is
propagated at the same time as C1 and C2.
Using a Look-ahead Generator we can easily construct a 4-bit parallel adder
with a Look-ahead carry scheme. Each sum output requires two exclusive-OR gates.
The output of the first exclusive-OR gate generates the P i variable, and the AND gate
generates the Gi variable. The carries are propagated through the carry look-ahead
generator and applied as inputs to the second exclusive-OR gate. All output carries

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are generated after a delay through two levels of gates. Thus, outputs S 1 through S3
have equal propagation delay times.

4-Bit Adder with Carry Look-ahead

Binary Subtractor (Parallel Subtractor)

The subtraction of unsigned binary numbers can be done most conveniently by
means of complements. The subtraction (A – B) can be done by taking the 2’s
complement of B and adding it to A. The 2’s complement can be obtained by taking
the 1’s complement and adding 1 to the least significant pair of bits. The 1’s
complement can be implemented with inverters and a 1 can be added to the sum
through the input carry.

The circuit for subtracting (A – B) consists of an adder with inverters placed

between each data input B and the corresponding input of the full adder. The input
carry C0 must be equal to 1 when performing subtraction. The operation thus
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performed becomes A, plus the 1’s complement of B, plus1. This is equal to A plus
the 2’s complement of B.
Let the 4-bit words to be subtracted be represented by,
A3A2A1A0= 1111 and B3B2B1B0= 1 011.

4-bit Parallel Subtractor

Parallel Adder/ Subtractor

The addition and subtraction operation can be combined into one circuit with
one common binary adder. This is done by including an exclusive-OR gate with each
full adder. A 4-bit adder Subtractor circuit is shown below.

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 4-Bit Adder Subtractor
The mode input M controls the operation. When M= 0, the circuit is an adder
and when M=1, the circuit becomes a Subtractor. Each exclusive-OR gate receives
input M and one of the inputs of B. When M=0, we have B0= B. The full adders
receive the value of B, the input carry is 0, and the circuit performs A plus B. When
M=1, we have B 1= B’ and C0=1. The B inputs are all complemented and a 1 is
added through the input carry. The circuit performs the operation A plus the 2’s
complement of B. The exclusive-OR with output V is for detecting an overflow.

MULTIPLEXER: (Data Selector)

A Multiplexeror MUX, is a combinational circuit with more than one input line,
one output line and more than one selection line. A multiplexer selects binary
information present from one of many input lines, depending upon the logic status of
the selection inputs, and routes it to the output line. Normally, there are 2 n input
lines and n selection lines whose bit combinations determine which input is selected.
The multiplexer is often labeled as MUX in block diagrams.
A multiplexer is also called a data selector, since it selects one of many
inputs and steers the binary information to the output line.

Block diagram of Multiplexer

2-to-1- line Multiplexer:

The circuit has two data input lines, one output line and one selection line, S.
When S= 0, the upper AND gate is enabled and I 0 has a path to the output.
When S=1, the lower AND gate is enabled and I 1 has a path to the output.

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 Logic diagram
The multiplexer acts like an electronic switch that selects one of the two sources.
Truth table:

S Y
0 I0
1 I1

4-to-1-line Multiplexer
A 4-to-1-line multiplexer has four (2 n) input lines, two (n) select lines and one
output line. It is the multiplexer consisting of four input channels and information of
one of the channels can be selected and transmitted to an output line according to
the select inputs combinations. Selection of one of the four input channel is possible
by two selection inputs.
Each of the four inputs I 0 through I3, is applied to one input of AND gate.
Selection lines S1 and S0 are decoded to select a particular AND gate. The outputs of
the AND gate are applied to a single OR gate that provides the 1-line output.

4-to-1-Line Multiplexer
Function table:

S1 S0 Y
0 0 I0
2
2
 0 1 I1
1 0 I2
1 1 I3
To demonstrate the circuit operation, consider the case when S 1S0= 10. The
AND gate associated with input I 2 has two of its inputs equal to 1 and the third input
connected to I2. The other three AND gates have atleast one input equal to 0, which
makes their outputs equal to 0. The OR output is now equal to the value of I 2,
providing a path from the selected input to the output.
The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0S1’S0’.
The data output is equal to I1 only if S1= 0 and S0= 1; Y= I1S1’S0.
The data output is equal to I2 only if S1= 1 and S0= 0; Y= I2S1S0’.
The data output is equal to I3 only if S1= 1 and S0= 1; Y= I3S1S0.
When these terms are ORed, the total expression for the data output is,
Y= I0S1’S0’+ I1S1’S0 +I2S1S0’+ I3S1S0.
As in decoder, multiplexers may have an enable input to control the operation
of the unit. When the enable input is in the inactive state, the outputs are disabled,
and when it is in the active state, the circuit functions as a normal multiplexer.

Quadruple 2-to-1 Line Multiplexer

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 This circuit has four multiplexers, each capable of selecting one of two input
lines. Output Y0 can be selected to come from either A0 or B0. Similarly, output Y1
may have the value of A1 or B1, and so on. Input selection line, S selects one of the
lines in each of the four multiplexers. The enable input E must be active for normal
operation.
Although the circuit contains four 2-to-1-Line multiplexers, it is viewed as a
circuit that selects one of two 4-bit sets of data lines. The unit is enabled when E= 0.
Then if S= 0, the four A inputs have a path to the four outputs. On the other hand, if
S=1, the four B inputs are applied to the outputs. The outputs have all 0’s when E=
1, regardless of the value of S.

Application:
1. They are used as a data selector to select out of many data inputs.

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 2. They can be used to implement combinational logic circuit.
3. They are used in time multiplexing systems.
4. They are used in frequency multiplexing systems.
5. They are used in A/D and D/A converter.
6. They are used in data acquisition systems.

Implementation of Boolean Function using MUX:

1. Implement the following boolean function using 4: 1 multiplexer,
F (A, B, C) = ∑m (1, 3, 5, 6).
Solution:
Variables, n= 3 (A, B, C)
Select lines= n-1 = 2 (S1, S0)
2n-1 to MUX i.e., 22 to 1 = 4 to 1 MUX
Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)
Implementation table:
Apply variables A and B to the select lines. The procedures for implementing the
function are:
i. List the input of the multiplexer
ii. List under them all the minterms in two rows as shown below.
The first half of the minterms is associated with A’ and the second half with
A. The given function is implemented by circling the minterms of the function and
applying the following rules to find the values for the inputs of the multiplexer.
1. If both the minterms in the column are not circled, apply 0 to the corresponding
input.
2. If both the minterms in the column are circled, apply 1 to the corresponding input.
3. If the bottom minterm is circled and the top is not circled, apply C to the input.
4. If the top minterm is circled and the bottom is not circled, apply C’ to the input.

Multiplexer Implementation:

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2. F (x, y, z) = ∑m (1, 2, 6, 7)
Implementation table:

Multiplexer Implementation:

3. F ( A, B, C) = ∑m (1, 2, 4, 5)
Solution:

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 Variables, n= 3 (A, B, C)
Select lines= n-1 = 2 (S1, S0)
2n-1 to MUX i.e., 22 to 1 = 4 to 1 MUX
Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)
Implementation table:

Multiplexer Implementation

4. F( A, B, C, D)= ∑m (0, 1, 3, 4, 8, 9, 15)

Solution:
Variables, n= 4 (A, B, C, D)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:

Multiplexer Implementation:

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5. Implement the Boolean function using 8: 1 and also using 4:1
multiplexer
F (A, B, C, D) = ∑m (0, 1, 2, 4, 6, 9, 12, 14)
Solution:
Variables, n= 4 (A, B, C, D)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:

Multiplexer Implementation (Using 8: 1 MUX)

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Using 4: 1 MUX:

6. F (A, B, C, D) = ∑m (1, 3, 4, 11, 12, 13, 14, 15)

Solution:
Variables, n= 4 (A, B, C, D)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:

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Multiplexer Implementation:

7. Implement the Boolean function using 8: 1 multiplexer.

F (A, B, C, D) = A’BD’ + ACD + B’CD + A’C’D.
Solution:
Convert into standard SOP form,
= A’BD’ (C’+C) + ACD (B’+B) + B’CD (A’+A) + A’C’D (B’+B)
= A’BC’D’ + A’BCD’+ AB’CD + ABCD +A’B’CD + AB’CD +A’B’C’D+ A’BC’D
= A’BC’D’ + A’BCD’+ AB’CD + ABCD +A’B’CD +A’B’C’D+ A’BC’D
= m4+ m6+ m11+ m15+ m3+ m1+ m5
= ∑m (1, 3, 4, 5, 6, 11, 15)
Implementation table:

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Multiplexer Implementation:

8. Implement the Boolean function using 8: 1 multiplexer.

F (A, B, C, D) = AB’D + A’C’D + B’CD’ + AC’D.
Solution:
= AB’D (C’+C) + A’C’D (B’+B) + B’CD’ (A’+A) + AC’D (B’+B)
= AB’C’D + AB’CD+ A’B’C’D + A’BC’D +A’B’CD’ + AB’CD’ +AB’C’D+ ABC’D
= AB’C’D + AB’CD+ A’B’C’D + A’BC’D +A’B’CD’ + AB’CD’+ ABC’D
= m9+ m11+ m1+ m5+ m2+ m10+ m13
= ∑m (1, 2, 5, 9, 10, 11, 13).
Implementation Table:

3
1
Multiplexer Implementation:

9. Implement the Boolean function using 8: 1 and also using 4:1 multiplexer
F (w, x, y, z) = ∑m (1, 2, 3, 6, 7, 8, 11, 12, 14)
Solution:
Variables, n= 4 (w, x, y, z)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:

Multiplexer Implementation (Using 8:1 MUX):

3
2
(Using 4:1 MUX)

10. Implement the Boolean function using 8: 1 multiplexer

3
3
 F (A, B, C, D) = ∏m (0, 3, 5, 8, 9, 10, 12, 14)
Solution:
Variables, n= 4 (A, B, C, D)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:

Multiplexer Implementation:

11. Implement the Boolean function using 8: 1 multiplexer

F (A, B, C, D) = ∑m (0, 2, 6, 10, 11, 12, 13) + d (3, 8, 14)
Solution:
Variables, n= 4 (A, B, C, D)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation Table:

3
4
Multiplexer Implementation:

DECODERS
A decoder is a combinational circuit that converts binary information from ‘n’
input lines to a maximum of ‘2n’ unique output lines. The general structure of
decoder circuit is

3
5
 General structure of decoder
The encoded information is presented as ‘n’ inputs producing ‘2 n’ possible
outputs. The 2n output values are from 0 through 2 n-1. A decoder is provided with
enable inputs to activate decoded output based on data inputs. When any one
enable input is unasserted, all outputs of decoder are disabled.

Binary Decoder (2 to 4 decoder)

A binary decoder has ‘n’ bit binary input and a one activated output out of 2 n
outputs.A binary decoder is used when it is necessary to activate exactly one of 2 n
outputs based on an n-bit input value.

2-to-4 Line decoder

Here the 2 inputs are decoded into 4 outputs, each output representing one of
the minterms of the two input variables.
Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs
(Y0 – Y3), is active for a given input.
The output Y0 is active, ie., Y0= 1 when inputs A= B= 0,
3
6
 Y1 is active when inputs, A= 0 and B= 1,
Y2 is active, when input A= 1 and B= 0,
Y3 is active, when inputs A= B= 1.
3-to-8 Line Decoder
A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y 0- Y7).
Based on the 3 inputs one of the eight outputs is selected.
The three inputs are decoded into eight outputs, each output representing one of the minterms of the
3-input variables. This decoder is used for binary-to-octal conversion. The input variables may represent a
binary number and the outputs will represent the eight digits in the octal number system. The output
variables are mutually exclusive because only one output can be equal to 1 at any one time. The output line
whose value is equal to 1 represents the minterm equivalent of the binary number presently available in the
input lines.
Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

3
7
 3-to-8 line decoder

BCD to 7-Segment Display Decoder

A seven-segment display is normally used for displaying any one of the
decimal digits, 0 through 9. A BCD-to-seven segment decoder accepts a decimal digit
in BCD and generates the corresponding seven-segment code.

Each segment is made up of a material that emits light when current is passed
through it. The segments activated during each digit display are tabulated as

3
8
Digit Display Segments Activated

0 a, b, c, d, e, f

1 b, c

2 a, b, d, e, g

3 a, b, c, d, g

4 b, c, f, g

5 a, c, d, f, g

6 a, c, d, e, f, g

7 a, b, c

8 a, b, c, d, e, f, g

9 a, b, c, d, f, g

3
9
Truth table:

Digi BCD code 7-Segment code

t A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1

K-map Simplification:

4
0
4
1
Logic Diagram

BCD to 7-segment display decoder

Applications of decoders:
1. Decoders are used in counter system.
2. They are used in analog to digital converter.
3. Decoder outputs can be used to drive a display system.
4. Address decoding
5. Implementation of combinational circuits.
6. Code converters.

4
2
 ENCODERS
An encoder is a digital circuit that performs the inverse operation of a
decoder. Hence, the opposite of the decoding process is called encoding. An encoder
is a combinational circuit that converts binary information from 2 n input lines to a
maximum of ‘n’ unique output lines.
The general structure of encoder circuit is

General structure of Encoder

It has 2n input lines, only one which 1 is active at any time and ‘n’ output lines.
It encodes one of the active inputs to a coded binary output with ‘n’ bits. In an
encoder, the number of outputs is less than the number of inputs.

Octal-to-Binary Encoder
It has eight inputs (one for each of the octal digits) and the three outputs that
generate the corresponding binary number. It is assumed that only one input has a
value of 1 at any given time.
The encoder can be implemented with OR gates whose inputs are determined directly from the truth table. Output z is equal to 1, when the input octal digit is
1 or 3 or 5 or 7. Output y is 1 for octal digits 2, 3, 6, or 7 and the output is 1 for digits 4, 5, 6 or 7.

Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

These conditions can be expressed by the following output Boolean functions:

z= D1+ D3+ D5+ D7
y= D2+ D3+ D6+ D7
x= D4+ D5+ D6+ D7

4
3
 The encoder can be implemented with three OR gates. The encoder defined in
the below table, has the limitation that only one input can be active at any given
time. If two inputs are active simultaneously, output produces an undefined
combination.
For eg., if D3 and D6 are 1 simultaneously, the output of the encoder may be
111. This does not represent either D6 or D3. To resolve this problem, encoder circuits
must establish an input priority to ensure that only one input is encoded. If we
establish a higher priority for inputs with higher subscript numbers and if D 3 and D6
are 1 at the same time, the output will be 110 because D 6 has higher priority than D3.

Octal-to-Binary Encoder
Another problem in the octal-to-binary encoder is that an output with all 0’s is
generated when all the inputs are 0; this output is same as when D 0 is equal to 1.
The discrepancy can be resolved by providing one more output to indicate that
atleast one input is equal to 1.

Priority Encoder
A priority encoder is an encoder circuit that includes the priority function. In
priority encoder, if two or more inputs are equal to 1 at the same time, the input
having the highest priority will take precedence.

In addition to the two outputs x and y, the circuit has a third output, V (valid bit
indicator). It is set to 1 when one or more inputs are equal to 1. If all inputs are 0,
there is no valid input and V is equal to 0.
The higher the subscript number, higher the priority of the input. Input D 3, has
the highest priority. So, regardless of the values of the other inputs, when D 3 is 1, the
output for xy is 11.

4
4
 D2 has the next priority level. The output is 10, if D 2= 1 provided D3= 0. The
output for D1 is generated only if higher priority inputs are 0, and so on down the
priority levels.

Truth table:

Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1

Although the above table has only five rows, when each don’t care condition is
replaced first by 0 and then by 1, we obtain all 16 possible input combinations. For
example, the third row in the table with X100 represents minterms 0100 and 1100.
The don’t care condition is replaced by 0 and 1 as shown in the table below.

Modified Truth table:

Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
0 1 0 0
0 1 1
1 1 0 0
0 0 1 0
0 1 1 0
1 0 1
1 0 1 0
1 1 1 0
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

K-map Simplification:

4
5
The priority encoder is implemented according to the above Boolean functions.

4-Input Priority Encoder

4
6
 INTRODUCTION to sequential circuits
Incombinationallogiccircuits,theoutputsatanyinstantoftimedependonlyon the
inputsignals presentatthat time.For anychange in input, the outputoccursimmediately.

CombinationalCircuit-BlockDiagram

In sequential logic circuits, it consists of combinational circuits to

whichstorage elements are connected to form a feedback path. The storage elements
aredevicescapableofstoringbinaryinformationeither1or0.

The information stored in the memory elements at any given time defines
thepresentstateofthesequentialcircuit.Thepresentstateandtheexternalcircuitdeterminetheoutputan
dthenextstateofsequentialcircuits.

SequentialCircuit-BlockDiagram

Thusinsequentialcircuits,theoutputvariablesdependnotonlyonthepresent input
variablesbut also on the past historyof input variables.

4
7
 Therotarychannelselectedknobonanold-fashionedTVislikeacombinational. Its output
selects a channel based only on its current input – theposition of the knob. The channel-up and
channel-down push buttons on a TV is
likeasequentialcircuit.Thechannelselectiondependsonthepastsequenceofup/downpushes.

Thecomparisonbetweencombinationalandsequentialcircuitsisgivenintablebelow.

S.No Combinationallogic Sequentiallogic

Theoutputvariable,atalltimesde Theoutputvariabledependsnotonlyon
1 pendsonthecombinationof thepresentinputbutalsodepend
inputvariables. uponthepasthistoryofinputs.
Memoryunitisrequiredtostorethe
2 Memoryunitisnot required.
pasthistoryofinputvariables.
3 Fasterinspeed. Slowerthancombinationalcircuits.
4 Easytodesign. Comparativelyhardertodesign.
Eg.Adder,subtractor,Decoder,
5 Eg.Shiftregisters,Counters
Encoders,Magnitudecomparator

3.1 CLASSIFICATIONOFLOGICCIRCUITS

Thesequentialcircuitscanbeclassifieddependingonthetimingoftheirsignals:

 Synchronoussequentialcircuits
 Asynchronoussequentialcircuits.

4
8
S.No Synchronoussequentialcircuits Asynchronoussequentialcircuits
Memoryelements
1 Memory elements are
areeitherunclockedflip-flops
clockedFlip-Flops.
(Latches) or time delay
elements.
Thechange ininputsignalscan Thechangeininputsignalscanaffect
2 affect memory element memoryelementatanyinstantoftime.

uponactivationofclocksignal.
Themaximumoperatingspeedofcl Becauseoftheabsenceofclock,itcanoper
3 ockdependsontimedelays ate faster than synchronous
involved. circuits.
4 Easiertodesign Moredifficulttodesign

3.2 TRIGGERINGOFFLIP-FLOPS

ThestateofaFlip-Flopisswitchedbyamomentarychangeintheinputsignal.This momentary
change is called a trigger and the transition it causes is said totrigger the Flip-Flop. Clocked Flip-
Flops are triggered by pulses. A clock pulse startsfrom an initial value of 0, goes momentarily to
1and after a short time, returns to itsinitial0value.

Latches are controlled by enable signal, and they are level triggered, eitherpositive level
triggered or negative level triggered. The output is free to changeaccording to the S and R input
values, when active level is maintained at the enableinput.

3
3.3 EDGETRIGGEREDFLIP-FLOPS

Flip-Flops are synchronous bistable devices (has two outputs Q and Q’).
Inthiscase,thetermsynchronousmeansthattheoutputchangesstateonlyataspecified point on the
triggering input called the clock (CLK), i.e., changes in
theoutputoccurinsynchronizationwiththeclock.

Anedge-triggeredFlip-Flopchangesstateeitheratthepositiveedge(rising
edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to itsinputs only at
this transition of the clock. The different types of edge-triggered Flip-Flopsare—

 S-RFlip-Flop (Set–Reset)
 J-KFlip-Flop (JackKilby)
 DFlip-Flop (Delay)
 TFlip-Flop (Toggle)
Although the S-R Flip-Flop is not available in IC form, it is the basis for the Dand J-K Flip-
Flops. Each type can be either positive edge-triggered (no bubble at Cinput)ornegativeedge-
triggered(bubbleatCinput).

The key to identifying an edge- triggered Flip-Flop by its logic symbol is thesmall triangle
inside the block at the clock (C) input. This triangle is called thedynamicinputindicator.

3.4.1 S-RFlip-Flop
TheSandRinputsoftheS-RFlip-Floparecalledsynchronousinputsbecausedata on these
inputs are transferred to the Flip-Flop's output only on the triggeringedge of the clock pulse.
The circuit is similar to SR latch except enable signal
isreplacedbyclockpulse(CLK).Onthepositiveedgeoftheclockpulse,thecircuit

respondstotheSandRinputs.

4
 SRFlip-Flop

WhenSisHIGHandRisLOW,theQoutputgoesHIGHonthetriggeringedgeoftheclockpulse,and
theFlip-FlopisSET.WhenSisLOWandRisHIGH,theQ output goes LOW on the triggering edge of the
clock pulse, and the Flip-Flop isRESET. When both S and R are LOW, the output does not change
from its prior state.AninvalidconditionexistswhenbothSandRareHIGH.

CLK S R Qn Qn+1 State

1 0 0 0 0
No Change(NC)
1 0 0 1 1
1 0 1 0 0
Reset
1 0 1 1 0
1 1 0 0 1
Set
1 1 0 1 1
1 1 1 0 x Indeterminate
1 1 1 1 x *

TruthtableforSRFlip-Flop
The timingdiagram ofpositiveedgetriggeredSRflip-flopisshownbelow.

InputandoutputwaveformsofSRFlip-Flop

5
CharacteristictableandCharacteristicequation:
The characteristic table for JK Flip-Flop is shown in the table below. From the table, K-map
for the next state transition (Q n+1) can be drawn and the simplified

logicexpressionwhichrepresentsthecharacteristicequationofJKFlip-Flopcanbefound.

S R Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x
Characteristictable

K-mapSimplification:

6
Characteristicequation:
Qn+1=S+R’Qn

3.4.2 J-KFlip-Flop:
JKmeansJackKilby,TexasInstrument(TI)Engineer,whoinventedICin1958.JK Flip-Flop has
two inputs J(set) and K(reset). A JK Flip-Flop can be obtained fromtheclockedSRFlip-
FlopbyaugmentingtwoANDgatesasshownbelow.

JKFlipFlop
The data input J and the output Q’ are applied o the first AND gate and itsoutput (JQ’) is
applied to the S input of SR Flip-Flop. Similarly, the data input K
andtheoutputQareappliedtothesecondANDgateanditsoutput(KQ)isappliedtotheRinputofSRFlip-
Flop.
J=K=0
WhenJ=K=0,bothANDgatesaredisabled.Thereforeclockpulsehavenoeffect,hencetheFlip-
Flopoutputis sameasthepreviousoutput.

J=0,K=1
WhenJ=0andK=1,ANDgate1isdisabledi.e.,S=0andR=1.ThisconditionwillresettheFlip-
Flopto0.

J=1,K=0
WhenJ=1andK=0,ANDgate2isdisabledi.e.,S=1andR=0.ThereforetheFlip-
Flopwillsetontheapplicationofaclockpulse.

J=K=0
WhenJ=K=1,itispossibletosetorresettheFlip-Flop.IfQisHigh,ANDgate 2 passes on a reset
pulse to the next clock. When Q is low, AND gate 1 passes ona set pulse to the next clock.
Eitherway, Q changes to the complement of the
laststatei.e.,toggle.Togglemeanstoswitchtotheoppositestate.

Truthtable:

Inputs Output
CLK State
J K Qn+1
1 0 0 Qn No Change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Qn’ Toggle
 Thetimingdiagram ofnegativeedgetriggeredJKflip-flopisshownbelow.

InputandoutputwaveformsofJKFlip-Flop

CharacteristictableandCharacteristicequation:
The characteristic table for JK Flip-Flop is shown in the table below. From the table, K-map
for the next state transition (Q n+1) can be drawn and the simplified

logicexpressionwhichrepresentsthecharacteristicequationofJKFlip-Flopcanbefound.

Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Characteristictable

K-mapSimplification:

Characteristicequation:
Qn+1=JQ’+K’Q
 3.4.3 DFlip-Flop:
LikeinDlatch,inDFlip-FlopthebasicSRFlip-Flopisusedwithcomplementedinputs.TheDFlip-
FlopissimilartoD-latchexceptclockpulseisusedinsteadofenableinput.

DFlip-Flop

ToeliminatetheundesirableconditionoftheindeterminatestateintheRSFlip-
FlopistoensurethatinputsSandRareneverequalto1atthesametime.Thisis donebyD Flip-Flop.TheD
(delay) Flip-Flophas one inputcalled delayinputandclockpulseinput.

TheDFlip-FlopusingSRFlip-Flopisshownbelow.

TruthTable:
The truth table of D Flip-Flop isgiven below.

Clock D Qn+1 State

1 0 0 ResetS
1 1 1 et
0 x Qn No Change

TruthtableforDFlip-Flop
 ThetimingdiagramofpositiveedgetriggeredD flip-flopis shownbelow.

InputandoutputwaveformsofclockedDFlip-Flop

Looking at the truth table for D Flip-Flop we can realize that Qn+1

functionfollowstheD inputatthepositivegoingedgesoftheclockpulses.

CharacteristictableandCharacteristicequation:
ThecharacteristictableforDFlip-Flopshows thatthenextstateof theFlip-
FlopisindependentofthepresentstatesinceQn+1isequaltoD.Thismeansthataninputpulsewilltransferthe

valueofinputDintotheoutputoftheFlip-
Flopindependentofthevalueoftheoutputbeforethepulsewasapplied.

ThecharacteristicequationisderivedfromK-map.

Qn D Qn+1
0 0 0
0 1 1
1 0 0
1 1 1
Characteristictable
K-mapSimplification:

Characteristicequation:

Qn+1=D.
 3.4.4 TFlip-Flop
The T (Toggle) Flip-Flop is a modification of the JK Flip-Flop. It is obtainedfromJKFlip-
FlopbyconnectingbothinputsJandKtogether,i.e.,singleinput.Regardlessofthepresentstate,theFlip-
FlopcomplementsitsoutputwhentheclockpulseoccurswhileinputT=1.

TFlip-Flop

When T= 0, Qn+1= Qn, ie., the next state is the same as the present state and

nochangeoccurs.

WhenT=1,Qn+1=Qn’,ie.,thenextstateisthecomplementofthepresentstate.

TruthTable:
ThetruthtableofTFlip-Flopisgivenbelow.

T Qn+1 State
0 Qn No Change
1 Qn’ Toggle

TruthtableforTFlip-Flop
CharacteristictableandCharacteristicequation:
ThecharacteristictableforTFlip-FlopisshownbelowandcharacteristicequationisderivedusingK-
map.

Qn T Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
K-mapSimplification:

Characteristicequation:
Qn+1=TQn’+T’Qn

3.4.5 Master-SlaveJKFlip-Flop
Amaster-slaveFlip-FlopconsistsofclockedJKflip-flopasamasterandclockedSRflip-
flopasaslave.Theoutputofthemasterflip-flopisfedasaninputtotheslaveflip-
flop.Clocksignalisconnecteddirectlytothemasterflip-
flop,butisconnectedthroughinvertertotheslaveflip-flop.Therefore,theinformationpresentatthe J and
Kinputs is transmitted tothe outputof masterflip-flop on the positiveclock pulse and it is held there
until the negative clock pulse occurs, after which it isallowedtopassthroughtotheoutputofslaveflip-
flop.Theoutputoftheslaveflip-flopisconnectedasathirdinputofthemasterJKflip-flop.

Logicdiagram
 When J= 1 and K= 0, the master sets on the positive clock. The high Youtput of the
master drives the S input of the slave, so at negative clock, slave
sets,copyingtheactionofthemaster.

When J=0andK=1,the masterresets on the positive clock. The high Y’output of the master
goes to the R input of the slave. Therefore, at the negative
clockslaveresets,againcopyingtheactionofthemaster.

When J= 1 and K= 1, master toggles on the positive clock and the output ofmaster is
copied by the slave on the negative clock. At this instant, feedback inputsto the master flip-flop
are complemented, but as it is negative half of the clock pulse,masterflip-
flopisinactive.Thisprevents racearoundcondition.

Theclockedmaster-slaveJ-KFlip-FlopusingNANDgateisshownbelow.

Master-SlaveJKFlip-Flop

Theinput andoutputwaveformsof master-slave JKflip-flop isshownbelow.

Inputandoutputwaveformofmaster-slaveflip-flop
3.4 APPLICATION TABLE(OR)EXCITATION TABLE:
ThecharacteristictableisusefulforanalysisandfordefiningtheoperationoftheFlip-
Flop.Itspecifiesthenextstate(Qn+1)whentheinputsandpresentstateareknown.

Theexcitationorapplicationtableisusefulfordesignprocess.ItisusedtofindtheFlip-

Flopinputconditionsthatwillcausetherequiredtransition,whenthe presentstate(Qn)andthenextstate(Q

n+1)areknown.

3.5.1 SRFlip-Flop:

Present
Inputs NextState Present Next
State Inputs Inputs
Qn S R Qn+1 State State
Qn Qn+1 S R S R
0 0 0 0
0 0 1 0 0 0 0 0
0 x
0 1 0 1 0 0 0 1

0 1 1 x 0 1 1 0 1 0

1 0 0 1 1 0 0 1 0 1

1 0 1 0 1 1 0 0
x 0
1 1 0 1 1 1 1 0

1 1 1 x ModifiedTable

CharacteristicTable

Present Next
Inputs
State State
Qn Qn+1 S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
ExcitationTable
 TheabovetablepresentstheexcitationtableforSRFlip-

Flop.Itconsistsofpresentstate(Qn),nextstate(Qn+1)andacolumnforeachinputtoshowhowtherequiredtra
nsitionisachieved.

Thereare4possibletransitionsfrompresentstatetonextstate.TherequiredInputconditionsfore
ach ofthefourtransitions arederivedfrom
theinformationavailableinthecharacteristictable.Thesymbol‘x’denotesthedon’tcarecondition;itdoesno
tmatterwhethertheinputis0or1.

3.5.2 JKFlip-Flop:
Present Next Present Next
Inputs Inputs Inputs
State State State State
Qn J K Qn+1 Qn Qn+1 J K J K
0 0 0 0 0 0 0 0
0 x
0 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0
1 x
0 1 1 1 0 1 1 1
1 0 0 1 1 0 0 1
x 1
1 0 1 0 1 0 1 1
1 1 0 1 1 1 0 0
x 0
1 1 1 0 1 1 1 0

CharacteristicTable
ModifiedTable

Present Next
Inputs
State State
Qn Qn+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

ExcitationTable
3.5.3 DFlip-Flop:

Present Next Present Next

Input Input
State State State State
Qn D Qn+1 Qn Qn+1 D
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 0
1 1 1 1 1 1
CharacteristicTable

3.5.4 TFlip-Flop:
ExcitationTable
 Present Next Present Next
Input Input
State State State State
Qn T Qn+1 Qn Qn+1 T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0

CharacteristicTable ExcitationTable

3.5 SHIFTREGISTERS:

A register is simply a group of Flip-Flops that can be used to store a

binarynumber.TheremustbeoneFlip-Flopforeachbitinthebinarynumber.Forinstance,aregister
usedtostorean8-bitbinary numbermusthave8Flip-Flops.

TheFlip-Flopsmustbeconnectedsuchthatthebinarynumbercanbeentered(shifted) into the

register and possibly shifted out. A group of Flip-Flops connectedtoprovide either orboth
ofthese functionsiscalledashiftregister.

Thebitsinabinarynumber(data)canberemovedfromoneplacetoanother
in either of two ways. The first method involves shifting the data one bit at a time ina serial
fashion, beginning with either the most significant bit (MSB) or the leastsignificantbit (LSB).
Thistechnique isreferredto as serialshifting. The second

methodinvolvesshiftingallthedatabitssimultaneouslyandisreferredtoasparallel
shifting.
There are two ways to shift into a register (serial or parallel) and similarly twoways to shift
the data out of the register. This leads to the construction of four basicregistertypes—

i. Serialin-serialout,
ii. Serialin-parallelout,
iii. Parallelin-serialout,
 iv. Parallelin-parallelout.

(i) Serial in-serialout (iii)Parallelin-serialout

(iii)Serialin-parallelout (iv)Parallelin-parallelout
3.11.1 Serial-InSerial-OutShiftRegister:
Theserialin/
serialoutshiftregisteracceptsdataserially,i.e.,onebitatatimeonasingleline.Itproducesthestoredinf
ormationonitsoutputalsoinserialform.

Serial-InSerial-OutShiftRegister

The entry of the four bits 1010 into the register is illustrated below, beginningwith the right-
most bit. The register is initially clear. The 0is put onto the data

inputline,makingD=0forFF0.Whenthefirstclockpulseisapplied,FF0isreset,thusstoringthe0.

Nextthesecondbit,whichisa1,isappliedtothedatainput,makingD=1for FF0andD=0forFF1becaus
etheDinputofFF1isconnectedtotheQ0output.Whenthesecondclockpulseoccurs,the1onthedatainputiss

hiftedintoFF0,causingFF0toset;andthe0thatwasinFF0isshiftedintoFFl.

The third bit, a 0, is now put onto the data-input line, and a clock pulse is applied. The 0
is entered into FF0, the 1 stored in FF0is shifted into FFl, and the 0storedinFF1isshiftedintoFF2.
 The lastbit, a 1,isnowapplied tothe data input, and a clockpulseis applied.This timethe 1
isentered intoFF0, the 0 storedin FF0 isshifted intoFFl, the 1 storedin FF1 isshiftedintoFF2, and the
0stored in FF2 is shiftedintoFF3.
Thiscompletestheserialentryofthefourbitsintotheshiftregister,wheretheycanbestoredforanylengthoft
imeaslongastheFlip-Flopshavedcpower.

To get the data out of the register, the bits must be shifted out serially andtaken
offtheQ3 output. AfterCLK4, theright-most bit, 0,appearson theQ3 output.

When clock pulse CLK5 is applied, the second bit appears on the Q3 output.Clock pulse
CLK6 shifts the third bit to the output, and CLK7 shifts the fourth bit
totheoutput.Whiletheoriginalfourbitsarebeingshiftedout,morebitscanbeshiftedin.Allzerosaresho
wnbeingshiftedout,morebitscanbeshiftedin.

3.11.2 Serial-InParallel-OutShiftRegister:
In this shift register, data bits are entered into the register in the same asserial-inserial-
outshiftregister.Buttheoutputistakeninparallel.Oncethedataarestored,eachbitappearsonitsrespe
ctiveoutputlineandallbitsareavailablesimultaneouslyinsteadofonabit-by-bit.

Serial-Inparallel-OutShiftRegister

3.11.3 Parallel-InSerial-OutShiftRegister:
 In this type, the bits are entered in parallel i.e., simultaneously into
theirrespectivestagesonparallellines.A 4-bit parallel-in serial-out shift register is illustrated

below. There are fourdata input lines, X0, X1, X2and X3for entering data in parallel into the
register.SHIFT/ LOAD input is the control input, which allows four bits of data to load

inparallelintotheregister.

Parallel-InSerial-OutShiftRegister
When SHIFT/LOADis LOW,gates G1,G2, G3and G4 are enabled, allowingeach data bit to

be applied to the D input of its respective Flip-Flop. When a clockpulse is applied, the Flip-Flops
with D = 1 will set and those with D = 0 will reset,therebystoringallfourbitssimultaneously.

WhenSHIFT/LOADisHIGH,gatesG1,G2,G3andG4aredisabledandgatesG5, G6 and G7 are

enabled, allowing the data bits to shift right from one stage to the next. The OR gates allow

either the normal shifting operation or the parallel data-entry operation, depending on which
AND gates are enabled by the level on theSHIFT/LOADinput.

3.11.4 Parallel-InParallel-OutShiftRegister:
In this type, there is simultaneous entry of all data bits and the bits appear
onparalleloutputssimultaneously.
 Parallel-InParallel-OutShiftRegister

3.6 UNIVERSALSHIFTREGISTERS:
If the register has shift and parallel load capabilities, then it is called a shiftregister with
parallel load or universal shift register. Shift register can be used forconverting serial
data to parallel data, and vice-versa. If a parallel load capability
isaddedtoashiftregister,thedataenteredinparallelcanbetakenoutinserialfashionbyshiftingthedata
storedintheregister.

Thefunctionsofuniversalshiftregisterare:

1. Aclearcontroltocleartheregisterto0.
2. Aclockinputtosynchronizetheoperations.
3. Ashift-
rightcontroltoenabletheshiftrightoperationandtheserialinputandoutputlinesasso
ciatedwiththeshiftright.
4. Ashift-
leftcontroltoenabletheshiftleftoperationandtheserialinputandoutputlinesassociated
withtheshiftleft.
5. Aparallel-
loadcontroltoenableaparalleltransferandtheninputlinesassociatedwiththeparallel
transfer.
6. ‘n’paralleloutputlines.
 7. Acontrollinethatleavestheinformationintheregisterunchangedeventhoughthecloc
kpulsesrecontinuouslyapplied.

4-BitUniversalShiftRegister
It consists of four D-Flip-Flops and four 4 input multiplexers (MUX). S 0 and

S1arethetwoselectioninputsconnectedtoallthefourmultiplexers.Thesetwoselectioninputsareuse

dtoselectoneofthefourinputsofeachmultiplexer.

The input 0 in each MUX is selected when S 1S0= 00 and input 1 is selectedwhen S1S0=

01. Similarly inputs 2 and 3 are selected when S 1S0= 10 and S1S0=

11respectively.TheinputsS1andS0controlthemodeoftheoperationoftheregister.

When S1S0= 00, the present value of the register is applied to the D-inputs of the Flip-

Flops. This is done by connecting the output of each Flip-Flop to the 0 inputof the respective
multiplexer. The next clock pulse transfers into each Flip-Flop,
thebinaryvalueisheldpreviously,andhencenochangeofstateoccurs.

WhenS1S0=01,terminal1ofthemultiplexerinputshasapathtotheDinputsof theFlip-Flops.

This causes a shift-rightoperation with the lefterserial inputtransferredintoFlip-FlopFF3.

 When S1S0= 10, a shift-left operation results with the right serial input goingintoFlip-

FlopFF1.

FinallywhenS1S0=11,thebinaryinformationontheparallelinputlines(I1,I2,I3andI4)aretransfe

rred intotheregistersimultaneouslyduringthenextclockpulse.

The function table of bi-directional shift register with parallel inputs

andparalleloutputsisshownbelow.

ModeControl
Operation
S1 S0
0 0 No
0 1 changeShi
1 0 ft-
1 1 rightShift-
left
Parallelload

3.7 BI-DIRECTIONSHIFTREGISTERS:
A bidirectional shift register is one in which the data can be shifted either leftor right. It
can be implemented by using gating logic that enables the transfer of adata bit from one stage
to the next stage to the right or to the left depending on thelevelofacontrolline.

A4-bitbidirectionalshiftregisterisshownbelow.AHIGHontheRIGHT/LEFT control input

allows data bits inside the register to be shifted to theright,andaLOW enablesdata bitsinside
theregisterto beshifted tothe left.

When the RIGHT/LEFT control input is HIGH, gates G1, G2, G3and G4areenabled, and the

state of the Q output of each Flip-Flop is passed through to the Dinput of the following Flip-
Flop. When a clock pulse occurs, the data bits are shiftedoneplacetotheright.

When the RIGHT/LEFT control input is LOW, gates G5, G6, G7and G8areenabled, and the

Q output of each Flip-Flop is passed through to the D input of thepreceding Flip-Flop. When a
clock pulse occurs, the data bits are then shifted oneplacetotheleft.
 4-bitbi-directionalshiftregister

3.8 SYNCHRONOUSCOUNTERS:

Flip-Flops can be connected together to perform counting operations. Such agroup of

Flip- Flops is a counter. The number of Flip-Flops used and the way inwhich they are connected
determine the number of states (called the modulus)
andalsothespecificsequenceofstatesthatthecountergoesthroughduringeachcompletecycle.
 Countersareclassifiedintotwobroadcategoriesaccordingtothewaytheyareclocked:

Asynchronous
counters,Synchronouscoun
ters.

Inasynchronous(ripple)counters,thefirstFlip-
FlopisclockedbytheexternalclockpulseandtheneachsuccessiveFlip-
FlopisclockedbytheoutputoftheprecedingFlip-Flop.

In synchronous counters, the clock input is connected to all of the Flip-

Flopssothattheyareclockedsimultaneously.Withineachofthesetwocategories,countersareclassifi
edprimarilybythetypeofsequence,thenumberofstates,orthenumberofFlip-Flopsinthecounter.

Theterm‘synchronous’referstoeventsthathaveafixedtimerelationshipwith each
other. In synchronous counter, the clock pulses are applied to all Flip-
Flopssimultaneously.Hencethereisminimumpropagationdelay.

S.No Asynchronous(ripple)counter Synchronouscounter

1 AlltheFlip- All the Flip-Flops are

Flopsarenotclockedsimultaneou clockedsimultaneously.
sly.
2 Thedelaytimesofall Flip- Thereisminimumpropagationdelay.
Flopsare added. Therefore
there
isconsiderablepropagationdela
y.
3 Speedofoperationislow Speedofoperation ishigh.

4 Logiccircuitisverysimpleevenfo Design involves complex logic

rmorenumber ofstates. circuitasnumberofstateincreases.
5 Minimumnumbersoflogicdevicesa Thenumberoflogicdevicesismoreth
reneeded. anripplecounters.
6 Cheaperthansynchronousc Costlierthanripplecounters.
ounters.

3.14.1 2-BitSynchronousBinaryCounter
Inthiscountertheclocksignalisconnectedinparalleltoclockinputsofboth
theFlip-Flops(FF0andFF1).TheoutputofFF0isconnectedtoJ1andK1inputsofthesecondFlip-Flop(FF1).
 2-BitSynchronousBinaryCounter

Assume that the counter is initially in the binary 0 state: i.e., both Flip-Flops are RESET.
When the positive edge of the first clock pulse is applied, FF 0 will togglebecause J0= k0= 1,

whereas FF1 output will remain 0 because J1= k1= 0. After the firstclockpulseQ0=1andQ1=0.

When the leading edge of CLK2 occurs, FF0will toggle and Q0will go LOW.Since FF1has a

HIGH (Q0= 1) on its J1and K1inputs at the triggering edge of thisclockpulse,theFlip-

FloptogglesandQ1goesHIGH.Thus,afterCLK2,

Q0=0andQ1=1.
WhentheleadingedgeofCLK3occurs,FF0againtogglestotheSETstate(Q0

= 1), and FF1 remains SET (Q1 = 1) because its J1 and K1 inputs are both LOW (Q0 =

0).Afterthistriggeringedge,Q0=1andQ1=1.

Finally, at the leading edge of CLK4, Q 0 and Q1 go LOW because they bothhave a toggle

condition on their J1 and K1 inputs. The counter has now recycled to itsoriginalstate,Q0=Q1=0.

Timingdiagram
 3.14.2 3-BitSynchronousBinaryCounter
A 3 bit synchronous binary counter is constructed with three JK Flip-Flops and an AND
gate. The output of FF0 (Q0) changes on each clock pulse as the counter progresses from its

original state to its final state and then back to its original state. To produce this operation, FF0
must be held in the toggle mode by constant HIGH,onitsJ0andK0inputs.

3- BitSynchronousBinaryCounter

The output of FF1(Q1) goes to the opposite state following each time Q 0= 1.This change
occurs at CLK2, CLK4, CLK6, and CLK8. The CLK8 pulse causes the counter to recycle. To produce
this operation, Q0 is connected to the J1 and K1 inputsof FF1. When Q0= 1 and a clock pulse
occurs, FF1 is in the toggle mode and thereforechanges state. When Q 0= 0, FF1 is in the no-
change mode and remains in its presentstate.

The output of FF2 (Q2) changes state both times; it is preceded by the uniquecondition in
which both Q0 and Q1 are HIGH. This condition is detected by the ANDgate and applied to the J 2
and K2 inputs of FF2. Whenever both outputs Q 0= Q1= 1,the output of the AND gate makes the
J2= K2= 1 and FF2toggles on the followingclock pulse. Otherwise, the J 2and K2inputs of FF2 are
held LOW by the AND gateoutput,FF2doesnotchangestate.

CLOCKPulse Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8(recycles) 0 0 0
 Timingdiagram

3.14.3 4-BitSynchronousBinaryCounter
This particular counter is implemented with negative edge-triggered Flip-Flops. The
reasoning behind the J and K input control for the first three Flip- Flops isthe same as previously

discussed for the 3-bit counter. For the fourth stage, the Flip- Flop has to change the state when
Q0= Q1= Q2= 1. This condition is decoded by ANDgateG2.

4- BitSynchronousBinaryCounter
Therefore, when Q0= Q1= Q2= 1, Flip-Flop FF3 toggles and for all other times it isinano-

changecondition.PointswheretheANDgateoutputsareHIGHareindicatedbytheshadedareas.

3.14.4 4-BitSynchronousDecadeCounter:(BCDCounter):
BCDdecadecounterhasasequencefrom0000to1001(9).After1001stateitmust recycle back
to 0000 state. This counter requires four Flip-Flops and AND/ORlogicasshownbelow.
 4-Bit Synchronous DecadeCounter

 First,noticethatFF0(Q0)togglesoneachclockpulse,sothelogicequationforitsJ0andK0input

sis

J0=K0=1
ThisequationisimplementedbyconnectingJ0andK0toaconstantHIGHlevel.

 Next, notice from table, that FF1(Q1) changes on the next clock pulse eachtime

Q0=1and Q3=0,sothelogicequationfortheJ1and K1inputsis

J1=K1=Q0Q3’
 Flip-Flop 2 (Q2) changes on the next clock pulse each time both Q 0= Q1= 1.This
requiresaninputlogicequationasfollows:
J2=K2=Q0Q1
This equation is implemented by ANDing Q 0 and Q1 and connecting the gate

outputtotheJ2andK2inputsofFF2.

 Finally, FF3(Q3) changes to the opposite state on the next clock pulse eachtime

Q0 = 1, Q1 = 1, and Q2 = 1 (state 7), or when Q0 = 1 and Q1 = 1 (state

9).Theequationforthisisasfollows:

J3=K3=Q0Q1Q2+Q0Q3
ThisfunctionisimplementedwiththeAND/ORlogicconnectedtotheJ 3andK3inputsofFF3.
 CLOCKPulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10(recycles) 0 0 0 0
Thetimingdiagramforthedecadecounterisshownbelow.

Timingdiagram

3.14.5 SynchronousUP/DOWNCounter
Anup/
downcounterisabidirectionalcounter,capableofprogressingineitherdirectionthroughacertainsequenc
e.A3-
bitbinarycounterthatadvancesupwardthroughitssequence(0,1,2,3,4,5,6,7)andthencanbereversedsot
hatit

goesthroughthesequenceintheoppositedirection(7,6,5,4,3,2,1,0)isanillustrationofup/
downsequentialoperation.

The complete up/down sequence for a 3-bit binary counter is shown in

tablebelow.Thearrowsindicatethestate-to-statemovementofthecounterforbothitsUPand its
DOWN modes of operation. An examination of Q 0 for both the up and downsequences shows

that FF0 toggles on each clock pulse. Thus, the J0and K0 inputs ofFF0are,

J0=K0=1
 Toform a synchronous UP/DOWN counter, the control input (UP/DOWN)is used to
allow either the normal output or the inverted output of one Flip-Flop
totheJandKinputsofthenextFlip-Flop.WhenUP/DOWN=1,theMOD8counterwillcount from000 to
111and UP/DOWN=0,itwillcountfrom 111to000.

WhenUP/DOWN=1,itwillenableANDgates1and 3 and disable ANDgates 2 and 4. This

allows the Q0 and Q1 outputs through the AND gates to the J andKinputsofthefollowingFlip-
Flops,sothecounter countsupaspulsesareapplied.

WhenUP/DOWN=0,thereverseactiontakesplace.

J1=K1=(Q0.UP)+(Q0’.DOWN)

J2=K2=(Q0.Q1.UP)+(Q0’.Q1’.DOWN)

3-bitUP/DOWNSynchronousCounter
3.14.6 MODULUS-N-COUNTERS:
Thecounterwith‘n’Flip-FlopshasmaximumMODnumber2n.FindthenumberofFlip-
Flops(n)requiredforthedesiredMODnumber(N)usingtheequation,

2n≥N
(i) For example, a 3 bit binary counter is aMOD 8 counter. The basic counter canbe
modified to produce MOD numbers less than 2 nby allowing the counter
toskinthosearenormallypartofcountingsequence.
n=3
N=8

2n=23=8=N

(ii) MOD5Counter:
2n=N

2n=5

22=4lessthanN.

23=8>N(5)

Therefore,3Flip-Flopsarerequired.

(iii) MOD10Counter:
2n=N=10

23=8lessthanN.

24=16>N(10).

ToconstructanyMOD-Ncounter,thefollowingmethodscanbeused.

1. FindthenumberofFlip-
Flops(n)requiredforthedesiredMODnumber(N)usingtheequation,
2n≥N.
2. ConnectalltheFlip-Flopsasarequiredcounter.
3. FindthebinarynumberforN.
4. ConnectallFlip-FlopoutputsforwhichQ=1whenthecountisN,asinputs toNANDgate.
5. ConnecttheNANDgateoutputtotheCLRinputofeachFlip-Flop.
 When the counter reaches Nthstate, the output of the NAND gate goes
LOW,resettingallFlip-Flopsto0.Thereforethecountercountsfrom0throughN-1.

For example, MOD-10 counter reaches state 10 (1010). i.e., Q 3Q2Q1Q0= 1 0 1

0.TheoutputsQ3andQ1areconnectedtotheNANDgateandtheoutputoftheNANDgategoesLOWandrese

ttingallFlip-Flopstozero.ThereforeMOD-
10countercountsfrom0000to1001.Andthenrecyclestothezerovalue.

TheMOD-10countercircuitisshownbelow.

MOD-10(Decade)Counter

3.16.1 Johnsoncounter (ShiftCounter):

InaJohnsoncounterthecomplementoftheoutputofthelastFlip-
FlopisconnectedbacktotheDinputofthefirstFlip-
Flop.Thisfeedbackarrangementproducesacharacteristicsequenceofstatesasshownintablebelow.The4-
bitsequencehasatotalofeightstates,andthatthe5-bitsequencehasatotaloftenstates. In general, a
Johnson counter will produce a modulus of 2n, where ‘n’ is thenumberofstagesinthecounter.

4-BitJohnson Counter
The Q output of each stage is connected to the D input of the next
stage(assumingthatDFlip-
Flopsareused).ThecomplementoutputofthelaststageisconnectedbacktotheDinputofthefirststage
.

Timesequencefora4-bitJohnsoncounter

3.16.2 RingCounters:
TheringcounterutilizesoneFlip-Flopforeachstateinitssequence.Ithastheadvantage that
decoding gates are not required. In the case of a l0-bit ring
counter,thereisauniqueoutputforeachdecimaldigit.

Ringcounter
The output Q0sets D1input, Q1sets D2, Q2sets D3and Q3is fed back to D0.Because

oftheseconditions, bitsareshiftedleft one positionperpositive clock edge

andfedbacktotheinput.AlltheFlip-
Flopsareclockedtogether.WhenCLRgoeslowthenbacktohigh,theoutputis0000.
 Timesequencefora Ringcounter

The first positive clock edge shifts MSB to LSB position and other bits to
onepositionleftsothattheoutputbecomesQ=0010.Thisprocesscontinuesonsecondandthirdclockedges
othatsuccessiveoutputsare0100and1000.Thefourthpositiveclockedgestarts the cycle all over again
and the output is 0001. Thus
thestored1bitfollowsacircularpath(i.e.,thestored1bitsmoveleftthroughallFlip-FlopsandthefinalFlip-
FlopsendsitbacktothefirstFlip-Flop).Thisactionhasgiventhenameofringcounter.

3.9 DESIGNOFCOUNTERS:
Theprocedurefordesignofcountersasfollows:

1. Specifythecountersequenceanddrawastatediagram.
2. Deriveanext-statetablefromthestatediagram.
3. Makethestateassignmentanddevelopatransitiontableshowingtheflip-
flopinputsrequired.
4. Draw theK-mapsforeachinputofeachFlip-Flop.
5. Derivethelogicexpressionfor eachFlip-FlopinputfromtheK-maps.
6. ImplementtheexpressionswithcombinationallogicandcombinewiththeFlip-
Flopstoformthecounter.
 Examples:
1. UsingJKFlip-Flops,designasynchronouscounterwhichcountsinthesequence,
000,001,010,011,100,101,110,111,000.

Step1:StateDiagram

Step2:ExcitationTable:
ExcitationTableforJKFlip-Flop:
PresentState NextState Inputs
Qn Qn+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
ExcitationTableforCounter:

PresentState NextState Flip-FlopInputs

Q2 Q1 Q0 q2 q1 q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 0 0 x 1 x x 1
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 1 0 0 1 x x 1 x 1
1 0 0 1 0 1 x 0 0 x 1 x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 1 1 1 x 0 x 0 1 x
1 1 1 0 0 0 x 1 x 1 x 1

Step3:K-mapSimplification
 Step4:LogicDiagram

2. DesignandexplaintheworkingofasynchronousMOD-3counter.
Soln:
2n≥N=3
22>3.
Therefore,2Flip-Flopsarerequired.

StateDiagram:

ExcitationTable:
 ExcitationTableforJKFlip-Flop:

PresentState NextState Inputs

Qn Qn+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
ExcitationTableforCounter:

PresentState NextState Flip-FlopInputs

QB QA QB+1 QA+1 JB KB JA KA
0 0 0 1 0 x 1 x
0 1 1 0 1 x x 1
1 0 0 0 x 1 0 x

K-mapSimplification:

LogicDiagram:
 3. Designasynchronouscounterwithstates0,1,2,3,0,1,………usingJKFlip-Flops.

Soln:
StateDiagram:

ExcitationTableforCounter:

PresentState NextState Flip-FlopInputs

QB QA QB+1 QA+1 JB KB JA KA
0 0 0 1 0 x 1 x
0 1 1 0 1 x x 1
1 0 1 1 x 0 1 x
1 1 0 0 x 1 x 1

K-mapSimplification:

LogicDiagram:
 4. Design a MOD-7 synchronous counter using JK Flip-Flops. Write excitation
tableandstatetable.

Soln:
2n≥N=7
23>8.
Therefore,3Flip-Flopsarerequired.

StateDiagram:

ExcitationTable:
ExcitationTableforJKFlip-Flop:

PresentState NextState Inputs

Qn Qn+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
ExcitationTableforCounter:

PresentState NextState Flip-FlopInputs

QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 0 0 x 1 x x 1
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 1 0 0 1 x x 1 x 1
1 0 0 1 0 1 x 0 0 x 1 x
 1 0 1 1 1 0 x 0 1 x x 1
1 1 0 0 0 0 x 1 x 1 0 x

K-mapSimplification:

LogicDiagram:

5. Design a MOD-10 synchronous counter using JK Flip-Flops. Write

excitationtableandstatetable.
Soln:
2n≥N=10
24> 10.
Therefore,4Flip-Flopsarerequired.

State Table:

ExcitationTable:
ExcitationTableforJKFlip-Flop:

PresentState NextState Inputs

Qn Qn+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

ExcitationTableforCounter:

PresentState NextState Flip-FlopInputs

QD QC QB QA QD+1 QC+1 QB+1 QA+1 JD KD JC KC JB KB JA KA
0 0 0 0 0 0 0 1 0 x 0 x 0 x 1 x
0 0 0 1 0 0 1 0 0 x 0 x 1 x x 1
0 0 1 0 0 0 1 1 0 x 0 x x 0 1 x
0 0 1 1 0 1 0 0 0 x 1 x x 1 x 1
0 1 0 0 0 1 0 1 0 x x 0 0 x 1 x
0 1 0 1 0 1 1 0 0 x x 0 1 x x 1
0 1 1 0 0 1 1 1 0 x x 0 x 0 1 x
0 1 1 1 1 0 0 0 1 x x 1 x 1 x 1
1 0 0 0 1 0 0 1 x 0 0 x 0 x 1 x
1 0 0 1 0 0 0 0 x 1 0 x 0 x x 1
K-mapSimplification:
LogicDiagram:

49