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Week10 assignment solution

The document contains a series of questions and answers related to CMOS latch design, transistor characteristics, and power dissipation in integrated circuits. It includes calculations for static and switching power, subthreshold leakage current, and evaluates different logic gate configurations. The answers provided are based on assumptions and parameters specific to a 65nm technology library.

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R INI BHANDARI
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10 views

Week10 assignment solution

The document contains a series of questions and answers related to CMOS latch design, transistor characteristics, and power dissipation in integrated circuits. It includes calculations for static and switching power, subthreshold leakage current, and evaluates different logic gate configurations. The answers provided are based on assumptions and parameters specific to a 65nm technology library.

Uploaded by

R INI BHANDARI
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Week -10

1) Why is tristate-inverter in the feedback path used in the CMOS Latch design?
a) To reduce the sensitivity towards Output noise
b) To reduce the sensitivity towards Input noise
c) To avoid the Dynamic output
d) To avoid Staticizing the output
e) To get complete rail-to-rail output swing
f) To improve the delay
g) To improve the dynamic power
h) To get benefits of dual logic family

2) In the most recommended Artisan Standard cell library design, a CMOS Latch has how
many transistors?
a) 100
b) 500
c) 110
d) 200
e) 140
f) 1000
g) 12
h) 4

3) A chip is designed for 65nm technology library, which consists of the following parameters
Number of Logic gates: 200 × 106, Width = 12λ, activity factor of logic gates = 0.1
Number of gates used in Memory: 800 ×106, W = 4λ, activity factor of memory design=0.02
Cgate = 1fF/μm, Cparasitic= 0.8 fF/μm.
Estimate static power dissipated by the Vdd rail of 1V for the designed Chip.
Assumption:
i) Logic 95% low Vt cells, 5% high Vt cells
ii) Memory only low Vt cells
iii) Isub of low Vt cell is 100nA/μm and Isub of high Vt cell is 10nA/μm
iv) Operating Freq = 3GHz

a) 9.9 mW
b) 1000 W
c) 1.185W
d) 6.12 W
e) 41.04
f) W
g) 18 mW
h) 8 mW
i) 28 mW
4) A chip is designed for 65nm technology library, which consists of the following parameters
Number of Logic gates: 200 × 106, Width = 12λ, activity factor of logic gates = 0.1
Number of gates used in Memory: 800 ×106, W = 4λ, activity factor of memory design=0.02
Cgate = 1fF/μm, Cparasitic= 0.8 fF/μm. Estimate switching power dissipated by the Vdd
rail of 1V for the designed Chip.
Assumption:
j) Logic 95% low Vt cells, 5% high Vt cells
ii) Memory only low Vt cells
iii) Isub of low Vt cell is 100nA/μm and Isub of high Vt cell is 10nA/μm
iv) Operating Freq = 3GHz
a) 9.9 mW
b) 1000 W
c) 1.185W
d) 6.12 W
e) 41.04 W
f) 18 mW
g) 8 mW
h) 28 mW

5) Evaluate the subthreshold-leakage current for 2-NAND gate when the inputs of 1, and 0 are
applied. Consider Logic ‘1’ to be applied to transistor closer to ground rail, and Logic ‘0’ to
be applied to the transistor closer to the output node in the PULL-DOWN side. Consider
Ioff for PMOS and NMOS transistors as 20 nA, and 10 nA respectively.
a) 30 nA
b) 6.01 nA
c) 1.01 nA
d) 1.12 nA
e) 10 nA
f) 2.13 nA
g) 0.56 nA
h) 0.5 nA

6) Evaluate the subthreshold-leakage current for 2-NAND gate when the inputs of 1, and 0 are
applied. Consider Logic ‘0’ to be applied to transistor closer to ground rail, and Logic ‘1’ to
be applied to the transistor closer to the output node in the PULL-DOWN side. Consider Ioff
for PMOS and NMOS transistors as 20 nA, and 10 nA respectively.
a) 30 nA
b) 6.01 nA
c) 1.01 nA
d) 10 nA
e) 5 nA
f) 2.13 nA
g) 0.56 nA
h) 0.5 nA

7) Determine the static power for 3-NAND gate for logic 011 where logic “0” is applied to the
transistor closer to the output node in the PULL DOWN side. Consider Ioff for PMOS and
NMOS transistors as 20 nA, and 10 nA respectively, with Igate-NMOS-leakage to be 8 nA.
a) 10 nW
b) 48 nW
c) 26 nW
d) 24 nW
e) 56 nW
f) 16 nW
g) 20 nW
h) 30 nW

8) Determine the static power for 3-NOR gate for logic 100 where logic “1” is applied to the
transistor closer to the output node in the PULL UP side. Consider Ioff for PMOS and NMOS
transistors as 20 nA, and 10 nA respectively, with Igate-NMOS-leakage to be 8 nA.
a) 36 nW
b) 38 nW
c) 28 nW
d) 10 nW
e) 20 nW
f) 25 nW
g) 8 nW
h) 30 nW

9) Select the correct statement.


i. Stacking reduces subthreshold leakage.
ii. Latch is an edge sensitive device.
iii. Flip-flop is two back-to-back connected latches with clk and clk’ connected their
clock port.
iv. Flip-flop is a edge sensitive device

a) i
b) ii, iii
c) ii, iv
d) iii
e) i, ii, iii
f) i, iii, iv
g) i, ii, iv
h) iv

10) The following is _______________ .


a) negative edge triggered flip-flop
b) positive edge triggered flip-flop
c) positive level latch
d) negative edge latch
e) inverter-buffer
f) Jamb latch
g) Clocked CMOS (tristate inverter)
h) behaviour cannot be predicted

Solution:
1) c) To avoid the Dynamic output
Conceptual

2) g) 12
Conceptual

3) c) 1.185W
Isub logic = 200 x 106 x 12 x 0.025µm x (0.95 x 10nA/µm + 0.05 x 100nA/µm) = 0.87A
Isub memory = 800 x 106 x 4 x 0.025 x 10 x 10-9 = 0.8A
Igate logic + memory = 5nA/µm x (200 x 106 x 12 + 800 x 106 x 4) x 0.025µm = 0.7A
Pstatic = 1.185W

4) e) 41.04W
Pswitching = αCVdd2f
= (1.8fF/um) x (0.1 x 200 x 106 x 12 + 0.02 x 800x106x4)x0.025 x3Ghz
= 41.04W

5) e) 10nA
Ioff = Isub = 10nA

6) e) 5nA
Ioff = Isub x 10-0.3 = 0.5011 x 10nA = 5nA
7) c) 26nW

Istatic = Ioffnmos + 2Igatenmos = 10 + 8 + 8 = 26nA


Pstatic = 26nW

8) c) 28nW

Istatic = Ioffpmos + Igatenmos = 20nA + 8nA = 28nA


Pstatic = 28nW

9) f) i, iii, iv
Conceptual

10) a) negative edge triggered flipflop


Conceptual

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