STRUCTURE OF THE CPU

INTRODUCTION:
To an engineer who is familiar with mainframe and mini computers, a microcomputer is simply a less
powerful mini-computer. Microcomputers have smaller instruction sets and are slower than mini
computers, but then they are far less expensive and smaller too.
To an engineer with a hardware background and no computer experience, a microcomputer will look like
a sequential state machine that can functionally replace thousands of random logic chips, but occupies a
much lesser space, costs much lesser and the number of device interconnections being fewer in it, is
much more reliable.
A microcomputer is primarily suited, because of its very low cost and very small size, to dedicated
applications. On the same grounds, the mainframe computer is as a rule suitable as a general purpose
computer. Mini-computer finds applications in both areas.
Definition:
THE MICROPROCESSOR is a programmable device that takes in numbers, performs on them
arithmetic or logical operations according to the program stored in memory and then produces other
numbers as a result.
Programmable device: The microprocessor can perform different sets of operations on the data it
receives depending on the sequence of instructions supplied in the given program. By changing the
program, the microprocessor manipulates the data in different ways.
Instructions set: Each microprocessor is designed to execute a specific group of operations. This group
of operations is called an instruction set. This instruction set defines what the microprocessor can and
cannot do.

TYPES OF MICROPROCESSORS
Assignment. Write short note on the history of microprocessor and give the different types of
microprocessor with their manufacturer that existing.

MAIN PARTS OF CPU

The microprocessor or CPU reads each instruction from the memory, decodes it, executes it and if needed
can stores the result. It processes the data as required in the instructions. The processing is in the form of
arithmetic and logical operations. The data is retrieved from memory or taken from an input device and
the result of processing is stored in the memory or delivered to an appropriate output device, all as per
the instructions.
To perform all these functions, the µP (microprocessor) incorporates various functional units in an
appropriate manner. Such an internal structure or organizational structure of µP, which determines how
it operates, is known as its architecture.
A typical microprocessor architecture is shown in Figure 1.1. The various functional units are as follows:

BY TSEKANE ADI L. M.SC. ENG AUTOMATIQUE ROBOTIQUE AND INDUSTRIAL COMPUTING 1

 (a) (b)
Figure 1.1 Internal structure of the CPU (a) simplify (b) more detail structure

THE REGISTER
CPU must have some working space (temporary storage); called “registers”. A number of registers are
normally included in the microprocessor. These are used for temporary storage of data, instructions and
addresses during execution of a program. Those in the Intel 8085 microprocessor are typical and are
described below:
i. Accumulator(Acc) or Result Register
This is an 8-bit register used in various arithmetic and logical operations. Out of the two operands to be
operated upon, one comes from accumulator (Acc), while the other one may be in another internal register
or may be brought in by the data bus from the main memory. Upon completion of the arithmetic/logical
operation, the result is placed in the accumulator (replacing the earlier operand). Because of the later
function, this register is also called as result register.
ii. General Purpose Registers or Scratch Pad Memory
There are six general purpose 8-bit registers that can be used by the programmer for a variety of purposes.
These registers, labelled as B, C, D, E, H and L, can be used individually (e.g., when operation on 8-bit
data is desired) or in pairs (e.g., when a 16-bit address is to be stored). Only B-C, D-E and H-L pairs are
allowed as showing in figure 1.2

Figure 1.2 Internal general purpose register

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 iii. Instruction Register(IR)
This 8-bit register stores the next instruction to be executed. At the proper time this stored word
(instruction) is fed to an instruction decoder which decodes it and supplied appropriate signals to the
control unit. When the execution has been accomplished the new word in the instruction register is
processed.
iv. Program Counter (PC)
This is a 16-bit register which holds the address of the next instruction that has to be fetched from the
main memory and loaded into the instruction register. The program controlling the operation is stored in
the main memory and instructions are retrieved from this memory normally in order. Therefore, normally
the address contained in the PC is incremented after each instruction is fetched. However, certain classes
of instruction can modify the PC so that the programmer can provide for branching away from the normal
program flow. Examples are instructions in the “jump” and ‘call subroutine’ groups.
v. Stack Pointer(SP)
This is also a 16-bit register and is used by the programmer to maintain a stack in the memory while
using subroutines. The stack is an area of memory used to hold data that will be retrieved soon. The
stack is usually accessed in a Last In First Out (LIFO) fashion.
vi. Status Register or Condition Flags
A status register consisting of a few flip-flops, called as condition flags (in 8085 the number of flags is
five) is used to provide indication of certain conditions that arise during arithmetic and logical operations.
These are:
‘zero’ Flag is set if result of instruction is 0.
‘sign’ Set if MSB of result is 1.
‘parity’ Set if result has even parity.
‘carry’ Set if carry or borrow resulted.
‘auxiliary carry’ Set if instruction caused a carry out of bit 3 and into bit 4 of the resulting value.
vii. Dedicated Registers
Several other registers are incorporated in the µP for its internal operation. They cannot be accessed by
the programmer and hence do not concern much a µP user.

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Organization of a Register: Generally a register is organize as showing in figure 1.3.

Figure 1.3 Internal structure of a general register

Control & Status Registers:

MAR/MBR

THE ARITHMETIC AND LOGIC UNIT (ALU)

The arithmetic-logic unit is a combinational network that performs arithmetic and logical operations on
the data.

THE CONTROL UNIT (CO)

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The CO can be thought of as the heart of the CPU. It controls the I/O devices and transfer of data to and
from the primary storage. It itself is controlled by the individual instructions in programs located in the
primary storage. Instructions are retrieved from the primary storage, one at a time. For this, the control
unit uses the instruction register for holding the current instruction, and an instruction pointer to hold the
address of the next instruction. Each instruction is interpreted (decoded) so that it can be executed. Based
on the instructions, the control unit controls how other parts of the CPU and, in turn, the rest of the
computer system should work so that the instructions are executed in a correct manner. An analogy can
be considered between the CO and the traffic police; the CO decides which action will occur just as the
traffic police takes decisions on which lanes traffic will move or stop and for how long.

Figure 4 The Control Unit

Figure 1.4 illustrates how CO instructs the other parts of the CPU (i.e. ALU and registers) and
the I/O devices on what to do and when to do. In addition, it determines what data are needed, where
they are stored and where to store the results of the operation as well as sends the control signals to the
devices involved in the execution of the instructions. It administers the movement of large amount of
instructions and data used by the computer. To maintain the proper sequence of events required for any
processing task, the control unit uses clock inputs. Thus, the control unit repeats a set of four basic
operations: fetching, decoding, executing and storing.
THE BUSES AND I/O MECHANISM
µC (microcomputer), like all computers, manipulates binary information. The binary information is
represented by binary digits, called bits. µC operates on a group of bits which are referred to as a word.
The number of bits making-µP a word varies with the µP. Common word sizes are 4, 8, 12 and 16 bits
(µPs with 32 bit-word have also of late entered the market). Another binary terms that will be of interest
in subsequent discussions are the byte and the nibble, which represent a set of 8 bits and 4 bits,
respectively. Figure 1.1 shows busses interconnecting various blocks. These busses allow exchange of
words between the blocks. A bus has a wire or line for each bit and thus allows exchange of all bits of a
word in parallel. The processing of bits in the µP is also in parallel. The busses can thus be viewed as

BY TSEKANE ADI L. M.SC. ENG AUTOMATIQUE ROBOTIQUE AND INDUSTRIAL COMPUTING 5

data highways. The width of a bus is the number of signal lines that constitute the bus. The figure shows
for simplicity three busses for distinct functions. Over the address bus, the µP transmits the address of
that I/O device or memory locations which it desires to access. This address is received by all the devices
connected to the processor, but only the device which has been addressed responds. The data bus is used
by the µP to send and receive data to and from different devices (I/O and memory) including instructions
stored in memory. Obviously the address bus is unidirectional and the data bus is bi-directional. The
control bus is used for transmitting and receiving control signals between the µP and various devices in
the system.
THE MACHINE CYCLE
The Indirect Cycle
• Instruction execution may involve one or more memory operands/accesses
• If indirect addressing is used additional accesses are needed
• Can be thought of as additional instruction subcycle
Instruction Cycle with Indirect Cycle

Instruction cycle state diagram

Data Flow (Instruction Fetch)

• Specifics depend on CPU design
• But In general:

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• Fetch
 PC contains address of next instruction
 Address moved to MAR
 Address placed on address bus
 Control unit requests memory read
 Result placed on data bus, copied to MBR, then to IR
 Meanwhile PC incremented by 1 (or length of current instruction)
Data Flow (Fetch Diagram)
Data Flow (Data Fetch)

Data Flow (Indirect Diagram) Data Flow (Execute)

Data Flow (Interrupt Diagram) Data Flow (Interrupt)

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THE PIPELINING Simplified Instruction Cycle

THE INTERRUPT PROCESSING

The table below describe some interrupt

The general detail architecture of the cpu is illustrated in the figure below.

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