DAl ofire

ASsIGN MENT - l

: Oraw the sbructure of N- channel Enhancement type MOSFET- Als0 expain

woYkirg and dsxaw its output
SoUYC Gdke
characteristics
.kSiO2

gubsrate
Working The highly doped NT oregions aTe difused sqhty in to
times connected
oF P Pe silicon subchrate thesubshrate is Some
the OurCe Oherulise it brought out as the fouy th terminl The
dsa and cOUrCe terminals are connected to Nt type doped teqion
+hrouqh the me talic contact The channel absent in thus type
the ansutatinq Sio dayer s stil paesent with isola te S +he termimal
from the subsrate Thig device (3 called the isdate d gate FET
because of the imsulating Layer Of Si02, thi8 Laqer gives Extremety
hqh impot aeeistance operaion:The opera Hon can be Explaincd ntith
tuio operating condi Hons
rvgS is Zero & pasiHive as the voltage s applied blw is derain 9
S0uYCe then due to the absence of n-type channel a gero dain,
cUrrent with pecent
* The positive potential as the qate terminal aepel the inde x
psese nt im the p-type substra te- Ths eesult in ceteati ng an depleron
Carier
eqion near the sioa Insulating Layer that
the p- ty pe Substrate The esultsim creakna on cdepleHon seqion
AS the Vqs beconnes more posi ive the no of Elechrons pre sent OF
GSio (ayer oill incre ase- The increase concentraion of electro
Caeates on imcluced Chanoel which connech the n- type doe
aeqions tlence, the conductiviy im cTea8e3 and cUTYent flocus from
SCUrCe ko daaim through inctud ec
channes
 CN-Chaore)
Ora'n Chaactert'sticg of Snhancenent MOSFE T

ohve eq
lian

6
8

i, Muth Vqs o, Io is no- exictent even when vds iG aPPliec

", For Fixed vaue vgs with increases in vds, Jd mc reases CorYesponagy
during
hiqher
the stt initial eqions of CUrVeS, iust as These s be ca0Se
vds ,the electrons are euppied by the SOUrCe are att ra ctec
1 a m , current becomes constant we catl thu satuation pinCh
OFF IF Vds is imcreased further we fnd that aYe mOYe 0r ess
Constant
Vgs 3 imcreased m vo .So no: Df Stectrpns im the channel altb
gets cre csed.This esutta, he increase in Vp So to qet more Jo
we have t increa se

&.llusrate the entre step-by - step CMDS fabracication P-utetl proCess

CM0S fabei catton: There are number of apprOgches to cMO6 fabyicaho n
sillcon-0n -i nsulotor
imclLdlng the Pw etl, the n wel, the tuin -tob, and the
Proce sses ln order to nroduce the eader to CMOS We oil be
deciqh
concerned mainly will -bsed circuil3-The P wel pAOCCSS oidey osed
pxactice and the n-well poOce SS is also popu lor, particularly as t
easy etro ft to Existing NMDS ünes For the LambQ- base c
ules set ater we cuill a
p-pwell prOce S>
The P-el proceSS :
bsief overview of the fobrication steps may be obtained coi-h
ePescence tD the iqure, nothinq that the basc procescing steps
are of the Same natore as thDse used for nMOS
)
P-w ell Cu-5Nn)
 Poly sitice
A Thin oxicle and
potpilicon

pt mayk
cpashve)
AAAAA

Pt nask
n-diffusion
tneqatv)

peimitive terms, 4ne srUctore consstS oF an n-Fype SubstYate

thicb p- devices may be foomed Ey suitaie maat and aiffUsian
and in osder to acComodato n-type devices, a deep p- bell s diffusedl
mto n -type Substrate The diFfusjon mst be carried out pecial re
since the p-wel doping concentrahon ancl deph will affect of the
n-ransistorS To ochi eve dow threshold voltages CO6 to Iov) we need
eifher deep well diffusion o high tesistivi tyttoey er deep octts
tramsisor S &
equze Laxqe spacin9 b|w the n-type & Ptype
ireg due o Later chip aYea. Vin

Vout Vss

Illus tTate the Entire efep- by -Step NMOS fabrication Process

, Poo ce ssi ng iS takes place on ap- doped di eilicon cystol
wafer on which go0n a 'thick' dayer of Sion
 Substrate

silicon Gur Face m crea s

.Mask -! pattern Sio2 to expose the areas OF transisfors
uhere path n the diffusion dayer 0r gate
Ths mask s Often called
are stequited. epasit thim orde over atl.
thin oxi de

thick oide CINm

3 mask-3 USn9
Deposite polyeilion oveg au, then pattern using
the same mask-3

Remove thim 0ide Layer where it & not covered by polysilicon

J

DifFUsion nt eqion imto thin oxIde has been Amoed

here
transieto dsaing anct SoUTCes Qre thus get atignment the sespect
to the gate shucture
 indowin
0xide

Pateined pay CI -2pm)

On thus 0xide (800-10 O0

DiEFUse nt xeqions into areas where thin oxi de has been aemoved
Transistor dsains nd souYCeS are thus self - aiqninq with stespect o e
qate sructores.

ndiefsion Cipm deep)

maskec
Thictk oxide (s0)
qoLon over all aqain and & then
nith photoxesict and Etched to Expose selector aaeas of polyeillcorn
are tO be
qate and the dain and cource aes other Connecti ngs
made
Contact holes (Cob)
AA

The whole chip then has metal (aluinium) deposited Over 5

SUT Face to thickness tyPicaty of LHm . This metal layer s then
matched anc etched to fosm the aequired inter - conection
31Tlustrate the entire step- by -step NMOS fabricaton proce ss
NIM0S fabsication: The boue F in froduction qern eral aspe cs of the
polysiticon qat fabi cation pce SS Oill now ba
set6 - aiqning Nmos fabsic atio
qiven AS welL as being elevant +heiY con sight the
pstocesses Lsed for Nos aeLe rant CMOS and

PMOS Fabrica hon

NMOS Enhancemeryt NMOS depletion fYom a
CaAHi ed out on a thin wafer ful
etep paoce ssng
Syetal of siticon Of high puify in to which the equised
Cinqle c Oon- Such waFeY8
P-impuiti es are inrodu ced as the csqetal s 9
anc omm thick and aLe
dte tYP Caly 75 to I50mm diameter
doped oitb soy tocon impusay
&5 ohm cm to aohn Cm

Step2! A tayer O Slo2 , dypically of Nm thic kness cll over the

wafer surface to psote c the sefer surface oxide layer
barrier depen auning subsequent pOCeSSinq and provide
tayer IAIhich other patter end Layers can be formed
an
insolHg
 with a phot0 - re distribuHorn of h
P3 The is now
Coverec
SuTface an Even
Sc posited onte The to chieve
wUafber and
equised thrckne6s

StcpH' The photo eSist Layer then Expasc c to uttraviolet

iqht +hrouqh a mask which defines thase eqions into wbich
diffusion s to take place togeHner with- transister Chan ne L, ASsUme
for Eample that those areas Expase d to ultravoilent sadia tion
are
polgmerized but that the area3 Stequive d for diffusion are
Shielded b the mask and Stemain naffected

Step 5 These areas are Subseqenty reactily Efched aUag togethe

KiHh the enderying silicon dioide eo that water Surface Exposed
wincdow alefined ma

Step 6 The temaining photo- seSiet Aermoved then ayer

OTum q0un over:The Entire chip surfa ce poly- sili con deposite a
sUcture poly si | icon -USC d aS gate al ectro de silicon
top gate
Stept Thin oxide is to Expose aIECS into ohi ch n-type
emoved
maus ft es are to be diffOsed to fam the souTCe and sain
Diffus on achelved by heating uater to high tempera ture
and paSsing a qas containing theanddeslred n-type importhy
before soUYCe daaln Seqions process
Forming the gate
aligned
o diffusion

Contart
ho leg

are complete the &ntire

On ce the SUTce and drain aeqions
SOUYce draim G gate
surface again sio>. The sio2 layer uthoqaapn

p aHened
calumm ium Im)
 Ecg9 The whole chip then has model caluminium) depoci ted over is
euYface a thickness tuplca ly of tmThis mutal dayer in them
maskecl and etched to fosurn the eqtied interconnecton patter
4 pescn be the sructurc Of NMoe and derive the expaession for
csain current im borh dinegr and satuYaHon eGions
&volves fromthe useg
The uthole concept of the MOS transis tor
qate of iTduce a change im the chahnet blw
Oravoltaqe and the Hhen be caued to
move from o0TCe
deain, iabich mu
S0urCe ancd cteate by voltaqe
nfluence of o0 &ectric ftelc
to deah under the the charqe
induced is
& OUTCe Smce deperdent
Votes applied b<o dsain YCe vaLtage
vqsrthen lds 3
to Ou electrors uill
depenclent on the qate
Vas Consider a GtrUctore
in wihch
on both rqs and
flow eource the dsoain. (Qc)
Change mdece ed in channel
Electron
transmit time ( )

Frst, transnit time

Ts length Of channd ()
veloci ky cv)
But relocity Y- Hed- Electric fie ld
wlhere u= &lectron 0T hole
s O U e
molbil
Gate
drain

EdS Electri C field Cdrain tD s00Ce)

Noo
Eds = Vds
So that V= NVds

Thos Tas L
Hyds
Non saturated Reqien: gate voLtage
induced in channel ceee to
change and channel Vgs
due o the voLtaqe dirfeence b| w the gate
 that tbe charqe lunit asea = Eq Eins Eoloe
Note
channel
&lectri c-field qate to
here
t9 averaqe b|0 qate and
Eins etativetg permi tivity of insulation
Eq lvgs -ve)-Yes.] thicknesS
D = 0ide
D

D
[cvqs-ve)Vs
[Cvqs-ve) -Vec
L2
NVds
Eins toH
L
D

Tas k a Cvqs-ve)- Yau vds

uthere ke EinsEo
D

Jds cvqs -vpvds- Yds and it s

The factor is of couTSe, cootribute d by qeometry

.
Common factas pscactice to Oite

The qatt capactance

EinsEo WL CparalLel lat)
D
wle aLs0 have
Jds =Ki

Tds - CNcvqs -VE)Va s - V'ds ara

L Capacitance per unit
aomeimes Convinient to ue qatt
ib s
co-Kathes than C

Tds CoOLN [Cvgs-ve)Vas-Yas

L

Tds - Co WCGs Ve) Vas - Vàs

The saturated teqion
saturatian beqins hen \Gs -Vgs-VE
(gVe) cor) ’ current
 Tas-P_ CVqs-Ve)' (o)
Tds gH vqs- VE)°C(or) gate Capacitance
Ias CoCVgs- V)*
The
Expsession derived Por Las hold for both depletion moct &
&nhancement mode deuices
5 TIustrate the entire step -by ecp cM0S fabi ca tioh N-well process
N-wel CMOS clTCUitS are ale0 SuperiOT to p- well becauSe OF
LOwer Substrate bias EFfecta on transistor thrRshold vol taqe aTe
mhexeny doDeT parasitic capacitance asscctatec iith SO UTCe G
dsaim eqions
Man steps in a typically nroell procs S
Fomation of Nuetl pso CeS S

Define Nrm0S and P-MOS

Field and ate oidationg

Form and pattern polqsilicon

pt difFusi on

Nt diFfusion

|Deposite G pattern metaliaton

Over
qlaas uith cuts for bonding pods

AA

A
 etat. ectriC Eins Enln

n-diffusion
’n7 mask
negative

4)

VreP

AAA
AA A AAA

6 Ilusrate the entire Stcp-by-step pM0S fabica tion processwgter' on

pxocessmq takes place on a n-doped silicom crystral
which s goon a tthick dayer of si02
 (HM thiCk, g
A laye Of silicon cioxide (sio) typicalIy
Over the suTface of ater tb protcct the urface

with the photoseS0st on to the

The SuTface ?s non COvered
diSribution of AequiTec
Wafier &Spen to achieve on Even
-thicknees.

The phototesiss ayer is then Exposec to Uv rays throogh

mask hich defineS those aegions into kihich
dcffoston is place
toqetther channels

together with
These QseaS sebsequenty seeadily &tched aoay
afer susface s
silicon dioxlde So that tbe
the unde xiying
exposed in the window deFined by mast.

emoved and a thin Laye

The semalninq photo sesist
Over the Either chip suDface g then
polysiltcoy,
to -form
S depasitec on top of thy gate
 Further photosxesist
pattexn and then coatng the masking alos the poysilicon to
he thin oxiCe s etemoved to Expose area 8
mto which n-type mpurities are to be diffosed to form SOUBe
cain.

Thick oxide (SiO2) s oon OVer all

uitth photoaesi st and gtched
aqin and i8 then masked
to Expose seeCted area of the polysi licon
qate Cnd doain coUrce area

The uhole Chip then has metal deposited over is Sur face to a
thickness typically m.Thus ayer s then magked G ttched to form
Kequlred inter Connection patten.