AD5933

Data Sheet
FEATURES
Programmable output peak-to-peak excitation voltage to a maximum frequency of 100 kHz Programmable frequency sweep capability with serial I2C interface Frequency resolution of 27 bits (<0.1 Hz) Impedance measurement range from 1 k to 10 M Capable of measuring of 100 to 1 k with additional circuitry Internal temperature sensor (2C) Internal system clock option Phase measurement capability System accuracy of 0.5% 2.7 V to 5.5 V power supply operation Temperature range: 40C to +125C 16-lead SSOP package
1 MSPS, 12-Bit Impedance Converter, Network Analyzer AD5933

GENERAL DESCRIPTION
The AD5933 is a high precision impedance converter system solution that combines an on-board frequency generator with a 12-bit, 1 MSPS, analog-to-digital converter (ADC). The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on-board ADC and a discrete Fourier transform (DFT) is processed by an on-board DSP engine. The DFT algorithm returns a real (R) and imaginary (I) data-word at each output frequency. Once calibrated, the magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep is easily calculated. This is done off chip using the real and imaginary register contents, which can be read from the serial I2C interface. A similar device, also available from Analog Devices, Inc., is the AD5934, a 2.7 V to 5.5 V, 250 kSPS, 12-bit impedance converter, with an internal temperature sensor and is packaged in a 16lead SSOP.
APPLICATIONS
Electrochemical analysis Bioelectrical impedance analysis Impedance spectroscopy Complex impedance measurement Corrosion monitoring and protection equipment Biomedical and automotive sensors Proximity sensing Nondestructive testing Material property analysis Fuel/battery cell condition monitoring
MCLK AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
OSCILLATOR
DDS CORE (27 BITS)
DAC ROUT VOUT
SCL SDA
I2C INTERFACE
TEMPERATURE SENSOR
Z()
REAL REGISTER
IMAGINARY REGISTER
AD5933
RFB
1024-POINT DFT VIN ADC (12 BITS) GAIN LPF

05324-001
VDD/2 AGND DGND
Figure 1.
Rev. D
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AD5933 TABLE OF CONTENTS

Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 I2C Serial Interface Timing Characteristics .............................. 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Descriptions.............................................. 8 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 12 System Description......................................................................... 13 Transmit Stage............................................................................. 14 Frequency Sweep Command Sequence................................... 15 Receive Stage ............................................................................... 15 DFT Operation ........................................................................... 15 System Clock............................................................................... 16 Temperature Sensor ................................................................... 16 Temperature Conversion Details.............................................. 16 Temperature Value Register ...................................................... 16 Temperature Conversion Formula........................................... 16 Impedance Calculation.................................................................. 17 Magnitude Calculation .............................................................. 17 Gain Factor Calculation ............................................................ 17 Impedance Calculation Using Gain Factor............................. 17 Gain Factor Variation with Frequency .................................... 17 Two-Point Calibration ............................................................... 18 Two-Point Gain Factor Calculation......................................... 18 Gain Factor Setup Configuration............................................. 18 Gain Factor Recalculation......................................................... 18 Gain Factor Temperature Variation ......................................... 19 Impedance Error......................................................................... 19 Measuring the Phase Across an Impedance ........................... 19 Performing a Frequency Sweep .................................................... 22
Data Sheet
Register Map ................................................................................... 23 Control Register (Register Address 0x80, Register Address 0x81)............................................................................................. 23 Start Frequency Register (Register Address 0x82, Register Address 0x83, Register Address 0x84)..................................... 24 Frequency Increment Register (Register Address 0x85, Register Address 0x86, Register Address 0x87) ..................... 25 Number of Increments Register (Register Address 0x88, Register Address 0x89) .............................................................. 25 Number of Settling Time Cycles Register (Register Address 0x8A, Register Address 0x8B) ................................................. 25 Status Register (Register Address 0x8F).................................. 26 Temperature Data Register (16 BitsRegister Address 0x92, Register Address 0x93) .............................................................. 26 Real and Imaginary Data Registers (16 BitsRegister Address 0x94, Register Address 0x95, Register Address 0x96, Register Address 0x97) .............................................................. 26 Serial Bus Interface......................................................................... 27 General I2C Timing.................................................................... 27 Writing/Reading to the AD5933 .............................................. 28 Block Write.................................................................................. 28 Read Operations......................................................................... 29 Typical Applications....................................................................... 30 Measuring Small Impedances................................................... 30 Biomedical: Noninvasive Blood Impedance Measurement.. 32 Sensor/Complex Impedance Measurement............................ 32 Electro-Impedance Spectroscopy............................................. 33 Choosing a Reference for the AD5933 ........................................ 34 Layout and Configuration............................................................. 35 Power Supply Bypassing and Grounding................................ 35 Evaluation Board ............................................................................ 36 Using the Evaluation Board ...................................................... 36 Prototyping Area ........................................................................ 36 Crystal Oscillator (XO) vs. External Clock............................. 36 Schematics................................................................................... 37 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 41
Rev. D | Page 2 of 44
Data Sheet
REVISION HISTORY
12/11Rev. C to Rev. D Changes to Impedance Error Section...........................................19 Removed Figure 26 and Figure 27; Renumbered Sequentially ..............................................................19 Removed Figure 28, Figure 29, Figure 30, Figure 31 ..................20 Changes to Figure 39 ......................................................................37 Changes to Figure 40 ......................................................................38 Changes to Figure 41 ......................................................................39 Changes to Figure 42 ......................................................................40 8/10Rev. B to Rev. C Changes to Impedance Error Section...........................................19 Changes to Figure 45 ......................................................................38 Changes to U4 Description in Table 19........................................42 2/10Rev. A to Rev. B Changes to General Description .....................................................1
AD5933
5/08Rev. 0 to Rev. A Changes to Layout.............................................................. Universal Changes to Figure 1 ..........................................................................1 Changes to Table 1 ............................................................................4 Changes to Figure 17 ......................................................................13 Changes to System Description Section ......................................13 Changes to Figure 19 ......................................................................14 Changes to Figure 24 ......................................................................18 Changes to Impedance Error Section...........................................19 Added Measuring the Phase Across an Impedance Section .....21 Changes to Register Map Section .................................................24 Added Measuring Small Impedances Section.............................31 Changes to Table 18 ........................................................................35 Added Evaluation Board Section ..................................................37 Changes to Ordering Guide...........................................................43 9/05Revision 0: Initial Version
AD5933 SPECIFICATIONS
Data Sheet
VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 k connected between Pin 5 and Pin 6; feedback resistor = 200 k connected between Pin 4 and Pin 5; PGA gain = 1, unless otherwise noted. Table 1.
Parameter SYSTEM Impedance Range Min 1K Y Version 1 Typ Max 10 M Unit Test Conditions/Comments 100 to 1 k requires extra buffer circuitry, see the Measuring Small Impedances section 2 V p-p output excitation voltage at 30 kHz, 200 k connected between Pin 5 and Pin 6
Total System Accuracy
0.5
System Impedance Error Drift TRANSMIT STAGE Output Frequency Range 2 Output Frequency Resolution MCLK Frequency Internal Oscillator Frequency 3 Internal Oscillator Temperature Coefficient TRANSMIT OUTPUT VOLTAGE Range 1 AC Output Excitation Voltage 4 DC Bias 5 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 2 AC Output Excitation Voltage4 DC Bias5 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 3 AC Output Excitation Voltage4 DC Bias5 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 4 AC Output Excitation Voltage4 DC Bias5 DC Output Impedance Short-Circuit Current to Ground at VOUT SYSTEM AC CHARACTERISTICS Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Wide Band (0 MHz to 1 MHz) Narrow Band (5 kHz)
30 1 0.1 16.776 16.776 30 100
ppm/C kHz Hz MHz MHz ppm/C
<0.1 Hz resolution achievable using DDS techniques Maximum system clock frequency Frequency of internal clock
1.98 1.48 200 5.8 0.97 0.76 2.4 0.25 0.383 0.31 1 0.20 0.198 0.173 600 0.15 60 52 56 85
V p-p V mA V p-p V k mA V p-p V k mA V p-p V mA dB dB dB dB
See Figure 4 for output voltage distribution DC bias of the ac excitation signal; see Figure 5 TA = 25C TA = 25C See Figure 6 DC bias of output excitation signal; see Figure 7
See Figure 8 DC bias of output excitation signal; see Figure 9
See Figure 10 DC bias of output excitation signal. See Figure 11
Data Sheet
Parameter RECEIVE STAGE Input Leakage Current Input Capacitance 6 Feedback Capacitance (CFB) Min Y Version 1 Typ 1 0.01 3 Max Unit nA pF pF
AD5933
Test Conditions/Comments To VIN pin Pin capacitance between VIN and GND Feedback capacitance around currentto-voltage amplifier; appears in parallel with feedback resistor
ANALOG-TO-DIGITAL CONVERTER6 Resolution Sampling Rate TEMPERATURE SENSOR Accuracy Resolution Temperature Conversion Time LOGIC INPUTS Input High Voltage (VIH) Input Low Voltage (VIL) Input Current 7 Input Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode ) IDD (Standby Mode)
12 250 2.0 0.03 800
Bits kSPS C C s
ADC throughput rate 40C to +125C temperature range Conversion time of single temperature measurement
0.7 VDD 0.3 VDD 1 7 2.7 10 17 11 5.5 15 25 A pF V mA mA mA TA = 25C TA = 25C
IDD (Power-Down Mode)
16 0.7 1
5 8
mA A A
VDD = 3.3 V VDD = 5.5 V VDD = 3.3 V; see the Control Register (Register Address 0X80, Register Address 0X81) section VDD = 5.5 V VDD = 3.3 V VDD = 5.5 V
1 2
Temperature range for Y version = 40C to +125C, typical at 25C. The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5933. 3 Refer to Figure 14, Figure 15, and Figure 16 for the internal oscillator frequency distribution with temperature. 4 The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula: Output Excitation Voltage (V p-p) = [2/3.3] VDD where VDD is the supply voltage. 5 The dc bias value of the output excitation voltage scales with supply voltage according to the following formula: Output Excitation Bias Voltage (V) = [2/3.3] VDD where VDD is the supply voltage. 6 Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of currentto-voltage amplifier. 7 The accumulation of the currents into Pin 8, Pin 15, and Pin 16.
AD5933
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. 1 Table 2.
Parameter 2 fSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 250 20 + 0.1 Cb 4 400 Unit kHz max s min s min s min s min ns min s max s min s min s min s min ns max ns min ns max ns min ns max ns min pF max Description
Data Sheet
Cb
1 2
SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT, data hold time tHD, DAT, data hold time tSU, STA, setup time for repeated start tSU, STO, stop condition setup time tBUF, bus free time between a stop and a start condition tF, rise time of SDA when transmitting tR, rise time of SCL and SDA when receiving (CMOS compatible) tF, fall time of SCL and SDA when transmitting tF, fall time of SDA when receiving (CMOS compatible) tF, fall time of SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line
See Figure 2. Guaranteed by design and characterization, not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL. 4 Cb is the total capacitance of one bus line in picofarads. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t3
t10
t11
t4
SCL
t4
START CONDITION
t6
t2
t5
t7
REPEATED START CONDITION
t1
t8
STOP CONDITION
05324-002
Figure 2. I2C Interface Timing Diagram
Data Sheet ABSOLUTE MAXIMUM RATINGS

TA = 25C, unless otherwise noted. Table 3.
Parameter DVDD to GND AVDD1 to GND AVDD2 to GND SDA/SCL to GND VOUT to GND VIN to GND MCLK to GND Operating Temperature Range Extended Industrial (Y Grade) Storage Temperature Range Maximum Junction Temperature SSOP Package, Thermal Impedance JA JC Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating 0.3 V to +7.0 V 0.3 V to +7.0 V 0.3 V to +7.0 V 0.3 V to VDD + 0.3 V 0.3 V to VDD + 0.3 V 0.3 V to VDD + 0.3 V 0.3 V to VDD + 0.3 V 40C to +125C 65C to +160C 150C 139C/W 136C/W 260C 10 sec to 40 sec
AD5933
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
AD5933 PIN CONFIGURATION AND DESCRIPTIONS

NC 1 NC 2 NC 3 RFB 4 VIN 5 VOUT 6 NC 7 MCLK 8 NC = NO CONNECT NOTES: 1. IT IS RECOMMENDED TO TIE ALL SUPPLY CONNECTIONS (PIN 9, PIN 10, AND PIN 11) AND RUN FROM A SINGLE SUPPLY BETWEEN 2.7V AND 5.5V. IT IS ALSO RECOMMENDED TO CONNECT ALL GROUND SIGNALS TOGETHER (PIN 12, PIN 13, AND PIN 14).
16 15
Data Sheet
SCL SDA AGND2 AGND1 DGND AVDD2 AVDD1 DVDD
TOP VIEW (Not to Scale)
AD5933
14 13 12 11 10 9
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions

Pin No. 1, 2, 3, 7 4 5 6 8 9 10 11 12 13 14 15 16 Mnemonic NC RFB VIN VOUT MCLK DVDD AVDD1 AVDD2 DGND AGND1 AGND2 SDA SCL Description No Connect. External Feedback Resistor. Connected from Pin 4 to Pin 5 and used to set the gain of the current-to-voltage amplifier on the receive side. Input to Receive Transimpedance Amplifier. Presents a virtual earth voltage of VDD/2. Excitation Voltage Signal Output. The master clock for the system is supplied by the user. Digital Supply Voltage. Analog Supply Voltage 1. Analog Supply Voltage 2. Digital Ground. Analog Ground 1. Analog Ground 2. I2C Data Input. Open-drain pins requiring 10 k pull-up resistors to VDD. I2C Clock Input. Open-drain pins requiring 10 k pull-up resistors to VDD.
05324-003
Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS

35 MEAN = 1.9824 SIGMA = 0.0072 30 25 20 15 10 5 0 1.92
AD5933
30 MEAN = 0.7543 SIGMA = 0.0099 25
NUMBER OF DEVICES
05324-004
NUMBER OF DEVICES
20
15
10
1.94
1.96
1.98
2.00
2.02
2.04
2.06
0.70
0.72
0.74
0.76
0.78
0.80
0.82
0.84
0.86
VOLTAGE (V)
VOLTAGE (V)
Figure 4. Range 1 Output Excitation Voltage Distribution, VDD = 3.3 V

30 MEAN = 1.4807 SIGMA = 0.0252 25
NUMBER OF DEVICES
NUMBER OF DEVICES 25 30
Figure 7. Range 2 DC Bias Distribution, VDD = 3.3 V
MEAN = 0.3827 SIGMA = 0.00167
20
20
15
15
10
10
05324-005
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
0.375
0.380
0.385 VOLTAGE (V)
0.390
0.395
0.400
VOLTAGE (V)

30 MEAN = 0.9862 SIGMA = 0.0041 25
NUMBER OF DEVICES

30 MEAN = 0.3092 SIGMA = 0.0014 25
NUMBER OF DEVICES
20
20
15
15
10
10
0.295
0.300
0.305 VOLTAGE (V)
0.310
0.315
0.320
VOLTAGE (V)
05324-009
0.96
0.97
0.98
0.99
1.00
1.01
1.02
05324-006
0 0.95
0 0.290
05324-008
0 1.30
0 0.370
05324-007
0 0.68
AD5933
30 MEAN = 0.1982 SIGMA = 0.0008 25
NUMBER OF DEVICES 15.8 15.3 14.8 14.3
Data Sheet
AVDD1, AVDD2, DVDD CONNECTED TOGETHER. OUTPUT EXCITATION FREQUENCY = 30kHz RFB, ZCALIBRATION = 100k
20
IDD (mA)
13.8 13.3 12.8 12.3 11.8 11.3
15
10
05324-010
0.194
0.196
0.198
0.200
0.202
0.204
0.206
10
12
14
16
18
VOLTAGE (V)
MCLK FREQUENCY (MHz)

30 MEAN = 0.1792 SIGMA = 0.0024 25
PHASE ERROR (Degrees) NUMBER OF DEVICES 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0
05324-011
Figure 12. Typical Supply Current vs. MCLK Frequency
VDD = 3.3V TA = 25C f = 32kHz
20
15
10
50
100
150
200
250
300
350
400
VOLTAGE (V)
PHASE (Degrees)
Figure 13. Typical Phase Error
05324-013
0 0.160 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 0.205
05324-012
0 0.192
10.8
Data Sheet
12 10 8 COUNT COUNT 8 6 4 2 0 16.4 16.6 16.8 17.0 17.2 OSCILLATOR FREQUENCY (MHz) N = 106 MEAN = 16.8292 SD = 0.142904 TEMP = 40C 12 N = 100 MEAN = 16.7257 SD = 0.137633 TEMP = 125C
AD5933
10
05324-014
16.4
16.6
16.8
17.0
17.2
OSCILLATOR FREQUENCY (MHz)
Figure 14. Frequency Distribution of Internal Oscillator at 40C

16 14 12 10
COUNT
N = 100 MEAN = 16.7811 SD = 0.0881565 TEMP = 25C
8 6 4 2 0
16.4
16.6
16.8
17.0
17.2
OSCILLATOR FREQUENCY (MHz)
05324-015
05324-016
AD5933 TERMINOLOGY
Total System Accuracy The AD5933 can accurately measure a range of impedance values to less than 0.5% of the correct impedance value for supply voltages between 2.7 V to 5.5 V. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The spurious-free dynamic range refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 Hz to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of 200 kHz, about the fundamental frequency.
Data Sheet
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental, where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. For the AD5933, THD is defined as
THD (dB) = 20 log
V2 2 + V3 2 + V4 2 + V 5 2 V6 2 V1
Data Sheet SYSTEM DESCRIPTION

MCLK DDS CORE (27 BITS) COS SCL MICROCONTROLLER SDA I2C INTERFACE SIN TEMPERATURE SENSOR Z() REAL REGISTER IMAGINARY REGISTER DAC ROUT VOUT
AD5933
OSCILLATOR
AD5933
RFB PROGRAMMABLE GAIN AMPLIFIER VIN ADC (12 BITS) LPF 5 1 VDD/2
05324-017
MAC CORE (1024 DFT) WINDOWING OF DATA MCLK
Figure 17. Block Overview
The AD5933 is a high precision impedance converter system solution that combines an on-board frequency generator with a 12-bit, 1 MSPS ADC. The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on-board ADC and DFT processed by an on-board DSP engine. The DFT algorithm returns both a real (R) and imaginary (I) data-word at each frequency point along the sweep. The impedance magnitude and phase are easily calculated using the following equations:
Magnitude = R 2 + I 2
Phase = tan1(I/R)
The AD5933 permits the user to perform a frequency sweep with a user-defined start frequency, frequency resolution, and number of points in the sweep. In addition, the device allows the user to program the peak-to-peak value of the output sinusoidal signal as an excitation to the external unknown impedance connected between the VOUT and VIN pins. Table 5 gives the four possible output peak-to-peak voltages and the corresponding dc bias levels for each range for 3.3 V. These values are ratiometric with VDD. So for a 5 V supply
Output Excitation Voltage for Range 1 = 1.98 Output DC Bias Voltage for Range 1 = 1.48 5.0 =3 V pp 3.3
To characterize an impedance profile Z(), generally a frequency sweep is required, like that shown in Figure 18.
5.0 = 2.24 V p p 3.3
Table 5. Voltage Levels Respective Bias Levels for 3.3 V

Range 1 2 3 4 Output Excitation Voltage Amplitude 1.98 V p-p 0.97 V p-p 383 mV p-p 198 mV p-p Output DC Bias Level 1.48 V 0.76 V 0.31 V 0.173 V
IMPEDANCE
FREQUENCY
Figure 18. Impedance vs. Frequency Profile
The excitation signal for the transmit stage is provided on-chip using DDS techniques that permit subhertz resolution. The receive stage receives the input signal current from the unknown impedance, performs signal processing, and digitizes the result. The clock for the DDS is generated from either an external reference clock, which is provided by the user at MCLK, or by the internal oscillator. The clock for the DDS is determined by the status of Bit D3 in the control register (see Register Address 0x81 in the Register Map section).
05324-018
AD5933
TRANSMIT STAGE
As shown in Figure 19, the transmit stage of the AD5933 is made up of a 27-bit phase accumulator DDS core that provides the output excitation signal at a particular frequency. The input to the phase accumulator is taken from the contents of the start frequency register (see Register Address 0x82, Register Address 0x83, and Register Address 0x84). Although the phase accumulator offers 27 bits of resolution, the start frequency register has the three most significant bits (MSBs) set to 0 internally; therefore, the user has the ability to program only the lower 24 bits of the start frequency register.
R(GAIN) PHASE ACCUMULATOR (27 BITS)
Data Sheet
Frequency Increment
This is a 24-bit word that is programmed to the on-board RAM at Register Address 0x85, Register Address 0x86, and Register Address 0x87 (see the Register Map). The required code loaded to the frequency increment register is the result of the formula shown in Equation 2, based on the master clock frequency and the required increment frequency output from the DDS. Frequency Increment Code = Re quired Frequency Increment 27 2 MCLK 4 (2)
DAC VOUT VBIAS

05324-019
Figure 19. Transmit Stage
For example, if the user requires the sweep to have a resolution of 10 Hz and has a 16 MHz clock signal connected to MCLK, the code that needs to be programmed is given by
The AD5933 offers a frequency resolution programmable by the user down to 0.1 Hz. The frequency resolution is programmed via a 24-bit word loaded serially over the I2C interface to the frequency increment register. The frequency sweep is fully described by the programming of three parameters: the start frequency, the frequency increment, and the number of increments.
10 Hz Frequency Increment Code = 0x00014F 16 MHz 4 The user programs the value of 0x00 to Register Address 0x85, the value of 0x01 to Register Address 0x86, and the value of 0x4F to Register Address 0x87.
Start Frequency
This is a 24-bit word that is programmed to the on-board RAM at Register Address 0x82, Register Address 0x83, and Register Address 0x84 (see the Register Map section). The required code loaded to the start frequency register is the result of the formula shown in Equation 1, based on the master clock frequency and the required start frequency output from the DDS. Start Frequency Code = Required Output Start Frequency 27 2 MCLK 4 (1)
Number of Increments
This is a 9-bit word that represents the number of frequency points in the sweep. The number is programmed to the on-board RAM at Register Address 0x88 and Register Address 0x89 (see the Register Map section). The maximum number of points that can be programmed is 511. For example, if the sweep needs 150 points, the user programs the value of 0x00 to Register Address 0x88 and the value of 0x96 to Register Address 0x89. Once the three parameter values have been programmed, the sweep is initiated by issuing a start frequency sweep command to the control register at Register Address 0x80 and Register Address 0x81 (see the Register Map section). Bit D2 in the status register (Register Address 0x8F) indicates the completion of the frequency measurement for each sweep point. Incrementing to the next frequency sweep point is under the control of the user. The measured result is stored in the two register groups that follow: 0x94, 0x95 (real data) and 0x96, 0x97 (imaginary data) that should be read before issuing an increment frequency command to the control register to move to the next sweep point. There is the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the control register. This has the benefit of allowing the user to average successive readings. When the frequency sweep has completed all frequency points, Bit D3 in the status register is set, indicating completion of the sweep. Once this bit is set, further increments are disabled.
For example, if the user requires the sweep to begin at 30 kHz and has a 16 MHz clock signal connected to MCLK, the code that needs to be programmed is given by
30 kHz 27 Start Frequency Code = 2 0x0F5C28 16 MHz 4 The user programs the value of 0x0F to Register Address 0x82, the value of 0x5C to Register Address 0x83, and the value of 0x28 to Register Address 0x84.
Data Sheet
FREQUENCY SWEEP COMMAND SEQUENCE
The following sequence must be followed to implement a frequency sweep: 1. Enter standby mode. Prior to issuing a start frequency sweep command, the device must be placed in a standby mode by issuing an enter standby mode command to the control register (Register Address 0x80 and Register Address 0x81). In this mode, the VOUT and VIN pins are connected internally to ground so there is no dc bias across the external impedance or between the impedance and ground. Enter initialize mode. In general, high Q complex circuits require a long time to reach steady state. To facilitate the measurement of such impedances, this mode allows the user full control of the settling time requirement before entering start frequency sweep mode where the impedance measurement takes place. An initialize with a start frequency command to the control register enters initialize mode. In this mode the impedance is excited with the programmed start frequency, but no measurement takes place. The user times out the required settling time before issuing a start frequency sweep command to the control register to enter the start frequency sweep mode. Enter start frequency sweep mode. The user enters this mode by issuing a start frequency sweep command to the control register. In this mode, the ADC starts measuring after the programmed number of settling time cycles has elapsed. The user can program an integer number of output frequency cycles (settling time cycles) to Register Address 0x8A and Register Address 0x8B before beginning the measurement at each frequency point (see Figure 28).
AD5933
RECEIVE STAGE
The receive stage comprises a current-to-voltage amplifier, followed by a programmable gain amplifier (PGA), antialiasing filter, and ADC. The receive stage schematic is shown in Figure 20. The unknown impedance is connected between the VOUT and VIN pins. The first stage current-to-voltage amplifier configuration means that a voltage present at the VIN pin is a virtual ground with a dc value set at VDD/2. The signal current that is developed across the unknown impedance flows into the VIN pin and develops a voltage signal at the output of the currentto-voltage converter. The gain of the current-to voltage amplifier is determined by a user-selectable feedback resistor connected between Pin 4 (RFB) and Pin 5 (VIN). It is important for the user to choose a feedback resistance value that, in conjunction with the selected gain of the PGA stage, maintains the signal within the linear range of the ADC (0 V to VDD). The PGA allows the user to gain the output of the current-tovoltage amplifier by a factor of 5 or 1, depending upon the status of Bit D8 in the control register (see the Register Map section, Register Address 0x80). The signal is then low-pass filtered and presented to the input of the 12-bit, 1 MSPS ADC.
R C RFB 5R R VIN VDD/2 LPF R
05324-020
2.
3.
ADC
Figure 20. Receive Stage
The DDS output signal is passed through a programmable gain stage to generate the four ranges of peak-to-peak output excitation signals listed in Table 5. The peak-to-peak output excitation voltage is selected by setting Bit D10 and Bit D9 in the control register (see the Control Register (Register Address 0X80, Register Address 0X81) section) and is made available at the VOUT pin.
The digital data from the ADC is passed directly to the DSP core of the AD5933, which performs a DFT on the sampled data.
DFT OPERATION
A DFT is calculated for each frequency point in the sweep. The AD5933 DFT algorithm is represented by
X( f ) =
1023
n=0
(x(n)(cos(n) j sin(n)))
where: X(f) is the power in the signal at the Frequency Point f. x(n) is the ADC output. cos(n) and sin(n) are the sampled test vectors provided by the DDS core at the Frequency Point f. The multiplication is accumulated over 1024 samples for each frequency point. The result is stored in two, 16-bit registers representing the real and imaginary components of the result. The data is stored in twos complement format.
AD5933
SYSTEM CLOCK
The system clock for the AD5933 can be provided in one of two ways. The user can provide a highly accurate and stable system clock at the external clock pin (MCLK). Alternatively, the AD5933 provides an internal clock with a typical frequency of 16.776 MHz by means of an on-chip oscillator. The user can select the preferred system clock by programming Bit D3 in the control register (Register Address 0x81, see Table 11). The default clock option on power-up is selected to be the internal oscillator. The frequency distribution of the internal clock with temperature can be seen in Figure 14, Figure 15, and Figure 16.
Table 6. Temperature Data Format
Temperature 40C 30C 25C 10C 0.03125C 0C +0.03125C +10C +25C +50C +75C +100C +125C +150C
Data Sheet
Digital Output D13D0 11, 1011, 0000, 0000 11, 1100, 0100, 0000 11, 1100, 1110, 0000 11, 1110, 1100, 0000 11, 1111, 1111, 1111 00, 0000, 0000, 0000 00, 0000, 0000, 0001 00, 0001, 0100, 0000 00, 0011, 0010, 0000 00, 0110, 0100, 0000 00, 1001, 0110, 0000 00, 1100, 1000, 0000 00, 1111, 1010, 0000 01, 0010, 1100, 0000
TEMPERATURE SENSOR
The temperature sensor is a 13-bit digital temperature sensor with a 14th bit that acts as a sign bit. The on-chip temperature sensor allows an accurate measurement of the ambient device temperature to be made. The measurement range of the sensor is 40C to +125C. At +150C, the structural integrity of the device starts to deteriorate when operated at voltage and temperature maximum specifications. The accuracy within the measurement range is 2C.
TEMPERATURE CONVERSION FORMULA

Positive Temperature = ADC Code (D)/32 Negative Temperature = (ADC Code (D) 16384)/32 where ADC Code uses all 14 bits of the data byte, including the sign bit. Negative Temperature = (ADC Code (D) 8192)/32 where ADC Code (D) is D13, the sign bit, and is removed from the ADC code.)
01, 0010, 1100, 0000
TEMPERATURE CONVERSION DETAILS

The conversion clock for the part is internally generated; no external clock is required except when reading from and writing to the serial port. In normal mode, an internal clock oscillator runs an automatic conversion sequence. The temperature sensor block defaults to a power-down state. To perform a measurement, a measure temperature command is issued by the user to the control register (Register Address 0x80 and Register Address 0x81). After the temperature operation is complete (typically 800 s later), the block automatically powers down until the next temperature command is issued. The user can poll the status register (Register Address 0x8F) to see if a valid temperature conversion has taken place, indicating that valid temperature data is available to read at Register Address 0x92 and Register Address 0x93 (see the Register Map section).
DIGITAL OUTPUT
00, 1001, 0110, 0000
75C
00, 0000, 0000, 0001 0.03125C 40C 30C 11, 1111, 1111, 1111 TEMPERATURE (C)
TEMPERATURE VALUE REGISTER

The temperature value register is a 16-bit, read-only register that stores the temperature reading from the ADC in 14-bit, twos complement format. The two MSB bits are dont cares. D13 is the sign bit. The internal temperature sensor is guaranteed to a low value limit of 40C and a high value limit of +150C. The digital output stored in Register Address 0x92 and Register Address 0x93 for the various temperatures is outlined in Table 6. The temperature sensor transfer characteristic is shown in Figure 21.
150C
11, 1100, 0100, 0000

05324-021
11, 1011, 0000, 0000
Figure 21. Temperature Sensor Transfer Function
Data Sheet IMPEDANCE CALCULATION

MAGNITUDE CALCULATION
The first step in impedance calculation for each frequency point is to calculate the magnitude of the DFT at that point. The DFT magnitude is given by Magnitude = R 2 + I 2 where: R is the real number stored at Register Address 0x94 and Register Address 0x95. I is the imaginary number stored at Register Address 0x96 and Register Address 0x97. For example, assume the results in the real data and imaginary data registers are as follows at a frequency point: Real data register = 0x038B = 907 decimal Imaginary data register = 0x0204 = 516 decimal
Magnitude = (907 2 + 516 2 ) = 1043.506
AD5933
1 200 k = 515.819 10 -12 Gain Factor = 9692.106
IMPEDANCE CALCULATION USING GAIN FACTOR

The next example illustrates how the calculated gain factor derived previously is used to measure an unknown impedance. For this example, assume that the unknown impedance = 510 k. After measuring the unknown impedance at a frequency of 30 kHz, assume that the real data and imaginary data registers contain the following data: Real data register = 0xFA3F = 1473 decimal Imaginary data register = 0x0DB3 = +3507 decimal
Magnitude = ((1473) 2 + (3507) 2 ) = 3802.863
To convert this number into impedance, it must be multiplied by a scaling factor called the gain factor. The gain factor is calculated during the calibration of the system with a known impedance connected between the VOUT and VIN pins. Once the gain factor has been calculated, it can be used in the calculation of any unknown impedance between the VOUT and VIN pins.
Then the measured impedance at the frequency point is given by Impedance = 1 Gain Factor Magnitude
1 = 509.791 k 515.819273 10 12 3802.863
GAIN FACTOR VARIATION WITH FREQUENCY

Because the AD5933 has a finite frequency response, the gain factor also shows a variation with frequency. This variation in gain factor results in an error in the impedance calculation over a frequency range. Figure 22 shows an impedance profile based on a single-point gain factor calculation. To minimize this error, the frequency sweep should be limited to as small a frequency range as possible.
101.5 VDD = 3.3V CALIBRATION FREQUENCY = 60kHz TA = 25C MEASURED CALIBRATION IMPEDANCE = 100k
GAIN FACTOR CALCULATION

An example of a gain factor calculation follows, with the following assumptions: Output excitation voltage = 2 V p-p Calibration impedance value, ZCALIBRATION = 200 k PGA Gain = 1 Current-to-voltage amplifier gain resistor = 200 k Calibration frequency = 30 kHz Then typical contents of the real data and imaginary data registers after a frequency point conversion are: Real data register = 0xF064 = 3996 decimal Imaginary data register = 0x227E = +8830 decimal Magnitude = (3996) 2 + (8830)2 = 9692.106 1 Impedance Admittance Gain Factor = = Code Magnitude
101.0
IMPEDANCE (k)
100.5
100.0
99.5
99.0
56
58
60
62
64
66
FREQUENCY (kHz)
Figure 22. Impedance Profile Using a Single-Point Gain Factor Calculation
05324-022
98.5 54
AD5933
TWO-POINT CALIBRATION
Alternatively, it is possible to minimize this error by assuming that the frequency variation is linear and adjusting the gain factor with a two-point calibration. Figure 23 shows an impedance profile based on a two-point gain factor calculation.
101.5 VDD = 3.3V CALIBRATION FREQUENCY = 60kHz TA = 25C MEASURED CALIBRATION IMPEDANCE = 100k
VOUT
Data Sheet
GAIN FACTOR SETUP CONFIGURATION
When calculating the gain factor, it is important that the receive stage operate in its linear region. This requires careful selection of the excitation signal range, current-to-voltage gain resistor, and PGA gain.
CURRENT-TO-VOLTAGE GAIN SETTING RESISTOR RFB ZUNKNOWN LPF
05324-024
101.0
IMPEDANCE (k)
100.5
VIN VDD/2 PGA (1 OR 5)
ADC
100.0
Figure 24. System Voltage Gain

99.5
The gain through the system shown in Figure 24 is given by

Ouput Excitation Voltage Range
05324-023
99.0
98.5 54
56
58
60
62
64
66
Gain Setting Re sistor ZUNKNOWN
PGA Gain
FREQUENCY (kHz)
Figure 23. Impedance Profile Using a Two-Point Gain Factor Calculation
For this example, assume the following system settings: VDD = 3.3 V Gain setting resistor = 200 k ZUNKNOWN = 200 k PGA setting = 1 The peak-to-peak voltage presented to the ADC input is 2 V p-p. However, if a PGA gain of 5 was chose, the voltage would saturate the ADC.
TWO-POINT GAIN FACTOR CALCULATION

This is an example of a two-point gain factor calculation assuming the following: Output excitation voltage = 2 V (p-p) Calibration impedance value, ZUNKNOWN = 100.0 k PGA gain = 1 Supply voltage = 3.3 V Current-to-voltage amplifier gain resistor = 100 k Calibration frequencies = 55 kHz and 65 kHz Typical values of the gain factor calculated at the two calibration frequencies read Gain factor calculated at 55 kHz is 1.031224E-09 Gain factor calculated at 65 kHz is 1.035682E-09 Difference in gain factor (GF) is 1.035682E-09 1.031224E-09 = 4.458000E-12 Frequency span of sweep (F) = 10 kHz Therefore, the gain factor required at 60 kHz is given by 4.458000E - 12 5 kHz + 1.031224 10 -9 10 kHz The required gain factor is 1.033453E-9. The impedance is calculated as previously described.
GAIN FACTOR RECALCULATION

The gain factor must be recalculated for a change in any of the following parameters: Current-to-voltage gain setting resistor Output excitation voltage PGA gain
Data Sheet
GAIN FACTOR TEMPERATURE VARIATION
The typical impedance error variation with temperature is in the order of 30 ppm/C. Figure 25 shows an impedance profile with a variation in temperature for 100 k impedance using a two-point gain factor calibration.
101.5 VDD = 3.3V CALIBRATION FREQUENCY = 60kHz MEASURED CALIBRATION IMPEDANCE = 100k
AD5933
by calculating the magnitude of the real and imaginary components of the DFT given by the following formula:
Magnitude = R 2 + I 2
After each measurement, multiply it by the calibration term and invert the product. The magnitude of the impedance is, therefore, given by the following formula:
Impedance =
101.0
+125C
IMPEDANCE (k)
100.5
1 Gain Factor Magnitude
Where gain factor is given by

100.0 +25C 99.5 40C 99.0
1 Impedance Admittance Gain Factor = = Code Magnitude The user must calibrate the AD5933 system for a known impedance range to determine the gain factor before any valid measurement can take place. Therefore, the user must know the impedance limits of the complex impedance (ZUNKNOWN) for the sweep frequency range of interest. The gain factor is determined by placing a known impedance between the input/output of the AD5933 and measuring the resulting magnitude of the code. The AD5933 system gain settings need to be chosen to place the excitation signal in the linear region of the on-board ADC. Because the AD5933 returns a complex output code made up of real and imaginary components, the user can also calculate the phase of the response signal through the AD5933 signal path. The phase is given by the following formula:
Phase(rads) = tan1(I/R)
56
58
60
62
64
66
FREQUENCY (kHz)
Figure 25. Impedance Profile Variation with Temperature Using a Two-Point Gain Factor Calibration
IMPEDANCE ERROR
It is important when reading the following section to note that the output impedance associated with the excitation voltages was actually measured and then calibrated out for each impedance error measurement. This was done using a Keithley current source/sink and measuring the voltage. ROUT (for example ,200 specified for a 1.98 V p-p in the specification table) is only a typical specification and can vary from part to part. This method may not be achievable for large volume applications and in such cases, it is advised to use an extra low impedance output amplifier, as shown in Figure 4, to improve accuracy. Please refer to CN-0217 for impedance accuracy examples on the AD5933 product web-page.
05324-025
98.5 54
(3)
The phase measured by Equation 3 accounts for the phase shift introduced to the DDS output signal as it passes through the internal amplifiers on the transmit and receive side of the AD5933 along with the low-pass filter and also the impedance connected between the VOUT and VIN pins of the AD5933. The parameters of interest for many users are the magnitude of the impedance (|ZUNKNOWN|) and the impedance phase (Z). The measurement of the impedance phase (Z) is a two step process. The first step involves calculating the AD5933 system phase. The AD5933 system phase can be calculated by placing a resistor across the VOUT and VIN pins of the AD5933 and calculating the phase (using Equation 3) after each measurement point in the sweep. By placing a resistor across the VOUT and VIN pins, there is no additional phase lead or lag introduced to the AD5933 signal path and the resulting phase is due entirely to the internal poles of the AD5933, that is, the system phase. Once the system phase has been calibrated using a resistor, the second step involves calculating the phase of any unknown impedance by inserting the unknown impedance between the VIN and VOUT terminals of the AD5933 and recalculating the
MEASURING THE PHASE ACROSS AN IMPEDANCE

The AD5933 returns a complex output code made up of separate real and imaginary components. The real component is stored at Register Address 0x94 and Register Address 0x95 and the imaginary component is stored at Register Address 0x96 and Register Address 0x97 after each sweep measurement. These correspond to the real and imaginary components of the DFT and not the resistive and reactive components of the impedance under test. For example, it is a very common misconception to assume that if a user is analyzing a series RC circuit, the real value stored in Register Address 0x94 and Register Address 0x95 and the imaginary value stored at Register Address 0x96 and Register Address 0x97 correspond to the resistance and capacitive reactance, respectfully. However, this is incorrect because the magnitude of the impedance (|Z|) can be calculated
AD5933
new phase (including the phase due to the impedance) using the same formula. The phase of the unknown impedance (Z) is given by the following formula:
Z = ( unknown system)
Data Sheet
The phase difference (that is, Z) between the phase response of a capacitor and the system phase response using a resistor is the impedance phase of the capacitor, Z (see Figure 27).
100 90 80 70 PHASE (Degrees) 60 50 40 30 20 10 0 15k 30k 45k 60k 75k FREQUENCY (Hz) 90k 105k 120k
05324-033
where:
system is the phase of the system with a calibration resistor
connected between VIN and VOUT. unknown is the phase of the system with the unknown impedance connected between VIN and VOUT. Z is the phase due to the impedance, that is, the impedance phase. Note that it is possible to calculate the gain factor and to calibrate the system phase using the same real and imaginary component values when a resistor is connected between the VOUT and VIN pins of the AD5933, for example, measuring the impedance phase (Z) of a capacitor. The excitation signal current leads the excitation signal voltage across a capacitor by 90 degrees. Therefore, an approximate 90 degree phase difference exists between the system phase responses measured with a resistor and that of the system phase responses measured with a capacitive impedance. As previously outlined, if the user would like to determine the phase angle of capacitive impedance (Z), the user first has to determine the system phase response ( system ) and subtract this from the phase calculated with the capacitor connected between VOUT and VIN (unknown).
A plot showing the AD5933 system phase response calculated using a 220 k calibration resistor (RFB = 220 k, PGA = 1) and the repeated phase measurement with a 10 pF capacitive impedance is shown in Figure 26. One important point to note about the phase formula used to plot Figure 26 is that it uses the arctangent function that returns a phase angle in radians and, therefore, it is necessary to convert from radians to degrees.
200 180 160
SYSTEM PHASE (Degrees)
Figure 27. Phase Response of a Capacitor
Also when using the real and imaginary values to interpret the phase at each measurement point, take care when using the arctangent formula. The arctangent function returns the correct standard phase angle only when the sign of the real and imaginary values are positive, that is, when the coordinates lie in the first quadrant. The standard angle is the angle taken counterclockwise from the positive real x-axis. If the sign of the real component is positive and the sign of the imaginary component is negative, that is, the data lies in the second quadrant, then the arctangent formula returns a negative angle and it is necessary to add a further 180 degrees to calculate the correct standard angle. Likewise, when the real and imaginary components are both negative, that is, when the coordinates lie in the third quadrant, then the arctangent formula returns a positive angle and it is necessary to add 180 degrees from the angle to return the correct standard phase. Finally, when the real component is positive and the imaginary component is negative, that is, the data lies in the fourth quadrant, then the arctangent formula returns a negative angle. It is necessary to add 360 degrees to the angle to calculate the correct phase angle. Therefore, the correct standard phase angle is dependent upon the sign of the real and imaginary component and is summarized in Table 7.
220k RESISTOR
140 120 100 80 10pF CAPACITOR 60 40 20 0 15k 30k 45k 60k 75k FREQUENCY (Hz) 90k 105k 120k
05324-032
Figure 26. System Phase Response vs. Capacitive Phase
Data Sheet
Once the magnitude of the impedance (|Z|) and the impedance phase angle (Z, in radians) are correctly calculated, it is possible to determine the magnitude of the real (resistive) and imaginary (reactive) component of the impedance (ZUNKNOWN) by the vector projection of the impedance magnitude onto the real and imaginary impedance axis using the following formulas: The real component is given by |ZREAL| = |Z| cos (Z) The imaginary component is given by |ZIMAG| = |Z| sin (Z)
Positive Negative Fourth
AD5933
Table 7. Phase Angle
Real Positive Positive Imaginary Positive Negative Quadrant First Second Phase Angle
tan 1( I / R )
180
180 180 + tan 1 (I / R )
Negative
Negative
Third
180 180 + tan 1 (I / R )

180 360 + tan 1 ( I / R )
AD5933 PERFORMING A FREQUENCY SWEEP

PROGRAM FREQUENCY SWEEP PARAMETERS INTO RELEVANT REGISTERS (1) START FREQUENCY REGISTER (2) NUMBER OF INCREMENTS REGISTER (3) FREQUENCY INCREMENT REGISTER
Data Sheet
PLACE THE AD5933 INTO STANDBY MODE. RESET: BY ISSUING A RESET COMMAND TO CONTROL REGISTER THE DEVICE IS PLACED IN STANDBY MODE. PROGRAM INITIALIZE WITH START FREQUENCY COMMAND TO THE CONTROL REGISTER.
AFTER A SUFFICIENT AMOUNT OF SETTLING TIME HAS ELAPSED, PROGRAM START FREQUENCY SWEEP COMMAND IN THE CONTROL REGISTER.
POLL STATUS REGISTER TO CHECK IF THE DFT CONVERSION IS COMPLETE. N Y READ VALUES FROM REAL AND IMAGINARY DATA REGISTER. PROGRAM THE INCREMENT FREQUENCY OR THE REPEAT FREQUENCY COMMAND TO THE CONTROL REGISTER.
Y POLL STATUS REGISTER TO CHECK IF FREQUENCY SWEEP IS COMPLETE. Y PROGRAM THE AD5933 INTO POWER-DOWN MODE.
05324-034
Figure 28. Frequency Sweep Flow Chart
Data Sheet REGISTER MAP

Table 8.
Register 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8F 0x92 0x93 0x94 0x95 0x96 0x97 Name Control Start frequency Register Data D15 to D8 D7 to D0 D23 to D16 D15 to D8 D7 to D0 D23 to D16 D15 to D8 D7 to D0 D15 to D8 D7 to D0 D15 to D8 D7 to D0 D7 to D0 D15 to D8 D7 to D0 D15 to D8 D7 to D0 D15 to D8 D7 to D0 Function Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Read only Read only Read only Read only
AD5933
Frequency increment
Number of increments Number of settling time cycles Status Temperature data Real data Imaginary data
CONTROL REGISTER (REGISTER ADDRESS 0x80, REGISTER ADDRESS 0x81)

The AD5933 has a 16-bit control register (Register Address 0x80 and Register Address 0x81) that sets the AD5933 control modes. The default value of the control register upon reset is as follows: D15 to D0 reset to 0xA000 upon power-up. The four MSBs of the control register are decoded to provide control functions, such as performing a frequency sweep, powering down the part, and controlling various other functions defined in the control register map. The user may choose to write only to Register Address 0x80 and not to alter the contents of Register Address 0x81. Note that the control register should not be written to as part of a block write command. The control register also allows the user to program the excitation voltage and set the system clock. A reset command to the control register does not reset any programmed values associated with the sweep (that is, start frequency, number of increments, frequency increment). After a reset command, an initialize with start frequency command must be issued to the control register to restart the frequency sweep sequence (see Figure 28).
Table 9. Control Register Map (D15 to D12)

D15 0 0 0 0 0 1 1 1 1 1 1 D14 0 0 0 0 1 0 0 0 0 1 1 D13 0 0 1 1 0 0 0 1 1 0 0 D12 0 1 0 1 0 0 1 0 1 0 1 Function No operation Initialize with start frequency Start frequency sweep Increment frequency Repeat frequency No operation Measure temperature Power-down mode Standby mode No operation No operation
Table 10. Control Register Map (D10 to D9)

D10 0 0 1 1 D9 0 1 0 1 Range No. 1 4 3 2 Output Voltage Range 2.0 V p-p typical 200 mV p-p typical 400 mV p-p typical 1.0 V p-p typical
AD5933
Table 11. Control Register Map (D11, D8 to D0)
Bits D11 D8 D7 D6 D5 D4 D3 D2 D1 D0 Description No operation PGA gain; 0 = 5, 1 = 1 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 Reset External system clock; set to 1 Internal system clock; set to 0 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0
Data Sheet
Power-Down Mode
The default state on power-up of the AD5933 is power-down mode. The control register contains the code 1010,0000,0000,0000 (0xA000). In this mode, both the VOUT and VIN pins are connected internally to GND.
Standby Mode
This mode powers up the part for general operation; in standby mode the VIN and VOUT pins are internally connected to ground.
Output Voltage Range

The output voltage range allows the user to program the excitation voltage range at VOUT.
PGA Gain
The PGA gain allows the user to amplify the response signal into the ADC by a multiplication factor of 5 or 1.
Control Register Decode Initialize with Start Frequency

This command enables the DDS to output the programmed start frequency for an indefinite time. It is used to excite the unknown impedance initially. When the output unknown impedance has settled after a time determined by the user, the user must initiate a start frequency sweep command to begin the frequency sweep.
Reset
A reset command allows the user to interrupt a sweep. The start frequency, number of increments, and frequency increment register contents are not overwritten. An initialize with start frequency command is required to restart the frequency sweep command sequence.
Start Frequency Sweep

In this mode the ADC starts measuring after the programmed number of settling time cycles has elapsed. The user has the ability to program an integer number of output frequency cycles (settling time cycles) to Register Address 0x8A and Register Address 0x8B before the commencement of the measurement at each frequency point (see Figure 28).
START FREQUENCY REGISTER (REGISTER ADDRESS 0x82, REGISTER ADDRESS 0x83, REGISTER ADDRESS 0x84)
The default value of the start frequency register upon reset is as follows: D23 to D0 are not reset on power-up. After a reset command, the contents of this register are not reset. The start frequency register contains the 24-bit digital representation of the frequency from where the subsequent frequency sweep is initiated. For example, if the user requires the sweep to start from frequency 30 kHz (using a 16.0 MHz clock), then the user programs the value of 0x0F to Register Address 0x82, the value of 0x5C to Register Address 0x83, and the value of 0x28 to Register Address 0x84. This ensures the output frequency starts at 30 kHz. The code to be programmed to the start frequency register is
Increment Frequency
The increment frequency command is used to step to the next frequency point in the sweep. This usually happens after data from the previous step has been transferred and verified by the DSP. When the AD5933 receives this command, it waits for the programmed number of settling time cycles before beginning the ADC conversion process.
Repeat Frequency
The AD5933 has the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the control register. This has the benefit of allowing the user to average successive readings.
Measure Temperature
The measure temperature command initiates a temperature reading from the part. The part does not need to be in powerup mode to perform a temperature reading. The block powers itself up, takes the reading, and then powers down again. The temperature reading is stored in a 14-bit, twos complement format at Register Address 0x92 and Register Address 0x93.
30 kHz 27 Start Frequency Code = 2 0 x0F5C28 16 MHz 4
Data Sheet
FREQUENCY INCREMENT REGISTER (REGISTER ADDRESS 0x85, REGISTER ADDRESS 0x86, REGISTER ADDRESS 0x87)
The default value upon reset is as follows: D23 to D0 are not reset on power-up. After a reset command, the contents of this register are not reset. The frequency increment register contains a 24-bit representation of the frequency increment between consecutive frequency points along the sweep. For example, if the user requires an increment step of 10 Hz using a 16.0 MHz clock, the user should program the value of 0x00 to Register Address 0x85, the value of 0x01 to Register Address 0x86m, and the value of 0x4F to Register Address 0x87. The formula for calculating the increment frequency is given by
AD5933
This register determines the number of frequency points in the frequency sweep. The number of points is represented by a 9-bit word, D8 to D0. D15 to D9 are dont care bits. This register, in conjunction with the start frequency register and the increment frequency register, determines the frequency sweep range for the sweep operation. The maximum number of increments that can be programmed is 511.
NUMBER OF SETTLING TIME CYCLES REGISTER (REGISTER ADDRESS 0x8A, REGISTER ADDRESS 0x8B)
The default value upon reset is as follows: D10 to D0 are not reset on power-up. After a reset command, the contents of this register are not reset (see Table 13). This register determines the number of output excitation cycles that are allowed to pass through the unknown impedance, after receipt of a start frequency sweep, increment frequency, or repeat frequency command, before the ADC is triggered to perform a conversion of the response signal. The number of settling time cycles register value determines the delay between a start frequency sweep/increment frequency /repeat frequency command and the time an ADC conversion commences. The number of cycles is represented by a 9-bit word, D8 to D0. The value programmed into the number of settling time cycles register can be increased by a factor of 2 or 4 depending upon the status of bits D10 to D9. The five most significant bits, D15 to D11, are dont care bits. The maximum number of output cycles that can be programmed is 511 4 = 2044 cycles. For example, consider an excitation signal of 30 kHz. The maximum delay between the programming of this frequency and the time that this signal is first sampled by the ADC is 511 4 33.33 s = 68.126 ms. The ADC takes 1024 samples, and the result is stored as real data and imaginary data in Register Address 0x94 to Register Address 0x97. The conversion process takes approximately 1 ms using a 16.777 MHz clock.
10 Hz 27 Frequency Increment Code = 2 0 x00014 F 16 MHz 4

The user programs the value 0x00 to Register Address 0x85, the value 0x01 to Register Address 0x86, and the value 0x4F to Register Address 0x87.
NUMBER OF INCREMENTS REGISTER (REGISTER ADDRESS 0x88, REGISTER ADDRESS 0x89)

The default value upon reset is as follows: D8 to D0 are not reset on power-up. After a reset command, the contents of this register are not reset.
Table 12. Number of Increments Register
Reg 0x88 Bits D15 to D9 D8 0x89 D8 to D0 Description Dont care Number of increments Number of increments Function Read or write Read or write Read or write Format Integer number stored in binary format Integer number stored in binary format
Table 13. Number of Settling Times Cycles Register

Register 0x8A Bits D15 to D11 D10 to D9 Description Dont care 2-bit decode D10 D9 Description 0 0 Default 0 1 No. of cycles 2 1 0 Reserved 1 1 No. of cycles 4 MSB number of settling time cycles Number of settling time cycles Function Read or write Format Integer number stored in binary format
0x8B
D8 D7 to D0
Read or write
AD5933
STATUS REGISTER (REGISTER ADDRESS 0x8F)
The status register is used to confirm that particular measurement tests have been successfully completed. Each of the bits from D7 to D0 indicates the status of a specific functionality of the AD5933. Bit D0 and Bit D4 to Bit D7 are treated as dont care bits These bits do not indicate the status of any measurement. The status of Bit D1 indicates the status of a frequency point impedance measurement. This bit is set when the AD5933 has completed the current frequency point impedance measurement. This bit indicates that there is valid real data and imaginary data in Register Address 0x94 to Register Address 0x97. This bit is reset on receipt of a start frequency sweep, increment frequency, repeat frequency, or reset command. This bit is also reset on power-up. The status of Bit D2 indicates the status of the programmed frequency sweep. This bit is set when all programmed increments to the number of increments register are complete. This bit is reset on power-up and on receipt of a reset command.
Table 14. Status Register (Register Address 0x8F)
Control Word 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 Function Valid temperature measurement Valid real/imaginary data Frequency sweep complete Reserved Reserved Reserved Reserved Reserved
Data Sheet
Valid Real/Imaginary Data
D1 is set when data processing for the current frequency point is finished, indicating real/imaginary data available for reading. D1 is reset when a start frequency sweep/increment frequency/ repeat frequency DDS start/increment/repeat command is issued. D1 is reset to 0 when a reset command is issued to the control register.
Frequency Sweep Complete

D2 is set when data processing for the last frequency point in the sweep is complete. This bit is reset when a start frequency sweep command is issued to the control register. This bit is also reset when a reset command is issued to the control register.
TEMPERATURE DATA REGISTER (16 BITSREGISTER ADDRESS 0x92, REGISTER ADDRESS 0x93)
These registers contain a digital representation of the temperature of the AD5933. The values are stored in 16-bit, twos complement format. Bit D15 and Bit D14 are dont care bits. Bit 13 is the sign bit. To convert this number to an actual temperature, refer to the Temperature Conversion Formula section.
REAL AND IMAGINARY DATA REGISTERS (16 BITSREGISTER ADDRESS 0x94, REGISTER ADDRESS 0x95, REGISTER ADDRESS 0x96, REGISTER ADDRESS 0x97)
The default value upon reset is as follows: these registers are not reset on power-up or on receipt of a reset command. Note that the data in these registers is valid only if Bit D1 in the status register is set, indicating that the processing at the current frequency point is complete. These registers contain a digital representation of the real and imaginary components of the impedance measured for the current frequency point. The values are stored in 16-bit, twos complement format. To convert this number to an actual impedance value, the magnitude(Real2 + Imaginary2)must be multiplied by an admittance/code number (called a gain factor) to give the admittance, and the result inverted to give impedance. The gain factor varies for each ac excitation voltage/gain combination.
Valid Temperature Measurement

The valid temperature measurement control word is set when a valid temperature conversion is complete indicating that valid temperature data is available for reading at Register Address 0x92 and Register Address 0x93. It is reset when a temperature measurement takes place as a result of a measure temperature command having been issued to the control register (Register Address 0x80 and Register Address 0x81) by the user.
Data Sheet SERIAL BUS INTERFACE

Control of the AD5933 is carried out via the I2C-compliant serial interface protocol. The AD5933 is connected to this bus as a slave device under the control of a master device. The AD5933 has a 7-bit serial bus slave address. When the device is powered up, it has a default serial bus address, 0001101 (0x0D).
AD5933
Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit, which can be from the master or slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-tohigh transition when the clock is high may be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before performing a read operation, it is sometimes necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition.
GENERAL I2C TIMING

Figure 29 shows the timing diagram for general read and write operations using the I2C-compliant interface. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line (SDA), while the serial clock line (SCL) remains high. This indicates that a data stream follows. The slave responds to the start condition and shifts in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus an R/W bit that determines the direction of the data transferthat is, whether data is written to or read from the slave device (0 = write, 1 = read). The slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, then the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device.
SCL
SDA
R/W
D7
D6
D5
D4
D3
D2
D1
D0 ACKNOWLEDGE BY MASTER/SLAVE
05324-035
START CONDITION BY MASTER
SLAVE ADDRESS BYTE
ACKNOWLEDGE BY AD5933
REGISTER ADDRESS
Figure 29. Timing Diagram
AD5933
WRITING/READING TO THE AD5933
The interface specification defines several different protocols for different types of read and write operations. This section describes the protocols used in the AD5933. The figures in this section use the abbreviations shown in Table 15.
Table 15. I2C Abbreviation Table
Abbreviation S P R W A A Condition Start Stop Read Write Acknowledge No acknowledge write byte/command byte
S SLAVE ADDRESS W A REGISTER ADDRESS A
Data Sheet
REGISTER DATA A P
05324-036
Figure 30. Writing Register Data to Register Address
The write byte protocol is also used to set a pointer to an address (see Figure 31). This is used for a subsequent singlebyte read from the same address or block read or block write starting at that address. To set a register pointer, the following sequence is applied: 1. 2. 3. 4. 5. 6. 7. 8. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA. The master sends a pointer command code (see Table 16; a pointer command = 1011 0000). The slave asserts an acknowledge on SDA. The master sends a data byte (a register address to where the pointer is to point). The slave asserts an acknowledge on SDA. The master asserts a stop condition on SDA to end the transaction.
S SLAVE ADDRESS W A A A P
05324-037
User Command Codes

The command codes in Table 16 are used for reading/writing to the interface. They are further explained in this section, but are grouped here for easy reference.
Table 16. Command Codes
Command Code 1010 0000 Code Name Block write Block read Address pointer Code Description This command is used when writing multiple bytes to the RAM; see the Block Write section. This command is used when reading multiple bytes from RAM/memory; see the Block Read section. This command enables the user to set the address pointer to any location in the memory. The data contains the address of the register to which the pointer should be pointing reworded
POINTER COMMAND 1011 0000
REGISTER ADDRESS TO POINT TO
1010 0001
Figure 31. Setting Address Pointer to Register Address
BLOCK WRITE
In this operation, the master device writes a block of data to a slave device (see Figure 32). The start address for a block write must previously have been set. In the case of the AD5933 this is done by setting a pointer to set the register address. 1. 2. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts an acknowledge on SDA. 4. The master sends an 8-bit command code (1010 0000) that tells the slave device to expect a block write. 5. The slave asserts an acknowledge on SDA. 6. The master sends a data byte that tells the slave device the number of data bytes to be sent to it. 7. The slave asserts an acknowledge on SDA. 8. The master sends the data bytes. 9. The slave asserts an acknowledge on SDA after each data byte. 10. The master asserts a stop condition on SDA to end the transaction.
1011 0000
Write Byte/Command Byte

In this operation, the master device sends a byte of data to the slave device. The write byte can either be a data byte write to a register address or can be a command operation. To write data to a register, the command sequence is as follows (see Figure 30): 1. 2. 3. 4. 5. 6. 7. 8. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA. The master sends a register address. The slave asserts an acknowledge on SDA. The master sends a data byte. The slave asserts an acknowledge on SDA. The master asserts a stop condition on SDA to end the transaction.
S SLAVE ADDRESS W A BLOCK WRITE A NUMBER BYTES WRITE A
BYTE 0
BYTE 1
BYTE 2
Figure 32. Writing a Block Write
05324-038
Data Sheet
READ OPERATIONS
The AD5933 uses two I2C read protocols: receive byte and block read.
AD5933
Block Read
In this operation, the master device reads a block of data from a slave device (see Figure 34). The start address for a block read must previously have been set by setting the address pointer. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA. The master sends a command code (1010 0001) that tells the slave device to expect a block read. The slave asserts an acknowledge on SDA. The master sends a byte-count data byte that tells the slave how many data bytes to expect. The slave asserts an acknowledge on SDA. The master asserts a repeat start condition on SDA. This is required to set the read bit high. The master sends the 7-bit slave address followed by the read bit (high). The slave asserts an acknowledge on SDA. The master receives the data bytes. The master asserts an acknowledge on SDA after each data byte. A no acknowledge is generated after the last byte to signal the end of the read. The master asserts a stop condition on SDA to end the transaction.
R A BYTE 0 A BYTE 1 A BYTE 2 A P
05324-040
Receive Byte
In the AD5933, the receive byte protocol is used to read a single byte of data from a register address whose address has previously been set by setting the address pointer. In this operation, the master device receives a single byte from a slave device as follows (see Figure 33): 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts an acknowledge on SDA. The master receives a data byte. The master asserts a no acknowledge on SDA (the slave needs to check that master has received data). The master asserts a stop condition on SDA and the transaction ends.
S SLAVE ADDRESS R A REGISTER DATA A P
05324-039
Figure 33. Reading Register Data
SLAVE ADDRESS
BLOCK READ
NUMBER BYTES READ
SLAVE ADDRESS
Figure 34. Performing a Block Read
AD5933 TYPICAL APPLICATIONS

MEASURING SMALL IMPEDANCES
The AD5933 is capable of measuring impedance values up to 10 M if the system gain settings are chosen correctly for the impedance subrange of interest. If the user places a small impedance value (500 over the sweep frequency of interest) between the VOUT and VIN pins, it results in an increase in signal current flowing through the impedance for a fixed excitation voltage in accordance with Ohms law. The output stage of the transmit side amplifier available at the VOUT pin may not be able to provide the required increase in current through the impedance. To have a unity gain condition about the receive side I-V amplifier, the user needs to have a similar small value of feedback resistance for system calibration as outlined in the Gain Factor Setup Configuration section. The voltage presented at the VIN pin is hard biased at VDD/2 due to the virtual earth on the receive side I-V amplifier. The increased current sink/source requirement placed on the output of the receive side I-V amplifier may also cause the amplifier to operate outside of the linear region. This causes significant errors in subsequent impedance measurements. The value of the output series resistance, ROUT, (see Figure 35) at the VOUT pin must be taken into account when measuring small impedances (ZUNKNOWN), specifically when the value of the output series resistance is comparable to the value of the impedance under test (ZUNKNOWN). If the ROUT value is unaccounted for in the system calibration (that is, the gain factor calculation) when measuring small impedances, there is an introduced error into any subsequent impedance measurement that takes place. The introduced error depends on the relative magnitude of the impedance being tested compared to the value of the output series resistance.
TRANSMIT SIDE OUTPUT AMPLIFIER DDS 2V p-p R1 R2
Data Sheet
The value of the output series resistance depends upon the selected output excitation range at VOUT and has a tolerance from device to device like all discrete resistors manufactured in a silicon fabrication process. Typical values of the output series resistance are outlined in Table 17.
Table 17. Output Series Resistance (ROUT) vs. Excitation Range
Parameter Range 1 Range 2 Range 3 Range 4 Value (Typ) 2 V p-p 1 V p-p 0.4 V p-p 0.2 V p-p Output Series Resistance Value 200 typ 2.4 k typ 1.0 k typ 600 typ
Therefore, to accurately calibrate the AD5933 to measure small impedances, it is necessary to reduce the signal current by attenuating the excitation voltage sufficiently and also account for the ROUT value and factor it into the gain factor calculation (see the Gain Factor Calculation section). Measuring the ROUT value during device characterization is achieved by selecting the appropriate output excitation range at VOUT and sinking and sourcing a known current at the pin (for example, 2 mA) and measuring the change in dc voltage. The output series resistance can be calculated by measuring the inverse of the slope (that is, 1/slope) of the resultant I-V plot. A circuit that helps to minimize the effects of the issues previously outlined is shown in Figure 35. The aim of this circuit is to place the AD5933 system gain within its linear range when measuring small impedances by using an additional external amplifier circuit along the signal path. The external amplifier attenuates the peak-to-peak excitation voltage at VOUT by a suitable choice of resistors (R1 and R2), thereby reducing the signal current flowing through the impedance and minimizing the effect of the output series resistance in the impedance calculations. In the circuit shown in Figure 35, ZUNKNOWN recognizes the output series resistance of the external amplifier which is typically much less than 1 with feedback applied depending upon the op amp device used (for example, AD820, AD8641, AD8531) as well as the load current, bandwidth, and gain.
ROUT VOUT
VDD 20k RFB VDD/2 20k RFB PGA I-V VIN VDD/2 ZUNKNOWN 1F
AD8531 AD820 AD8641 AD8627
Figure 35. Additional External Amplifier Circuit for Measuring Small Impedances
05324-048
Data Sheet
The key point is that the output impedance of the external amplifier in Figure 35 (which is also in series with ZUNKNOWN) has a far less significant effect on gain factor calibration and subsequent impedance readings in comparison to connecting the small impedance directly to the VOUT pin (and directly in series with ROUT). The external amplifier buffers the unknown impedance from the effects of ROUT and introduces a smaller output impedance in series with ZUNKNOWN. For example, if the user measures ZUNKNOWN that is known to have a small impedance value within the range of 90 to 110 over the frequency range of 30 kHz to 32 kHz, the user may not be in a position to measure ROUT directly in the factory/lab. Therefore, the user may choose to add on an extra amplifier circuit like that shown in Figure 35 to the signal path of the AD5933. The user must ensure that the chosen external amplifier has a sufficiently low output series resistance over the bandwidth of interest in comparison to the impedance range under test (for an op amp selection guide, see www.analog.com/opamps). Most amplifiers from Analog Devices have a curve of closed loop output impedance vs. frequency at different amplifier gains to determine the output series impedance at the frequency of interest. The system settings are VDD = 3.3 V VOUT = 2 V p-p R2 = 20 k R1 = 4 k Gain setting resistor = 500 ZUNKNOWN = 100 PGA setting = 1
AD5933
To attenuate the excitation voltage at VOUT, choose a ratio of R1/R2. With the values of R1 = 4 k and R2 = 20 k, attenuate the signal by 1/5th of 2 V p-p = 400 mV. The maximum current flowing through the impedance is 400 mV/ 90 = 4.4 mA. The system is subsequently calibrated using the usual method with a midpoint impedance value of 100 , a calibration resistor, and a feedback resistor at a midfrequency point in the sweep. The dynamic range of the input signal to the receive side of the AD5933 can be improved by increasing the value of the I-V gain resistor at the RFB pin. For example, increasing the I-V gain setting resistor at the RFB pin increases the peak-to-peak signal presented to the ADC input from 400 mV (RFB = 100 ) to 2 V p-p (RFB = 500 ). The gain factor calculated is for a 100 resistor connected between VOUT and VIN, assuming the output series resistance of the external amplifier is small enough to be ignored. When biasing the circuit shown in Figure 35, note that the receive side of the AD5933 is hard-biased about VDD/2 by design. Therefore, to prevent the output of the external amplifier (attenuated AD5933 Range 1 excitation signal) from saturating the receive side amplifiers of the AD5933, a voltage equal to VDD/2 must be applied to the noninverting terminal of the external amplifier.
AD5933
BIOMEDICAL: NONINVASIVE BLOOD IMPEDANCE MEASUREMENT
When a known strain of a virus is added to a blood sample that already contains a virus, a chemical reaction takes place whereby the impedance of the blood under certain conditions changes. By characterizing this effect across different frequencies, it is possible to detect a specific strain of virus. For example, a strain of the disease exhibits a certain characteristic impedance at one frequency but not at another; therefore, the requirement is to sweep different frequencies to check for different viruses. The AD5933, with its 27-bit phase accumulator, allows for subhertz frequency tuning. The AD5933 can be used to inject a stimulus signal through the blood sample via a probe. The response signal is analyzed, and the effective impedance of the blood is tabulated. The AD5933 is ideal for this application because it allows the user to tune to the specific frequency required for each test.
1 2 16 15
Data Sheet
SENSOR/COMPLEX IMPEDANCE MEASUREMENT
The operational principle of a capacitive proximity sensor is based on the change of a capacitance in an RLC resonant circuit. This leads to changes in the resonant frequency of the RLC circuit, which can be evaluated as shown Figure 37. It is first required to tune the RLC circuit to the area of resonance. At the resonant frequency, the impedance of the RLC circuit is at a maximum. Therefore, a programmable frequency sweep and tuning capability is required, which is provided by the AD5933.
RESONANT FREQUENCY CHANGE IN RESONANCE DUE TO APPROACHING OBJECT
ADuC702x
TOP VIEW (Not to Scale)
AD5933
3
4 5 6 7
13 12 11 10 9
FREQUENCY (Hz)
Figure 37. Detecting a Change in Resonant Frequency
PROBE
8
7V
2
ADR43x
4
6
05324-041
An example of the use of this type of sensor is for a train proximity measurement system. The magnetic fields of the train approaching on the track change the resonant frequency to an extent that can be characterized. This information can be sent back to a mainframe system to show the train location on the network. Another application for the AD5933 is in parked vehicle detection. The AD5933 is placed in an embedded unit connected to a coil of wire underneath the parking location. The AD5933 outputs a single frequency within the 80 kHz to 100 kHz frequency range, depending upon the wire composition. The wire can be modeled as a resonant circuit. The coil is calibrated with a known impedance value and at a known frequency. The impedance of the loop is monitored constantly. If a car is parked over the coil, the impedance of the coil changes and the AD5933 detects the presence of the car.
0.1F
10F
Figure 36. Measuring a Blood Sample for a Strain of Virus
05324-042
RFB
TOP VIEW 14 (Not to Scale)
PROXIMITY IMPEDANCE ()
FO
Data Sheet
ELECTRO-IMPEDANCE SPECTROSCOPY
The AD5933 has found use in the area of corrosion monitoring. Corrosion of metals, such as aluminum and steel, can damage industrial infrastructures and vehicles such as aircraft, ships, and cars. This damage, if left unattended, may lead to premature failure requiring expensive repairs and/or replacement. In many cases, if the onset of corrosion can be detected, it can be arrested or slowed, negating the requirement for repairs or replacement. At present, visual inspection is employed to detect corrosion; however, this is time consuming, expensive, and cannot be employed in hard-to-access areas. An alternative to visual inspection is automated monitoring using corrosion sensors. Monitoring is cheaper, less time consuming, and can be deployed where visual inspections are impossible. Electrochemical impedance spectroscopy (EIS) has been used to interrogate corrosion sensors, but at present large laboratory test instruments are required. The AD5933 offers an accurate and compact solution for this type of measurement, enabling the development of field deployable sensor systems that can measure corrosion rates autonomously. Mathematically, the corrosion of aluminum is modeled using an RC network that typically consists of a resistance, RS, in series with a parallel resistor and capacitor, RP and CP. A system metal would typically have values as follows: RS is 10 to 10 k, RP 1 is k to 1 M, and CP is 5 F to 70 F. Figure 38 shows a typical Bode plot, impedance modulus, and phase angle vs. frequency, for an aluminum corrosion sensor.
100k
AD5933
75
10k PHASE ANGLE

05324-043
50 MODULUS
1k
25 100
10 0.1
10
100 FREQUENCY (Hz)
1k
10k
0 100k
Figure 38. Bode Plot for Aluminum Corrosion Sensor
To make accurate measurements of these values, the impedance needs to be measured over a frequency range of 0.1 Hz to 100 kHz. To ensure that the measurement itself does not introduce a corrosive effect, the metal needs to be excited with minimal voltage, typically in the 20 mV range. A nearby processor or control unit such as the ADuC702x would log a single impedance sweep from 0.1 kHz to 100 kHz every 10 minutes and download the results back to a control unit. To achieve system accuracy from the 0.1 kHz to 1 kHz range, the system clock needs to be scaled down from the 16.776 MHz nominal clock frequency to 500 kHz, typically. The clock scaling can be achieved digitally using an external direct digital synthesizer like the AD9834 as a programmable divider, which supplies a clock signal to MCLK and which can be controlled digitally by the nearby microprocessor.
AD5933 CHOOSING A REFERENCE FOR THE AD5933

To achieve the best performance from the AD5933, carefully choose the precision voltage reference. The AD5933 has three reference inputs: AVDD1, AVDD2, and DVDD. It is recommended that the voltage on these reference inputs be run from the same voltage supply. There are four sources of error that should be considered when choosing a voltage reference for high accuracy applications: initial accuracy, ppm drift, long-term drift, and output voltage noise. To minimize these errors, a reference with high initial accuracy is preferred. Also, choosing a reference with an output trim adjustment, such as a device in the ADR43x family, allows a system designer to trim system errors by setting a reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Because the supply current required by the AD5933 is extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended in this case.
Data Sheet
The ADR395 requires less than 100 A of quiescent current. It also provides very good noise performance at 8 V p-p in the 0.1 Hz to 10 Hz range. Long-term drift is a measure of how much the reference drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains stable during its entire lifetime. A reference with a tight temperature coefficient specification should be chosen to reduce the temperature dependence of the system output voltage on ambient conditions. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. Choosing a reference with as low an output noise voltage as practical for the system noise resolution required is important. Precision voltage references such as the ADR433 produce low output noise in the 0.1 Hz to 10 Hz range. Examples of some recommended precision references for use as supplies to the AD5933 are shown in Table 18.
Table 18. List of Precision References for the AD5933

Part No. ADR433B ADR433A ADR434B ADR434A ADR435B ADR435A ADR439B ADR439A Initial Accuracy (mV max) 1.5 4 1.5 5 2 6 2 5.5 Output Voltage (V) 3. 0 3. 0 4. 096 4. 096 5.0 5.0 4.5 4.5 Temp. Drift (ppm/C Max) 3 10 3 10 3 10 3 10 0.1 Hz to 10 Hz Noise (V p-p Typ) 3.75 3.75 6.25 6.25 8 8 7.5 7.5
Data Sheet LAYOUT AND CONFIGURATION

POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5933 should have separate analog and digital sections, each having its own area of the board. If the AD5933 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5933. The power supply to the AD5933 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be physically as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor have low effective series resistance (ESR) and effective series inductance (ESI); common ceramic types of capacitors are suitable. The 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching.
AD5933
The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only, and the signal traces are placed on the solder side. However, this is not always possible with a two-layer board.
AD5933 EVALUATION BOARD

The AD5933 evaluation board allows designers to evaluate the high performance AD5933 impedance converter with minimum effort. The evaluation board interfaces to the USB port of a PC. It is possible to power the entire board from the USB port. The impedance converter evaluation kit includes a populated and tested AD5933 printed circuit board. The EVAL-AD5933EB kit is shipped with a CD-ROM that includes self-installing software. Connect the PC to the evaluation board using the supplied cable. The software is compatible with Microsoft Windows 2000 and Windows XP and Windows 7. A schematic of the evaluation board is shown in Figure 39 and Figure 40.
Data Sheet
USING THE EVALUATION BOARD
The AD5933 evaluation board is a test system designed to simplify the evaluation of the AD5933. The evaluation board data sheet is also available with the evaluation board that gives full information on operating the evaluation board. Further evaluation information is available from www.analog.com.
PROTOTYPING AREA
An area is available on the evaluation board for the user to add additional circuits to the evaluation test set. Users may want to include switches for multiple calibration use.
CRYSTAL OSCILLATOR (XO) vs. EXTERNAL CLOCK

A 16 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and, if required, an external CMOS clock can be connected to the part.
Data Sheet
SCHEMATICS
05324-044
AD5933
Figure 39. EVAL-AD5933EBZ USB Schematic
AD5933
05324-045
Data Sheet
Figure 40. EVAL-AD5933EBZ Schematic
Data Sheet
05324-046
AD5933
Figure 41. Linear Regulator on the EVAL-AD5933EB Evaluation Board
AD5933
Data Sheet
05324-047
Figure 42. Decoupling on the EVAL-AD5933EB Evaluation Board
Data Sheet OUTLINE DIMENSIONS

6.50 6.20 5.90
AD5933
16
5.60 5.30 5.00

1 8
8.20 7.80 7.40
2.00 MAX
1.85 1.75 1.65 0.38 0.22 SEATING PLANE 8 4 0
0.25 0.09
0.05 MIN COPLANARITY 0.10 0.65 BSC
0.95 0.75 0.55

060106-A
COMPLIANT TO JEDEC STANDARDS MO-150-AC
Figure 43. 16-Lead Shrink Small Outline Package [SSOP] (RS-16) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD5933YRSZ AD5933YRSZ-REEL7 EVAL-AD5933EBZ
1
Temperature Range 40C to +125C 40C to +125C 40C to +125C
Package Description 16-Lead Shrink Small Outline Package (SSOP) 16-Lead Shrink Small Outline Package (SSOP) Evaluation Board
Package Option RS-16 RS-16
Z = RoHS Compliant Part.
AD5933 NOTES
Data Sheet
Data Sheet NOTES
AD5933
AD5933 NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
20052011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05324-0-12/11(D)

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Data Sheet

1 MSPS, 12-Bit Impedance Converter, Network Analyzer AD5933

FUNCTIONAL BLOCK DIAGRAM

DDS CORE (27 BITS)

DAC ROUT VOUT

1024-POINT DFT VIN ADC (12 BITS) GAIN LPF

VDD/2 AGND DGND

AD5933 TABLE OF CONTENTS

Total System Accuracy

30 1 0.1 16.776 16.776 30 100

ppm/C kHz Hz MHz MHz ppm/C

V p-p V mA V p-p V k mA V p-p V k mA V p-p V mA dB dB dB dB

See Figure 8 DC bias of output excitation signal; see Figure 9

See Figure 10 DC bias of output excitation signal. See Figure 11

12 250 2.0 0.03 800

0.7 VDD 0.3 VDD 1 7 2.7 10 17 11 5.5 15 25 A pF V mA mA mA TA = 25C TA = 25C

IDD (Power-Down Mode)

Figure 2. I2C Interface Timing Diagram

Data Sheet ABSOLUTE MAXIMUM RATINGS

AD5933 PIN CONFIGURATION AND DESCRIPTIONS

SCL SDA AGND2 AGND1 DGND AVDD2 AVDD1 DVDD

TOP VIEW (Not to Scale)

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Range 1 Output Excitation Voltage Distribution, VDD = 3.3 V

Figure 7. Range 2 DC Bias Distribution, VDD = 3.3 V

MEAN = 0.3827 SIGMA = 0.00167

0.385 VOLTAGE (V)

Figure 5. Range 1 DC Bias Distribution, VDD = 3.3 V

Figure 8. Range 3 Output Excitation Voltage Distribution, VDD = 3.3 V

0.305 VOLTAGE (V)

Figure 6. Range 2 Output Excitation Voltage Distribution, VDD = 3.3 V

Figure 9. Range 3 DC Bias Distribution, VDD = 3.3 V

13.8 13.3 12.8 12.3 11.8 11.3

MCLK FREQUENCY (MHz)

Figure 10. Range 4 Output Excitation Voltage Distribution, VDD = 3.3 V

Figure 12. Typical Supply Current vs. MCLK Frequency

VDD = 3.3V TA = 25C f = 32kHz

Figure 11. Range 4 DC Bias Distribution, VDD = 3.3 V

Figure 13. Typical Phase Error

OSCILLATOR FREQUENCY (MHz)

Figure 14. Frequency Distribution of Internal Oscillator at 40C

Figure 16. Frequency Distribution of Internal Oscillator at 125C

N = 100 MEAN = 16.7811 SD = 0.0881565 TEMP = 25C

OSCILLATOR FREQUENCY (MHz)

Figure 15. Frequency Distribution of Internal Oscillator at 25C

THD (dB) = 20 log

Data Sheet SYSTEM DESCRIPTION

MAC CORE (1024 DFT) WINDOWING OF DATA MCLK

Figure 17. Block Overview

5.0 = 2.24 V p p 3.3

Table 5. Voltage Levels Respective Bias Levels for 3.3 V

Figure 18. Impedance vs. Frequency Profile

DAC VOUT VBIAS

Figure 19. Transmit Stage

Figure 20. Receive Stage

TEMPERATURE CONVERSION FORMULA

TEMPERATURE CONVERSION DETAILS

00, 1001, 0110, 0000