Finite State Machine Design

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Chapter #8: Finite State Machine Design

Contemporary Logic Design
Transparency No. 8-1
Motivation
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Finite State Machines:

Outputs are Function of State (and Inputs)
Next States are Functions of State and Inputs
Used to implement circuits that control other circuits
"Decision Making" logic
Application of Sequential Logic Design Techniques
Word Problems
Mapping into formal representations of FSM behavior
Case Studies
Chapter Overview
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Memory Element
Basic Design Approach
Six Step Design Process
State Machine Representation

State Diagram
Moore and Mealy Machines
Definitions, Implementation Examples
Word Problems
Case Studies
Memory Elements
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Sequential Networks
Simple Circuits with Feedback
R-S Latch
J-K Flipflop
Edge-Triggered Flipflops
Realizing Circuits with Flipflops
Choosing a FF Type
Characteristic Equations
Sequential Switching Networks
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7474
D
Clk
Positiv e edge-triggered
f lip-f lop
Edge triggered device sample inputs on the event

edge
Transparent latches sample inputs as long as the
clock is asserted
Timing Diagram:
7476
D
C
Clk
Lev el-s ens itiv e
latch
Bubble here
for negative
edge triggered
device
Clk
Q
Q
7474
7476
Behavior the same unless input changes

while the clock is high
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Six Step Process
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state minimization
4. Perform state assignment
5. Choose FF types to implement FSM state register

6. Implement the FSM
1, 2 covered now; 3, 4, 5 covered later;

4, 5 generalized from the counter design procedure
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Example: Vending Machine FSM
General Machine Concept:

deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram
N
Coin
Sensor D
Res et
Vending
Machine
FSM
Open
Gum
Release
Mechanism
Clk
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Vending Machine Example
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:

three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Re set
S0
N
Draw state diagram:

S1
Inputs: N, D, reset
Output: open
S2
S4
S5
S6
[ope n]
[ope n]
[ope n]
S3
S7
S8
[ope n]
[ope n]
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Step 3: State Minimization

Pres ent
State
Reset
0
0
N
5
D
5
N
10
D
N, D
10
15
[open]
15
reuse states
whenever
possible
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Next
State
Output
Open
0
5
10
X
5
10
15
X
10
15
15
X
15
0
0
0
X
0
0
0
X
0
0
0
X
1
Symbolic State Table
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Step 4: State Encoding
Pres ent State Inputs
Q1 Q0
D N
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
Output
Open
0
0
0
1
1
0
X X
0
1
1
0
1
1
X X
1
0
1
1
1
1
X X
1
1
1
1
1
1
X
X
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
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Parity Checker Example
Step 5. Choose FFs for implementation

D FF easiest to use
Q1
D
Q0
N
D1 D
CLK
R
Q1
\ Q1
D1 = Q1 + D + Q0 N
\reset
N
\ Q0
Q0
\N
Q1
N
Q1
D
OPEN
D0 D
CLK
Q
R
\reset
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
Q0
Q \ Q0
8 Gates
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Parity Checker Example

Step 5. Choosing FF for Implementation
J-K FF
Pres ent State Inputs
Q1 Q0
D N
0
0
0
0
0
1
1
0
1
1
0
1
0
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
Next State J1
D 1 D0
0
0
1
X
0
1
1
X
1
1
1
X
1
1
1
X
0
1
0
X
1
0
1
X
0
1
1
X
1
1
1
X
0
0
1
X
0
1
1
X
X
X
X
X
X
X
X
X
K1
J0 K 0
X
X
X
X
X
X
X
X
0
0
0
X
0
0
0
X
0
1
0
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
X
X
X
0
0
0
X
Remapped encoded state transition table

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Implementation:
J1 = D + Q0 N
K1 = 0
J0 = Q0 N + Q1 D
K0 = Q1 N
N
Q0
D
\ Q0
J
CLK
K RQ
Q1
\ Q1
N
OPEN
Q1
D
CLK
\ Q1
KR Q
Q0
\ Q0
\reset
7 Gates
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Moore and Mealy Machine Design Procedure

Definitions
Mealy Machine
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs a nd
Ne xt State
State Regis te r
Clock
Outputs depend on
state AND inputs
Input change causes
an immediate output
change
State
Fe edback
Asynchronous signals
State
Re giste r
Xi
Inputs
Moore Machine
Comb.
Logic for
Outputs
Combinational
Logic for
Ne xt State
(Flip-flop
Inputs )
Zk
Outputs
Cloc k
Outputs are function

solely of the current
state
Outputs change
synchronously with
state changes
state
feedbac k
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State Diagram Equivalents
Moore
Machine
N D + Reset
(N D + Reset)/0
Reset/0
Reset
0
Mealy
Machine
[0]
Reset/0
Reset
N/0
5
N D/0
D/0
ND
D
[0]
N
N/0
10
10
D
D/1
N D/0
N+ D/1
[0]
N+ D
ND
15
15
Reset/1
Outputs are associated

with State
[1]
Reset
Outputs are associated

with Transitions
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States vs. Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
0/0
0
[0]
Same I/O behavior
Different # of states
1/0
0/0
1
1/1
[0]
1
2
[1]
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Finite State Machine Word Problems
Mapping English Language Description to Formal Specifications

Four Case Studies:
Finite String Pattern Recognizer

Complex Counter with Decision Making
Traffic Light Controller
Digital Combination Lock
We will use state diagrams and ASM Charts
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Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence 010
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010
Z: 00010101000
X: 11011010010
Z: 00000001000
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Finite String Recognizer

Step 2. Draw State Diagrams for the strings that must be
recognized. I.e., 010 and 100.
Moore State Diagram

Reset signal places
FSM in S0
Outputs 1
Loops in State

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Exit conditions from state S3: have recognized 010

if next input is 0 then have 0100!
if next input is 1 then have 0101 = 01 (state S2)

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Exit conditions from S1: recognizes strings of form 0 (no 1 seen)

loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form 1 (no 0 seen)
loop back to S4 if input is 1

S2, S5 with incomplete transitions
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S2 = 01; If next input is 1, then string could be prefix of (01)1(00)

S4 handles just this case!
S5 = 10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
Final State Diagram

Review of Process:
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Write down sample inputs and outputs to understand specification
Write down sequences of states and transitions for the sequences

to be recognized
Add missing transitions; reuse states as much as possible
Verify I/O behavior of your state diagram to insure it functions
like the specification
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Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter

counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M
0
0
1
1
1
0
0
Current State
000
001
010
110
111
101
110
Next State (Z2 Z1 Z0)

001
010
110
111
101
110
111

Complex Counter
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One state for each output combination

Add appropriate arcs for the mode control

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A busy highway is intersected by a little used farmroad. Detectors

C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.

Picture of Highway/Farmroad Intersection:
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Fa rmroad
C
HL
FL
Highw ay
Highw ay
HL
FL
C
Fa rmroad

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Tabulation of Inputs and Outputs:

Input Signal
reset
C
TS
TL
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
Tabulation of Unique States: Some light configuration imply others

State
S0
S1
S2
S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)
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Compare with state diagram:
TL + C
Res et
S0: HG
S0
TLC/ST
S1: HY
TS /ST
TS
S1
S2: FG
S3
TS
TS /ST
S3: FY
TL + C/ST
S2
TL C
Advantages of State Charts:
Concentrates on paths and conditions for exiting a state

Exit conditions built up incrementally, later combined into
single Boolean condition for exit
Easier to understand the design as an algorithm
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"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."
Problem specification is incomplete:
how do you set the internal combination?
exactly when is the ERROR light asserted?

Make reasonable assumptions:
hardwired into next state logic vs. stored in internal register
assert as soon as error is detected vs. wait until full combination

has been entered
Our design: registered combination plus error after full combination
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Understanding the problem: draw a block diagram

RESET
Operator Data
ENTER
UNLOCK
KEY-IN
Combination
Lock F SM ERR OR
Internal
Combination
Inputs:
Reset
Enter
Key-In
L0, L1, L2
L0
L1
L2
Outputs:
Unlock
Error

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Re set + E nter
Re set
Start
Re set Enter
Comp0
KI = L0
KI L0
Ente r
Ente r
Idle0
Idle0'
Ente r
Ente r
Comp1
Equivalent State Diagram
KI = L1
Error1
KI L1
Ente r
Ente r
Idle1
Idle1'
Ente r
Ente r
Comp2
KI = L2
Re set
Done
[Unloc k]
Re set
Start
Error2
KI L2
Error3
[Error]
Re set
Re set
Start

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CSCI 3301

Chapter #8: Finite State Machine Design

Transparency No. 8-1

Finite State Machines:

Transparency No. 8-2

State Machine Representation

Transparency No. 8-3

Transparency No. 6-4

Sequential Switching Networks

Edge triggered device sample inputs on the event

Behavior the same unless input changes

Basic Design Approach

5. Choose FF types to implement FSM state register

1, 2 covered now; 3, 4, 5 covered later;

Transparency No. 8-6

Basic Design Approach

General Machine Concept:

Transparency No. 8-7

Vending Machine Example

Step 2. Map into more suitable abstract representation

Tabulate typical input sequences:

Draw state diagram:

Transparency No. 8-8

Vending Machine Example

Step 3: State Minimization

Symbolic State Table

Transparency No. 8-9

Vending Machine Example

Transparency No. 8-10

Parity Checker Example

Step 5. Choose FFs for implementation

Parity Checker Example

Remapped encoded state transition table

Vending Machine Example

Transparency No. 8-13

Moore and Mealy Machine Design Procedure

Outputs are function

Transparency No. 8-14

Moore and Mealy Machines

Outputs are associated

Outputs are associated

Transparency No. 8-15

Moore and Mealy Machines

Same I/O behavior

Transparency No. 8-16

Finite State Machine Word Problems

Mapping English Language Description to Formal Specifications

Finite String Pattern Recognizer

Transparency No. 8-17

Finite State Machine Word Problems

Transparency No. 8-18

Finite State Machine Word Problems

Finite String Recognizer

Moore State Diagram

Transparency No. 8-19

Finite State Machine Word Problems

Exit conditions from state S3: have recognized 010

Transparency No. 8-20

Finite State Machine Word Problems

Exit conditions from S1: recognizes strings of form 0 (no 1 seen)