Virtual Memory
Virtual Memory
Virtual Memory
• 2 options
1) Store entire page table for process in registers
- No memory reference to access page table
- But, context switch between processes would be
expensive – why?
1) Store page table in memory and one register points
to start of page table for running process
- On context switch, load only 1 register value
- But, need one or more memory reference per instruction –
why?
• Neither methods rarely used. Instead, use hybrid
methods.
Managing Page Tables
• 2 types of TLBs
1) Those whose entries include an address space ID
field
– Address space ID associates TLB entry with process
– No need to invalidate entries on context switch
2) Those whose entries do not include address
space ID
– TLB must be flushed on context switch
– When process is loaded, TLB is loaded from page table in
memory
Inverted Page Table
• Inverted page table has as many entries as physical
page frames – will max size be smaller than that of
page table?
• One single global inverted page table, rather than one
page table per process
• Each entry contains process ID and virtual page
number
• Given virtual address, must search in inverted page
table – cannot use virtual address as index as with
standard page table
• Solutions:
– Maintain inverted page table in associative memory hardware
whose entries are search in parallel
– Use hash table to hash the virtual page address – how?
Two Different Architectures
• Typical page table architecture
– Information is kept in combination of page tables and map of
allocated virtual address space region to backing store –
backing store is swap space on disk where pages are
swapped in & out
– TLB is a cache
– PTE present/absent bit must be reset when page is replaced
(page frame field is considered garbage)