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State Encoding: One-Hot Encoding Output Encoding

This document discusses state encoding techniques for finite state machines (FSMs). It introduces concepts like one-hot encoding, output encoding, and state partitioning. For one-hot encoding, each state is represented by a unique bit pattern with one high bit, allowing direct translation from a state diagram. Output encoding reuses outputs as state bits. State partitioning breaks a large FSM into smaller FSMs to simplify design. Idle states are introduced for handoffs between partitions. The document provides an example to illustrate partitioning an FSM into two state machines.

Uploaded by

Rajesh Bathija
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
120 views

State Encoding: One-Hot Encoding Output Encoding

This document discusses state encoding techniques for finite state machines (FSMs). It introduces concepts like one-hot encoding, output encoding, and state partitioning. For one-hot encoding, each state is represented by a unique bit pattern with one high bit, allowing direct translation from a state diagram. Output encoding reuses outputs as state bits. State partitioning breaks a large FSM into smaller FSMs to simplify design. Idle states are introduced for handoffs between partitions. The document provides an example to illustrate partitioning an FSM into two state machines.

Uploaded by

Rajesh Bathija
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 24

Lecture 22

State encoding

One-hot encoding
Output encoding

State partitioning

FSM design

FSM design procedure


1.
2.
3.
4.
5.
6.

State diagram
State-transition table
State minimization
State encoding
Next-state logic minimization
Implement the design
2

Usual example

15 cents for a cup of coffee


Doesnt take pennies or quarters
Doesnt provide any change
Reset

N
Coin
Sensor

Vending
Machine
FSM

Clock

Open

Release
Mechanism

After state minimization


Reset

present
state
0

D' N'
0
D' N'

N
5

5
D

N
D

10

10
D' N'
15

N+D
15
[open]

inputs
D
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1

next
N
0
5
10

5
10
15

10
15
15

15

output
state
0
0
0

0
0
0

0
0
0

open

symbolic state table

How many state encodings?

Assume n state bits and m states

2n! / (2n m)! possible encodings

Example: 3 state bits, 4 states, 1680 possible state


assignments

Which encoding is best?

Want to pick state encoding strategy that results


in optimizing your criteria

FSM size (amount of logic and number of FFs)


FSM speed (depth of logic and fan-in/fan-out)
FSM ease of design or debugging
5

State encoding strategies

No guarantee of optimality

An intractable problem

Most common strategies

Binary (sequential) number states as in the state table


Random computer tries random encodings
Heuristic rules of thumb that seem to work well

e.g. Gray-code try to give adjacent states (states with an


arc between them) codes that differ in only one bit position

One-hot use as many state bits as there are states


Output use outputs to help encode states
Hybrid mix of a few different ones (e.g. One-hot +
heuristic)
6

One-hot encoding

One-hot: Encode n states using n flipflops

Assign a single 1 for each state

Example: 0001, 0010, 0100, 1000

Propagate a single 1 from one flip-flop


to the next

All other flip-flop outputs are 0

One-hot variants

The inverse: One-cold encoding

Assign a single 0 for each state

Example: 1110, 1101, 1011, 0111

Propagate a single 0 from one flip-flop


to the next

All other flip-flop outputs are 1

One-hot variants

almost one-hot encoding (modified


one-hot encoding)

Use no-hot (0000) for the initial (reset


state)
Assumes you never revisit the reset state
till reset again

One-hot encoding

Often the best/convenient approach for


FPGAs

FPGAs have many flip-flops

Draw FSM directly from the state diagram

+ One product term per incoming arc


- Complex state diagram complex design
- Many states many flip flops
10

Vending machine
present state inputs next state output
Q3Q2Q1Q0 D N D3 D2D1D0 open
00 0 1

00 1 0

01 0 0

10 0 0

0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1

0
0
0

0
0
1

0
1
1

0
0
1

0
1
0

1
0
0

0
1
0

1
0
0

0
0
0

1
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

Reset
D' N'
0
D' N'

N
5

N
D

10

D' N'

N+D
15
[open]

11

Designing from state diagram


Reset

D0 = Q0DN

D' N'

D1 = Q0N + Q1DN

0
D' N'

D2 = Q0D + Q1N + Q2DN

N
5

D3 = Q1D + Q2D + Q2N + Q3

OPEN = Q3

N
D

10

D' N'

N+D
15
[open]

12

Output encoding

Reuse outputs as state bits

Why create new functions when you can


use outputs?
Bits from state assignments are the
outputs for that state

Take outputs directly from the flip-flops

Yields small circuits for most FSMs


13

Output encoding

Inputs

Combinational
Logic

State Inputs

Outputs
State Outputs

Storage Elements

14

FSM partitioning

Break a large FSM into two or more


smaller FSMs

Less states in each partition

Simpler minimization and state assignment


Smaller combinational logic
Shorter critical path

But more logic overall

15

Example

Partition into two halves


C1
S1

C2
S2

S3

C4

C3

S6

S5
C5

S4

16

Introduce idle states

SA and SB handoff control between machines


C1

S1

C2
S2 C3

S3
S1

S5
C5

S4

C1
C2S6

S2
S3

C4

S6

C4

C3+C5

C1S1

(C2S6)

SA

S6

(C1S1+
C3S2+
C4S3+
C5S2)

C2

SB

C3S2+ S5
C4S3

C5S2

S4
17

Partitioning rules
Rule #1: Source-state transformation
Replace by transition to idle state (SA)
S1

C1

S6

S1

C1

SA

Rule #2: Destination state transformation


Replace with exit transition from idle state
S1

C2

S6

S1

C2S6

SA

18

Partitioning rules

Rule #3: Multiple transitions with same source or destination


Source Replace by transitions to idle state (SA)
Destination Replace with exit transitions from idle state
C3
S2

C3S2 +
C4S3

S2 C3+C5

S5

SA
S3

C4

C5

S4

S3

C4

S5

SB
C5S2

S4

Rule #4: Hold condition for idle state


OR exit conditions and invert
C2S6
S1

C2S6

SA
19

Example

U
U

S0

S5
D

S1

S4
D

D
D

S2

S3

20

Example
Count sequence S0, S1, S2, S3, S4, S5

S2 goes to SA and holds, leaves after S5

S5 goes to SB and holds, leaves after S2

Down sequence is similar


S5

S0
US5

U
D

S1

D
U

SA

DS3

S2

U
(DS3 +
US5)

(DS0+
US2)

SB

U
DS0
D

US2

S3

S4

D
U
21

Example
U

Compare behavior
on UUUUUU:

S0

S5
D

S1

S4
D

D
D

S2

S3

S5

S0
US5

U
D

S1

D
U

SA

DS3

S2

U
(DS3 +
US5)

(DS0+
US2)

SB

U
DS0
D

US2

S3

S4

D
U
22

Example

4-state machines need 2 state bits each


total 4 state bits

Enough to represent 16 states, though the


combination of the two FSMs has only 6 different
configurations

Why do this?

Each FSM may be much simpler to think about


(and design logic for) than the original FSM (not
here, though)
Essential to do this partitioning for large FSMs
23

Minimize communication

Ideal world: Two machines handoff


control

Separate I/O, states, etc.

Real world: Minimize handoffs and


common I/O

Minimize number of state bits that cross


boundary
24

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