Chapter 4

Instruction Sets
Part I: Instruction Formats & Instruction
Types

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 In this lecture:

Introduction
Instruction Format
Instruction Types

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 Introduction

Instructions
Specify operations to be performed by a computer
Words of a computers language

Instruction set
Collection of the instructions of a computer
Vocabulary of a computers language

Elements of an instruction

Operation Code Addresses

(Opcode) (operands)

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 Introductioncntd

Operation code (opcode)

Specifies the operation to be performed

Addresses (operands)
Provide more information about the operation
May include:
Source operands: specify where operands come from
Destination operands: specify where results go
Next instruction reference: specifies where to fetch next instruction from

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 Introductioncntd

Instructions to be read by a computer contain strings of 1s and

0s (They are numbers) (Machine instructions)
Symbolic representations of machine instructions are used for
convenience (assembly language)
Even more convenient (High-level languages)

void main()
{ Compiler Assembler
main: 0567
int a,b,c;
ADD c,a,b
c = a+b;
}

High-level language Assembly language Machine language

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 Introductioncntd

We will discuss:
Instruction Formats: How long is an instruction? How many
operands?
Instruction Types: What kind of operations?
Data Types: What kind of operands?
Addressing Modes: Where are the operands?

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 Instruction Format

Defines the layout of the bits of an instruction in terms of its

constituent fields (What does each field represent and how
many bits is it?)

Common formats:
Opcode Opcode Address
(zero operand ) (one operand )

Opcode Address1 Address2 Opcode Add.1 Add.2 Add.3

(two operands ) (three operands )

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 Instruction Formatcntd

Instruction length
How many bits for an instruction?
Affects and affected by:
Number of operations
Memory size
Memory organization
Bus structure
Processor complexity (e.g. number of registers)

Can be fixed-length or variable-length

Fixed-length: All instructions have the same length (but with different
formats)
Instruction decoding hardware simpler
o Wastes space (Instruction length is determined by the longest instruction)

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 X86 Instruction formats

The x86 architecture has variable-length instructions with different

formats. Examples:
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Opcode e.g. RET
5 3
Opcode Reg e.g. PUSH reg

8 8
Opcode Address e.g. JE address

8 16
Opcode Address e.g. JMP address

8 8 16
Opcode reg Immediate e.g. ADD reg, 500

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 Instruction Types

Common types:
Data transfer(Data movement)
Arithmetic
Logical
Input/output
Transfer of control(Program flow control)
System control

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 Data Transfer

Copy values from one location to another

(e.g. MOV, LEA, IN/OUT, PUSH/POP)
MOV destination, source
Destination: can be register or memory location
Source: can be register, memory location or an immediate
number
e.g. MOV CX, 20 place the value 20 in CX register (CX20)
MOV CX, [20] copy value at memory location 20 to CX
CPU Memory CPU Memory
CX 0 19 78 CX 96 19 78
20 96 20 96
21 0 21 0

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 Data Transfercntd

PUSH source
Used to transfer data to stack
Source: can be register or memory location

e.g. PUSH CX copy CX to stack

CPU Stack CPU Stack

CX 96 23 CX 96 96
15 23
0 15

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 Data Transfercntd

POP destination
Used to retrieve data from stack
Destination: can be register or memory location

e.g. POP BX copy data on top of stack to register BX

CPU Stack CPU Stack

BX 0 96 BX 96 23
23 15
15 0

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 Arithmetic

(e.g. ADD, INC, SUB, DEC,MUL,DIV)

ADD destination, source
Destination: can be register or memory location
Source: can be register, memory location or an immediate
number
e.g. ADD CX, BX (CXCX+BX)

CPU CPU
BX 96 BX 96
CX 96 CX 192

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 Arithmeticcntd

DEC destination
Destination: can be register or memory location

e.g. DEC CX (CXCX-1)

CPU CPU
CX 192 CX 191

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 Arithmeticcntd

MUL source
Source: can be register or memory location
Destination is an accumulator register, AX
e.g. MUL BL (AXAL x BL)

CPU
BX 96
0 96 CPU

AX 960(03C0H)
AX 10
03H C0H
0 10

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 Logical

Operate on a bit-by-bit basis

(e.g. AND, OR, XOR, NOT, SHR, SHL)

e.g. AND CX, BX (CXCX AND BX)

CPU CPU
BX 96 (60H) BX 96(60H)
CX 191(BFH) CX 32(20H)

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 Input/output

Instructions to read data from an input module and to

write data to an output module
(e.g. IN, OUT)
IN accumulator, port OUT port, accumulator
Port: address of the I/O module (8-bits for 8086)

e.g. IN AL, 60H (read keyboard port)

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 Transfer of control

Instructions discussed so far execute sequentially

Transfer of control instructions change the sequence

of execution (update value of the program counter
(PC))

Common transfer of control instructions

Branch (Jump) instructions
Procedure call instruction
Skip instructions

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 Transfer of controlcntd

Branch (Jump) Instruction

Has address of next instruction as an operand
Conditional branch: branch is made if a certain condition is
met
e.g. JZ target (Jump to target address if result of previous
operation is zero)
e.g. SUB CX, 32
CX=CX-32;
JZ label
If(CX==0)
{
label: BX=10;
}
MOV BX, 10

Let label indicates the address 204

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 Transfer of controlcntd
CPU Memory CPU Memory
BX 96 200 SUB CX,32 BX 96 200 SUB CX,32
CX 32 201 JZ 204 CX 0 201 JZ 204
202 202
PC (IP) 200 203 PC (IP) 201
203
ZF 0 204 MOV BX,10 ZF 1 204 MOV BX,10

CPU Memory CPU Memory

BX 96 200 SUB CX,32 BX 10 200 SUB CX,32
CX 0 201 JZ 204 CX 0 201 JZ 204
202 202
PC (IP) 204 203 PC (IP) 205
203
204 MOV BX,10 204 MOV BX,10

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 Transfer of controlcntd

Unconditional branch: branch is made without any condition

e.g. Jmp target (Jump to target address)

CX=CX-32;
e.g. SUB CX, 32
goto label;
Jmp label
label:

BX=10;
label:
MOV BX, 10

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 Transfer of controlcntd

Procedure call Instructions

Instruct the processor to go and execute an entire
procedure and return

Procedure:
Small, self-contained program within a larger program
(like function in high-level languages)
Allows same piece of code to be used many times
e.g. CALL subroutine ..RET

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 Transfer of controlcntd

CX=CX-32;
e.g. SUB CX, 32 Sub();
CALL sub
Void sub()
sub: {
BX=10;
MOV BX, 10 }
RET

Let sub indicates the address 204

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 Transfer of controlcntd
CPU Memory CPU Memory
BX 96 200 SUB CX,32 BX 96 200 SUB CX,32
CX 32 201 CALL 204 CX 0 201 CALL 204
202 202
PC (IP) 200 203 PC (IP) 201
203
204 MOV BX,10 204 MOV BX,10
205 RET 205 RET
CPU Memory CPU Memory
BX 96 200 SUB CX,32 BX 10 200 SUB CX,32
CX 0 201 CALL 204 CX 0 201 CALL 204
202 202
PC (IP) 204 203 PC (IP) 205
203
204 MOV BX,10 204 MOV BX,10
205 RET 205 RET
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 Transfer of controlcntd
CPU Memory
BX 10 200 SUB CX,32
CX 0 201 CALL sub
202
PC (IP) 202 203
204 MOV BX,10
205 RET

During a call operation the return address of memory has

to be saved first

Generally the return address is saved in stack

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 More Readings

1. Computer Architecture and Organization,

William Stallings, 8th edition (chapters 10&11)

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