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    8254 Timer

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    Yosef Kiros
    The 8253/54 is a programmable interval timer chip used in PCs to generate precise timing and frequency signals. It contains 3 independent timers that can be programmed to different modes and divisors using an 8-bit control word. The 8254 is an enhanced version that supports higher clock frequencies up to 10MHz. Initialization involves sending control words and divisors to each timer register to set the desired timing parameters.

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    © All Rights Reserved
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    8254 Timer

    Uploaded by

    Yosef Kiros
    102 views19 pages
    The 8253/54 is a programmable interval timer chip used in PCs to generate precise timing and frequency signals. It contains 3 independent timers that can be programmed to different modes and divisors using an 8-bit control word. The 8254 is an enhanced version that supports higher clock frequencies up to 10MHz. Initialization involves sending control words and divisors to each timer register to set the desired timing parameters.

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    8254-timer

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    The 8253/54 is a programmable interval timer chip used in PCs to generate precise timing and frequency signals. It contains 3 independent timers that can be programmed to different modes and divisors using an 8-bit control word. The 8254 is an enhanced version that supports higher clock frequencies up to 10MHz. Initialization involves sending control words and divisors to each timer register to set the desired timing parameters.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    102 views19 pages

    8254 Timer

    Uploaded by

    Yosef Kiros
    The 8253/54 is a programmable interval timer chip used in PCs to generate precise timing and frequency signals. It contains 3 independent timers that can be programmed to different modes and divisors using an 8-bit control word. The 8254 is an enhanced version that supports higher clock frequencies up to 10MHz. Initialization involves sending control words and divisors to each timer register to set the desired timing parameters.

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    © All Rights Reserved
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    8253/54 Timer

    8253/54 Timer Description and Initialization


    • PTI (programmable Interval Timer)
    • The 8253 chip was used in the IBM PC/XT, but starting with
    the IBM PC/AT, the 8254 replaced the 8253.
    • 8253 and 8254 have exactly the same pinout.
    • 8254 is a superset of the 8253.
    Programmable Interval Timer - 8254
    Pin Description of 8253/54
    A0, A1, and CS
    • Inside the 8253/54 timer, there
    are 3 counters.
    • Each timer works independently
    and programmed separately.
    • Each counter is assigned an
    individual port address.
    • The control register common to
    all 3 counters and has its own
    port.
    CLK
    • CLK is the input clock frequency, which can range between 0 and 2
    MHz for the 8253.
    • For input frequencies higher than 2 MHz, the 8254 must be used.
    • The 8254 can go as high as 8 MHz, and 8254-2 can go 10 MHz.
    OUT
    • Can have square-wave, one-shot, and other square-shape waves for
    various duty cycles but no sine-wave or saw-tooth shapes.
    Gate
    • This pin is used to enable or disable the counter.
    D0-D7
    • The D0-D7 data bus of the 8253/54 is a bidirectional bus
    connected to D0-D7 of the system data bus.
    • RD and WR are connected to IOR and IOW control signals of the
    system bus.
    Initialization of the 8253/54
    • Each of the three counters of the 8253/54 must be programmed
    separately.
    • The 8253/54 must be initialized before it is used.
    Control word
    The figure shows the one-byte control word of the 8253/54.
    • D0 chooses between a binary number divisor of 0000 to
    FFFFH or a BCD divisor of 0000 to 9999H.
    • The highest number is 216 for binary and 104 for BCD.
    • To get the highest count, the counter is loaded with zeros.
    • D1, D2, and D3 are for mode selection.
    • D4 and D5 are for RL0 and RL1
    • RL0 and RL1 are used to indicate the size of the divisor, and have
    3 options:
    1. Read/write MSB only
    2. Read/write LSB only
    3. Read/write LSB first followed immediately by the MSB.
    Operation Modes
    Mode 0 Interrupt on terminal count
    Mode 1 Programmable one-shot
    Mode 2 Rate Generator
    Mode 3 Square wave rate generator
    Mode 4 Software triggered strobe
    Mode 5 Hardware trigger strobe
    • All counters are down counters.
    • D6 and D7 are used to select the 3 counters, counter 0, counter
    1, or counter 2, is to be initialized by the control byte.
    • To program a given counter of the 8253/54 to divide the CLK
    input frequency one must send the divisor to that specific
    counter’s reg.
    • To divide the frequency by 10000 (BCD) or 65536 (binary) we
    must send in 0 for both high and low bytes.

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