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˜ What is FPGA?
˜ History of Evolution
˜ FPGA programmability
Antifuse Programming
SRAM Programming
Floating Gate programming
˜ FPGA Architecture
CLB
IOB
Programmable Floating Channel
˜ Why FPGA?
˜ FPGA Drawbacks
˜ Application
˜ Conclusion 0
WHAT IS FPGA?
It is an IC(Integrated Circuit)

˜ with a very high logic capacity

˜ Completely programmable even after the a

product is shipped or in the ´fieldµ so the name is
given.

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HISTORY OF EVOLUTION:
˜ FPGAs belong to a class of devices named as
FPD(field programmable device) or
PLD(programmable logic devices)

˜ FPD/PLDs- can be configured by the end user to

realize various functionality.

˜ The evolution of FPGA goes like this

PROM PLA PAL CPLD FPGA

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HISTORY OF EVOLUTION (CNTD«)
Programmable Read Only Memory (PROM)
Structure
˜ fuse programming

˜ n address i/p can implement n i/p logic

function
˜ uses full decoder for its i/p

Problem
˜ Area efficiency
fuses
PROM CELLS
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 HISTORY OF EVOLUTION (CNTD«)
Programmable Logic Array (PLA) Programmable Array Logic (PAL)
Structure Structure
˜ Programmable AND plane followed by ˜ Programmable AND plane and fixed
programmable or wired OR plane. OR plane.
˜ Sum of product form Advantage
Advantage ˜ Low cost and size.
No decoder required
Problem
Problem
˜ Less flexible than PLA
˜ Two levels of programming adds delay
and increases cost.

All these PLA and PAL are Simple Programmable Logic Devices (SPLD). ÿ
Common Problem:
Logic plane structure grows rapidly with number of inputs
HISTORY OF EVOLUTION (CNTD«)

To mitigate the problem

Complex Programmable Logic Devices (CPLD)

Structure
˜ programmably interconnect multiple SPLDs.

advantage
˜ logic capacity up to the equivalent of about 50 typical

SPLD devices

Problem :
˜ Extending to higher density difficult 
HISTORY OF EVOLUTION (CNTD«)
All the previous devices indicates that the
complete solution would be a

˜ Very high capacity device

with
˜ wide range of programmability.

Then FPGA came into the picture.

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˜ Programmability of FPGA is achieved in three
ways
y Antifuse programming methodology
y SRAM programming technology
y Floating Gate Programming

‰
$% &'())()''*'(

˜ Antifuse systems(eg. amorphous Si,ONO) are placed at the

junctions of different connecting paths.
˜ These systems(built of special materials) antifuse

normally have high resistance R>1Mohm

Before the
(effectively open circuits) antifuse blown

˜ Upon application of programming

voltage across them resistance drop to a
few ohms.
+( Connecting paths

˜ Small size
R=few
˜ Low series resistance and low ohms

parasitic capacitance After the antifuse

blown

+(
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˜ Interconnect is not reprogrammable

&'())(,'*'(

˜ Loads and stores values in SRAMs to facilitate

programmability
˜ to control pass gates.
1= closed switch connection
0= open
˜ For mux, SRAM determines
the mux input selection
process.
+(
 Fast re-programmability
 Standard IC fabrication Tech. is used
˜ +(
 SRAM volatile ""
 Requires large area
m*'(
 '())(

˜ Tech used in EPROM and EEPROM devices is used

+v
˜ Switch is disable by applying high
voltage to gate-2 between gate-1
and drain.
˜ The charge is removed by UV light Bit
Line
Advantage:--
Advantage:
˜ No external permanent Gate 1
EPROM
memory is needed to program it transister
at power-up
Word Gate 2
Disadvantage:-
Disadvantage:- line

y Extra processing steps

y Static power loss due to pull up
resistor and high on resistance "0
FPGA ARCHITECTURE
There are three primary configurable elements
in FPGA
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Configurable
-implement different functions.
0&% %&% *', 
- provides the interface between Program
mable
external pins and internal intercon
signal lines ection

u '())*'%( Routing
I/O
channel
bloc
!* k

-controls the connections among

different blocks Configura
ble logic
block

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- 
!  !.!
DIN SR
 CLBs contain
! # 

u Look Up
Table(F,G &H
function
generator)
SR

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Two D Flip-
Flops

And

 A group of

-/,''** MUXs
,'$(%'
&'()

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''-&*
˜ Can perform any function on its i/p depending on the values stored in the
memory location.
˜ Combination of F,G & H allows to implement a function of upto 9
variables.
+(
˜ Minimizes no. of blocks required
˜ Thereby increases speed and density
m*&11m*'&
m*&
˜ 2 edge triggered Flip-Flops are having common clock & clock enable i/ps
˜ Clock may be inverted before driving Flip-Flops thus configuring them as
either positive or negative edge triggered.
˜ Clock enable i/p to Flip-Flop is active high.
˜ Set-Reset i/p allows to set or reset Flip-Flops asynchronously.
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!!#00

-/
˜ Used to allow the intended signal to go to the
next stage.
˜ Allows the combinational functions o/p that is
F,G or H o/p to be o/p of the CLB through X or Y
˜ Controls the D Flip-Flop i/p (allows F,G or H o/p
or a direct input to CLB as DIN to go to the i/p of
d Flip-Flop)
˜ Determines triggering edge of the clock.

"ÿ
# - - -  !. 
Two types of IOBs are there
1)Dedicated for configuration of FPGA
2)User Configurable
User configurable IOBs can be configured as i/p,o/p or
bidirectional for providing connections of internal CLBs to
external package pins
# - !.
˜ The i/p signal can directly go to routing channel or it can go
via i/p register
˜ I/P register can be level or edge sensative
˜ Clock can be direct or inverted
˜ Registered data path has one tap delay element to adjust
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set up or hold time of Flip-Flops.
 # - - -  (CNTD..)
 !. 
- - !.
CLB o/ps can be inverted
and go directly or via a register
to the o/p buffer

 user controlled T i/p ORing with

GTS(Global Tri Sate)signal
controls o/p buffer(e.g-if high
,places buffer in high impedence
state)

GTS which is common to all

user IOBs is made high during
configuration

Programmable pull up or down

netwrk is there for connecting
unused pin to Vcc or GND.
"-
 


  -#
!2##

˜ Routing Channel-metallic
Channel conductor used to
make connection
˜ Three types are there
CLB Routing Channel:-runs along each row
and columns of CLBs.
IOB Routing Channel:-forms Versa Ring
outside CLB array & connects IOB with CLB
routing channels.
Global Routing Channel:-routs global signals
(eg. Clock) with minimum delay.
˜ Programmability in routing channels is obtained by
using :- (a)connection box and (b)switch box "‰
 


  -#

!2##(CNTD..)
˜ Connection Box:- Switch
connects channel wires box

to the i/o pins of CLBs.

˜ Switch Box:- allow

wires to switch between

vertical and horizontal
wires.
Connection
˜ Routing channels may
box
be of three types
(a)Single length,(b)double length & (c)long lines 0
 



 -#

!2##(CNTD..) SB SB SB
˜ Single length lines
span through one
CLB & provide
short connections
among CLBs CB CB CB
˜ Double length line
spans two CLBs,
offers low routing
delay.
˜ Long lines run SB SB SB
along entire
length or width of
the array

0"
longs doubles singles
 


  -#

!2##(CNTD..)
˜ Interconnect Point in both switching and
connection box ²implemented through 6 pass
transistors.
Interconnect Pass Transistors
point
vertical wires
2
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42 m
55
˜ In the field FPGA has strong opponent in the
form of ASIC(application Specific IC).
˜ ASICs are designed to perform a particular
function using custom design technique.
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˜ FPGAs are flexible,can be used for prototyping.

˜ Offers less time-to-market.

˜ NRE cost is low.

˜ Design cycle is simple

˜ Easy upgrades like software

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˜ FPGAs are lagging in some fields while compared
to ASICs
1) ASICs are specifically designed for some
purpose, so are faster than FPGAs.
2) ASICs require less power than FPGAs.

u) ASICs are cost effective for very large volume

design.

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 ! #
˜ Applications of FPGAs include
(a)digital signal processing,
(b)aerospace and defense systems,
(c)ASIC prototyping,
(d)medical imaging,
(e)metal detection
and a growing range of other areas.

˜ The inherent parallelism of the logic resources on an

FPGA allows for considerable computational
throughput. This has driven a new type of processing
called reconfigurable computing, where time intensive
tasks are offloaded from software to FPGAs. 0Ñ
! #!- #
˜ Choice of ASICs or FPGAs are completely case
dependent
˜ For a good design technique and implementation
a perfect mixture of both will ensure the
optimum profitability.

0ÿ
m#!
˜ ''
CMOS VLSI DESIGN
-by NEIL H.E. WESTE
DAVID HARRIS
AYAN BANERJEE
FPGA-Based System Design
-by WAYNE WOLF
˜ 4
1.http://www.wikipedia.org
2.http://searchcio-midmarket.techtarget.com
u.http://www.vlsibank.com
4.http://web.ukonline.co.uk
5.http://www.electronicsweekly.com 0
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