ECE 331 - Digital System Design: Derivation of State Graphs and State Tables
ECE 331 - Digital System Design: Derivation of State Graphs and State Tables
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Material to be covered …
X= 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0
Z= 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0
(time: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)
Fall 2010 ECE 331 - Digital System Design 6
Example: A sequence detector (Mealy)
Design in progress …
Design in progress …
Design in progress …
Design in progress …
Design in progress …
A sequential circuit has two inputs (X1, X2) and one output (Z). The output
remains a constant value unless one of the following input sequences
occurs:
(a) The input sequence X1X2 = 01, 11 causes the output to become 0.
(b) The input sequence X1X2 = 10, 11 causes the output to become 1.
(c) The input sequence X1X2 = 10, 01 causes the output to change value.
XiXj / ZpZq means if inputs Xi and Xj are 1 (we don’t care what
the other input values are), the outputs Zp and Zq are 1 (and
the other outputs are 0). That is, for a circuit with four inputs
(X1, X2, X3, and X4) and four outputs (Z1, Z2, Z3, and Z4),
X1X4′ / Z2Z3 is equivalent to 1--0 / 0110.
This type of notation is very useful for large sequential circuits
where there are many inputs and outputs.