Ho Chi Minh City University of Technology

FACULTY OF COMPUTER SCIENCE & ENGINEERING

Laboratory Manual
Digital Systems
Experiment 5

Ho Chi Minh City, 11/2022

 Digital Systems – Lab 6

1. INTRODUCTION

1.1 Goals:
 Understand the design procedure of Synchronous Counter.
 Understand how MSI circuits works
 Design and implement basic Synchronous Counters and MSI circuits.

1.2 Equipment and apparatus:

 Digital System KIT
 Lab tools: VOM, Oscilloscope
 74-Series Integrated Circuits (IC): new type!! 74151, 74138, 7485

1.3 References:
 Digital Systems: Principles and Applications (11th Edition) – Ronald J. Tocci, Neal S.
Widmer, Gregory L. Moss, 2010.
 Lecture Slides/Videos – Assoc. Prof. Dr. Tran Ngoc Thinh.

1.4 Pre-laboratory:
 Read this experiment carefully to become familiar with the procedural steps in this
experiment.

1.5 Safety First

 You are dealing with live power. Be mindful of the current and voltage you are supplying
to the circuit. No drinks on the working surface!

1.6 Submit your reports:

 Complete all exercises in Section 2.3. Show all of your work step-by-step.
 Capture and include images about your implemented circuits in Logisim, KIT, and Tools
 Submit report to BKeL by deadline.

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2. EXPERIMENTAL PROCEDURE:

2.1 Synchronous Counter

In the previous experiment, we already worked with Asynchronous Counters. This experiment,
we will continue to design and implement synchronous counters.
In Synchronous counters, the counting sequence is controlled by means of a clock pulse and
changes in the output occur in “synchronization” with the clock signal. In particular, the clock
signal is connected to the clock input of EVERY individual flip-flop within the counter so that
all of the flip-flops are triggered together simultaneously (in parallel) at the same.

Step to design a synchronous counter:

1. Determine the number of FFs needed to support the

counting sequence.

2. Build a State Transition Diagram. Be sure to include all

states.

3. Build a State/Excitation Truth Table.

4. Simplify expressions for the inputs of each FF using K-

Map methods.

5. Implement the Synchronous Counter/State Machine

Circuit.

Example: Design and implement a MOD-4 Synchronous Counter using D Flip-flops

1. Determine the number of Flip-flops needed to support the number of states in the
counting sequence
A synchronous counter with n flip-flops can count 2𝑛 − 1 possible states.
2𝑛 − 1 ≥ 𝑡ℎ𝑒 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑡𝑎𝑡𝑒𝑠

With a MOD-4 counter, we have four states. Therefore, we need at least two FFs to build it.

2. Build a State Transition Diagram. Be sure to include all states

We can describe the counting sequence of counters by using a
00 CLK
State Transition Diagram (State Machine), where the nodes CLK
represent the states and the edge represents transitions. The
triggering of clock will cause the transition to next state 11 01

The following figure depicts the State Transition Diagram of CLK CLK
10
a MOD-4 Synchronous Counter.
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3. Build a State/Excitation Truth Table

An excitation table shows the minimum inputs that are necessary to generate a particular next state
(in other words, to "excite" it to the next state) when the current state is known. They are similar to
truth tables and state tables, but rearrange the data so that the current state and next state are next
to each other on the left-hand side of the table, and the inputs needed to make that state change
happen are shown on the right side of the table.

In order to obtain the excitation table of a flip-flop, one needs to draw the Q(t) and Q(t + 1) for all
possible cases (e.g., 00, 01, 10, and 11), and then make the value of flip-flop such that on giving
this value, one shall receive the input as Q(t + 1) as desired.

Figure 1: Flip-Flop Excitation Tables

By referencing the FF’s excitation tables, we design an excitation table to summarize the state
machine. The following excitation table is used for MOD-4 Synchronous counter using D Flip-
flops.

Current State Input Next State

Q1 Q0 D1 D0 Q1 (Next) Q0 (Next)
0 0 0 1 0 1
0 1 1 0 1 0
1 0 1 1 1 1
1 1 0 0 0 0
Figure 2: The excitation table of MOD-4 counter

4. Simplify expressions for the inputs of each FF using K-Map methods

Based on the excitation table we obtain the simplified function of each input by using K-Map
methods

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 Digital Systems – Lab 6

K-Map for D1 K-Map for D0

Figure 3: K-Map for D1, D0

5. Implement the Synchronous Counter

Once obtained the expression for the input of each FF, we can implement the circuit for the counter.
The implementation of MOD-4 Synchronous Counter is depicted as the following figure.

Figure 4: MOD-4 Synchronous Counter

Warm-up: Let try using Logisim to design and implement a MOD-4 Synchronous
Counter

2.2 MSI Circuits

2.2.1 Multiplexer (MUX)

The Multiplexer (MUX), also called Data Selector, is a device that acts as a multi-position
switch. See Figure 1. A number of DATA inputs are applied to this device (I0-I3) and one of
the inputs is switched to the output (Y) of the device. A binary number applied to the SELECT
(S1 & S0) lines controls which input is passed to the output.

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S1 S0 Y

0 0 I0 I0
0 1 I1
I1
1 0 I2
Y
1 1 I3 I2

S0 I3
0 1
S1 S0
I0 I1
S1
0

1 I2 I3

Figure 5: Truth table, logic graph, and block diagram of a 4-to-1 multiplexer.

For example, when S1=S0=0, I0 is “logically” connected to the output Y. When S1=0 & S0=1,
I1 “logically” connected to Y and so forth for I2 & I3 to connect to Y.

IC 74151
74151 is an 8-to-1 Multiplexer with 16 Pin IC. Data Selector/Multiplexer contains full on-chip
decoding to select one-of-eight data sources as a result of a unique three binary code at select
inputs.

Figure 6: Logic Symbol and Truth table of IC 74151

2.2.2 Decoder

Decoder circuits receive inputs in the form of an N-bit binary number and generate one or more
outputs according to some requirement. A binary decoder has N inputs and 2N outputs. If the
N inputs are taken as an N-bit binary number, then only the output that corresponds to the input
binary number is asserted.

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 Digital Systems – Lab 6

For example, in the 3:8 binary decoder shown in the figure below, if a binary 5 (or “101”) is
presented on the input of the decoder, then only the 5th output of the decoder (Y5) will be
asserted and all of the other outputs will be de-asserted.

I2 I1 I0 Y[7:0]
Y0
0 0 0 00000001 Y1
0 0 1 00000010 Y2
0 1 0 00000100 I0
I1 Y3
0 1 1 00001000 Y4
1 0 0 00010000 I2
Y5
1 0 1 00100000 Y6
1 1 0 01000000 Y7
1 1 1 10000000

Figure 7: Truth Table and Block Diagram of a 3:8 Binary Decoder.

IC 74138

74LS138 is designed for decoding or de-multiplexing applications and comes with 3 inputs to
8 output setup.. The three enable pins of chip (in which TWO active-low and ONE active-high)
reduce the need for external gates or inverters when expanding.

Figure 8: Pin Diagram and Truth table of IC 74138 . Note: G2 = G2A + G2B

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2.2.3 Comparator

Comparator is a combination circuit that compares two digital or binary numbers in order to
find out whether one binary number is equal, less than or greater than the other binary number.
The following figure describes 1-bit Digital Comparator Circuit.

Figure 9: 1-bit Digital Comparator Circuit

IC 7485

74LS138 is a 4-bit magnitude comparator have additional input terminals that allow more
individual comparators to be “cascaded” together to compare words larger than 4-bits with
magnitude comparators of “n”-bits being produced.

Figure 10: Pin diagram and truth table of IC 7485

2.3 Exercise

2.3.1 Design, simulate, and implement a MOD-4 Synchronous Down Counter using D Flip-
flops
2.3.2 Design, simulate and implement an 8-to-1 Multiplexer using IC 74151
2.3.3 Design and simulate a 3-to-8 Decoder using IC 74138 in Logisim.
2.3.4 Design and simulate an 8-bit magnitude comparator using IC 7485 in Logisim.