R65C51

ASYNCHRONOUS COMMUNICATIONS

PRELiMlNARY
DESCRIPTION FEATURES
The Rockwell CMOS R65C51 Asynchronous Communications Low power CMOS N-well silicon gate technology
Interface Adapter (ACIA) provides an easily implemented, pro- Direct replacement for NMOS R6551 ACIA
gram controlled interface between 8-bit microprocessor-based Full duplex operation with buffered receiver and transmitter
systems and serial communication data sets and modems.
Data set/modem control functions

The ACIA has an internal baud rate generator. This feature elim- Internal baud rate generator with 15 programmable bau
inates the need for multiple component support circuits, a crystal rates (50 to 19,200)
being the only other part required. The Transmitter baud rate . Program-selectable internally or’externally controlled receive
can be selected under program control to be either 1 of 15 dif- rate
ferent rates from 50 to 19,200 baud, or at l/16 times an external . Programmable word lengths, number of stop bits, and pant
clock rate. The Receiver baud rate may be selected under pro- bit generation and detection
gram control to be either the Transmitter rate, or at l/16 times Programmable interrupt control
the external clock rate. The ACIA has programmable word
Program reset
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'12, or
Program-selectable serial echo mode
2 stop bits.
Two chip selects
The ACIA is designed for maximum programmed control from 1 or 2 MI-Q operation
the microprocessor (MPU), to simplify hardware implementa- 5.0 Vdc t 5% supply requirements
tion. Three separate registers permit the MPU to easily select 28-pin plastic or ceramic DIP
the R65C51’s operating modes and’ data checking parameters
Full TTL compatibility
and determine operational status.
Compatible with. R6500, R6500/’ and R65COO micro-
The Command Register controls parity, receiver echo mode, processors
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.

The Control Register controls the number of stop bits, word

length, receiver clock source, and baud rate.
--
The Status Register indicates the states of the IRQ, DSR, and
DCD lines. Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions,

The Transmitter and Receiver Data Registers are used for tem-
porary data storage by the ACIA Transmit and Receiver circuits.

ORDERING INFORMATION

Part No.: R65C51

Temperature Range (TL to TH):

Blank = 0% to +70°C
E= -40% to +85%

- Frequency Range:
1 = 1 MHz
2 = 2 MHz

Package:
C = Ceramic
P = Plastic
Figure 1. R65C51 AClA Pin Configuration

Document No. 29651 N60 Product Description Order No. 2157

2-296 Rev. 3, October 1984
 RGSCEi’O Asynchronous Communications. Interface Adapter (ACIA)

TRANSMIT
I
I
CONTROL l-
I
CTS

t
1 , *
> TRANSMIT ’ TRANSMIT
I DATA > SHIFT __) TxD
; __c REGISTER REGISTER
& .
4p Dcd
STATUS
REGISTER + DSR
l
’ BAUD N RxC
a CONTROL c RATE -XTLt
cI REGISTER GENERATOR __c XTl_O
L
a COMMAND ’ tDTR
cc REGISTER ,RTS
RSl ------ 1

$2 RECEIVE
TIMING 1 t SHIFT RxD
RES L REGISTER
* REGISTER

I RECEIVE
CONTROL
1

Figure 2. ACIA Internal Organization

FUNCTIONAL DESCRIPTION TIMING AND CONTROL

: block diagram of the ACIA is presented in Figure 2 followed The Timing and Control logic controls the timing of data trans-
zy a descrtption of each functional element of the device. fers on the internal data bus and the registers, the Data Bus
Buffer, and the microprocessor data bus, and the hardware
DATA BUS BUFFERS reset features.
The Data Bus Buffer interfaces the system data lines to the inter-
Timing is controlled by the system 82 clock input. The chip WIII
Ial data bus. The Data Bus Buffer is bidirectional. When the
perform data transfers to or from the microcomputer data bus
%i? line is low and the chip is selected, the Data Bus Buffer
during the $2 high period when selected.
.vntes the data from the system data lines to the ACIA internal
zata bus. When the Rfi line is high and the chip is selected, All registers will be initialized by the Timing and Control Logic
:?e Data Bus Buffer drives the data from the internal data bus
when the Reset (m) line goes low. See the individual register
‘3 the system data bus. description for the state of the registers following a haraware
reset.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor
‘3 50 low when conditions are met that require the attention of TRANSMllTER AND RECEIVER DATA REGISTERS
:ne mlcroprocessor. The conditions which can cause an inter-
‘uot will set bit 7 and the appropriate bit of bits 3 through 6 in These registers are used as temporary data storage for the
:ne Status Register, if enabled. Bits 5 and 6 correspond to the ACIA Transmit and Receive Circuits. Both the Transmitter and
3ata Carrier Detect (DCD) logic and the Data Set Ready (DSR) Receiver are selected by a Register Select 0 (RSO) and Register
ogle. Bits 3 and 4 correspond to the Receiver Data Register full Select 1 (RSl) low condition. The Read/Write (R/m) line deter-
3na the Transmitter Data Register empty conditions. These con- mines which actually uses the internal data bus: the Transmitter
Xons can cause an interrupt request if enabled by the Com- Data Register is write only and the Receiver Data Register 1s
-and Register. read only.

Bit 0 is the first bit to be transmitted from the Transmttter Data

110 CONTROL
Register (least significant bit first). The higher order bits follow
The IO Control Logic controls the selectlon of internal registers in order. Unused bits in this register are “don’t care”.
‘n Preparation for a data transfer on the Internal data bus and
!he direction of the transfer to or from the register. The Receiver Data Regtster holds the first received data bit In
bit 0 (least significant bit first). Unused high-order bits are “0”.
The registers are selected by the Receiver Select (RSl, RSO) Parity bits are not contained in the Receiver Data Register. They
and Read Write (R/w) lines as described later in Table 1. are stripped off after being used for parity checking.

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R&C51 Asynchronous Communications Interface Adapter (ACIA

STATUS REGISTER Parity Error (Bit 0), Framing Error (Bit l), and
The Status Register indicates the state of interrupt conditions
Overrun (2)
and other non-interrupt status lines. The interrupt conditions are None of these bits causes a processor interrupt to occur, t
the Data Set Ready, Data Carrier Detect, Transmitter Data Reg- they are normally checked at the time the Receiver Data Re
ister Empty and Receiver Data Register Full as reported in bits ister is read so that the validity of the data can be verified. The
6 through 3, respectively. If any of these bits are set, the Inter- bits are self clearing (i.e., they are automatically cleared at:
rupt (IRQ) indicator (bit 7) is also set. Overrun, Framing Error, a read of the Receiver Data Register).
and Parity Enor are also reported (bits 2 through 0 respectively).

7 6 5 4 3 2 1 0
t ,
Receiver Data Register Full (Bit 3)
IRG DSR DCD TDRE RDRE OVRN FE PE
This bit goes to a 1 when the ACIA transfers data from :’
4
Receiver Shift Register to the Receiver Data Register. and go.
Bit 7 Interrupt (IRQ) to a 0 (is cleared) when the processor reads the Receiver D;
0 No interrupt Register.
1 Interrupt has occurred

Bit 6 Data Set Ready (DSR)

0 DSR low (ready) Transmitter Data Register Empty (Bit 4)
1 DSR high (not ready)
This bit goes to a 1 when the ACIA transfers data from tr
Transmitter Data Register to the Transmitter Shift Register, ar
Bit 5 Data Carrier Detect (DCD) goes to a 0 (is cleared) when the processor writes new da-
0 DCD low (detected)
onto the Transmitter Data Register.
1 DCD high (not detected)

Bit 4 Transmitter Data Register Empty

0 Not empty Data Carrier Detect (Bit 5) and Data Set Ready
1 Empty (Bit 6)
Bit 3 Receiver Data Register Full These bits reflect the levels of the DCD and DSR inputs to tt
0 Not full ACIA. A 0 indicates a low level (true condition) and a 1 indicate
1 Full a high level (false). Whenever either of these inputs chant
state, an immediate processor interrupt (IRQ) occurs. unless :
Bit 2 Overrun* 1 of the Command Register (IRD) is set to a 1 to disable IR(
0 No overrun When the interrupt occurs, the status bits indicate the levels
1 Overrun has occurred the inputs immediately after the change of state occurred. SL
sequent level changes will not affect the status bits until t’
Bit 1 Framing Error’ Status Register is interrogated by the processor. At that tirr
0 No framing error another interrupt will immediately occur and !he status !I
1 Framing error detected reflect the new input levels. These bits are not automatica
cleared (or reset) by an internal operation.
Bit 0 Parity Error*
0 No parity error
1 Parity error detected
Interrupt (Bit 7)
‘No interrupt occurs for these conditions
This bit goes to a 1 whenever an interrupt condition occurs ar
goes to a 0 (is cleared) when the Status Register IS read.
Reset initialization

76543210
0 -1-I 1 0 0 0 0 Hardware reset
- -/-(- - 0 - _ ’ Program reset
1

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 m
-
R65C5 1 Asynchronous Communications Interface Adapter (ACIA)

CONTROL REGISTER Selected Baud Rate (Bits 0, 1, 2, 3)

Y antrot Register selects the desired baud rate, frequency These bits select the Transmitter baud rate, which can be at
-. word length, and the number of stop bits. ‘I16 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator.
7 6 5 4 3 2 1 0
.
c If the Receiver clock uses the same baud rate as the transmitter,
WL S8R then RxC becomes an output and can be used to slave other
SBN ’ 1 RCS
WLl WLO SBR3 SBR2 SBRl SBRO circuits to the ACIA. Figure 3 shows the Transmitter and Receiver
\ layout.
Bit 7 Stop Bit Number (SBN)
? 1 Stop bit
i
. 2 Stop bits
. I 1:~Stop bits
For WL = 5 and no parity
: 1 Stop bit
For WL = 8 and parity I
1
RECEIVER
SHIFT REGISTER
I-_r
J
RxD

Bits 6-5 Word Length (WL) t

.
_ r No. Bits
4
‘3 CLOCK SYNC
3 -? 8 * DIVIDER e LOGIC
3 1 7 (16) ‘
. 0 6 RxC
. 1 5

Bit 4 Receiver Clock Source (RCS)

External receiver clock BIT 4
0 . CLOCK
1 Baud rate XTU C
BAUD RATE + DIVIDER
XTLOC GENERATOR (16)
Bits 3-o Selected Baud Rate (SBR)
3 2 1 0 Baud f t t t, 1
-Ti- 0 0 016x
r;;T;;:” TRANSMITTER
0 0 0 1 50 1 SHIFT REGISTER I-- TxD
0 0 1 0 75 REGISTER
0 0 1 1 109.92
3 1 0 0 134.58
0 1 0 1 150
Figure 3. Transmitter/Receiver Clock Circuits
0 7 1 0 300
0 1 1 1 600
9 0 0 0 1200
: 0 0 1 1800
1 0 1 0 2400
Receiver Clock Source (Bit 4)
1 0 1 1 3600 This bit controls the clock source to the Receiver. A 0 causes
1 1 0 0 4800 the Receiver to operate at a baud rate of l/16 an external clock.
? 1 0 1 7200 A 1 causes the Receiver to operate at the same baud rate as
1 1 1 0 9600 is selected for the transmitter.
1 1 1 1 19.200
Word Length (Bits 5, 6)
?eset Initialization
These bits determine the word length to be used (5, 6, 7 or 8
76543210 bits).
o o o o 0 0 0 0 Hardware reset (i%%)
‘ZJZFQ$j Program reset Stop Bit Number (Bit 7)
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1% stop bits if the word
length is 5 with no parity selected, 1 stop bit if the word length
is 8 with parity selected, and 2 stop bits in all other configurations.

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 R65C51 Asynchronous Communications Interface Adapter (ACIA

COMMAND REGISTER Data Terminal Ready (Bit 0)

The Command Register controls specific modes and functions. This bit enables all selected interrupts and controls the state o*
the Data Terminal Ready (m) line. A 0 indicates the micro-
76543210 computer system is not ready by setting the DTR line high. b
1 indicates the microcomputer system is ready by setting the
PMC TIC
PME REM 1 - IRD DTR DTR line low. fi line low. m also enables and disables
PNCl PNCO TIC1 TIC0 the transmitter and receiver.

Receiver Interrupt Control (Bit 1)

Bits 7-6 Parity Mode Control (PMC)
7 6 This bit disables the Receiver from generating an interrupt whee
‘i;j- 0 Odd parity transmitted/received set to a 1. The Receiver interrupt is enabled when this bit is SE
0 1 Even parity transmitted/received to a 0 and Bit 0 is set to a 1.
1 0 Mark parity bit transmitted
Parity check disabled
Transmitter Interrupt Control (Bits 2, 3)
1 1 Space parity bit transmitted
Parity check disabled These bits control the state of the Ready to Send (m) line an’
the Transmitter interrupt.
Bit 5 Parity Mode Enabled (PME)
0 Parity mode disabled
No parity bit generated Receiver Echo Mode (Bit 4)
Parity check disabled . A 1 enables the Receiver Echo Mode and a 0 disables the
1 Parity mode enabled Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
0. In the Receiver Echo Mode, the Transmitter returns eact
Bit 4 Receiver Echo Mode (REM) transmission received by the Receiver delayed by one-half bi-
0 Receiver normal mode time.
1 Receiver echo mode bits 2 and 3
Must be zero for receiver echo mode, m will
be low. Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disable:
Bits 3-2 Transmitter Interrupt Control (TIC) parity bit generation by the Transmitter and parity bit checking
3 2 by the Receiver. A 1 bit enables generation and checking c
00 RTS = High, transmitter disabled parity bits.
0 1 RTS = Low, transmit interrupt enabled
1 0 RTS = Low, transmit interrupt disabled
1 1 I?% = Low, transmit interrupt disabled Parity Mode Control (Bits 6, 7)
transmit break on TxD These bits determine the type of parity generated by the Trans
mitter, (even, odd, mark or space) and the type of parity chec
Bit 1 Receiver Interrupt Request Disabled (IRD) done by the Receiver (even. odd, or no check).
0 IRQ enabled (receiver)
1 IRQ disabled (receiver)
Reset Initialization
Bit 0 Data Terminal Ready (DTR) 76543210
I Hardware reset (m)
0 Data terminal not ready (m high)’ ~olololo~o~o~o~o~
1.
--1-1-t ]ojo~O~O~o, Program reset
1 Data terminal ready (fi low)

NOTE
‘The transmitter is disabled immediately. The receiver is
disabled but will first complete receiving a byte in process
of being received.

2-300
 5s
Asynchronous Communications Interface Adapter (ACIA)

NTERFACE SIGNALS Interrupt Request (m)

_2. *e-a srows the ACIA interface signals associated with the The iis1s pin is an interrupt output from the interrupt control logic.
-&zrocessor and the modem. It is an open drain output, permitting several devices to be con-
nected to the common m microprocessor input. Normally a
high level, m goes low when an interrupt occurs.
1

a--m Data Bus (00-07)

The eight data line (DO-D7) pins transfer data between the pro-
TRANSMIT

cl
cessor and the ACIA. These lines are bi-directional and are nor-
DATA & mally high-impedance except during Read cycles when the
-_) TxD
SHIFT ACIA is selected.
REGISTERS

c-OCD
.--iz% Chip Selects (CSO, a)
I/O W RxC
CONTROL BAUD The two chip select inputs are normally connected to the pro-
RATE * XTLI cessor address lines either directly or through decoders. The
GENERATOR --c XTLO ACIA is selected when CSO is high and C%i is low. When the
ACIA is selected, the internal registers are addressed in accor-
dance with the register select lines (RSO, RSl).
62
RES
I COMMAND
REGISTER I Register Selects (RSO, RSl)
The two register select lines are normally connected to the pro-
cessor address lines to allow the processor to select the various
C Rx0 ACIA internal registers. Table 1 shows the internal register
select coding.

Figure 4. ACIA Interface Diagram

Table 1. ACIA Register Selection

Register Operation
ICROPROCESSOR INTERFACE
RSl RSO Rl%ij=Low Rm = High
eset (RES) L L Write Transmit Data Read Recewer
Resister Data Reaister
mng system initialization a low on the RES input causes a
irdware reset to occur. Upon reset, the Command Register Programmed Reset
Id the Control Register are cleared (all bits set to 0). The
atus Register is cleared with the exception of the indications
Data Set Ready and Data Carrier Detect, which are externally
)ntrolled by the DSR and DCD lines, and the transmitter Empty
:. which is set. RES must be held low for one 82 clock cycle l-l H Write Control Read Control
r a reset to occur. Register Register
I

Iput Clock (82)

ie input clock is the system 82 clock and clocks all data trans-
! ‘ers between the system microprocessor and the ACIA.
Only the Command and Control registers can both be read and
written. The programmed Reset operation does not cause any
i Read/Write (RN)
data transfer, but is used to clear bits 4 through 0 in the Com-
1 The R/W input. generated by the microprocessor controls the mand register and bit 2 in the Status Register. The Control Reg-
i direction of data transfers. A high on the FUfi pin allows the ister is unchanged by a programmed Reset. It should be noted
i Xocessor to read the data supplied by the ACIA, a low allows that the programmed Reset is slightly different from the hard-
i a write to the ACIA. ware Reset (m); refer to the register description.

2-301
 R65C51 Asynchronous Communications Interface Adapter (ACIA
ACIA/MODEM INTERFACE Clear to Send (m)
The Cm input pin controls the transmitter operation. The enabl
Crystal Pins (XTLI, XTLO) state is with CTS low. The transmitter is automatically disable
These pins are normally directly connected to the parallel mode if CTS is high.
external crystal (1.8432 MHz) to derive the various baud rates.
Alternatively, an externally generated clock can drive the XTLI Data Terminal Ready (m)
pin, in which case the XTLO pin must float. XTLI is the input
This output pin indicates the status of the ACIA to the moderr
pin for the transmit clock.
A low on DTR indicates the ACIA is enabled, a high indicate:
it is disabled. The processor controls this pin via bit 0 of the
Transmit Data (TxD) Command Register.
The TxD output line transfers serial nonreturn-to-zero (NRZ)
data to the modem. The least significant bit (LSB) of the Transmit Data Set Ready (m)
Data Register is the first data bit transmitted and the rate of data
The m input pin indicates to the ACIA the status of the
transmission is determined by the baud rate selected or under modem. A low indicates the “ready” state and a high, “not.
control of an external clock. This selection is made by program- ready. ”
ming the Control Register.

Data Carrier Detect (DCb)

Receive Data (RxD)
The m input pin indicates to the ACIA the status of the carrier-
The RxD input line transfers serial NRZ data into the ACIA from detect output of the modem. A low indicates that the modem
‘the modem, LSB first. The receiver data rate is either the pro- carrier signal is present and a high, that it is not.
grammed baud rate or under the control of an externally gen-
erated receiver clock. The selection is made by programming TRANSMITTER AND RECEIVER OPERATION
the Control Register.
Continuous Data Transmit
Receive Clock (RxC) In the normal operating mode, the interrupt request output (m)
The RxC is a bi-directional pin which is either the receiver 16x signals when the ACIA is ready to accept the next data word to
clock input or the receiver 16x clock output. The latter mode be transmitted. This interrupt occurs at the beginning of the Start
results if the internal baud rate generator is selected for receiver Bit. When the processor reads the Status Register of the ACIA,
data clocking. the interrupt is cleared.

The processor must then identify that the Transmit Data Reg-
Request to Send (m)
ister is ready to be loaded and must then load it with the next
The m output pin controls the modem from the processor. data word. This must occur before the end of the Stop Bit, other-
The state of the RTS pin is determined by the contents of the wise a continuous “MARK” will be transmitted. Figure 5 shows
Command Register. the continuous Data Transmit timing relationship.

CHAR=n CHAR=n+l CHAR =n+2 CHAR =cn+3

PROCESSOR MUST
PROCESSOR /
\ LOAONEWOATA
INTERRUPT \ IN THIS TIME
PROCESSOR.REAOSSTATUS
(TRANSMIT OATA INTERVAL; OTHERWISE,
REGISTER, CAUSES IRO
REGISTER EMPTY) CONTINUOUS “MARK”
TO CLEAR
IS TRANSMITTED

Figure 5. Continuous Data Transmit

2-302
 Asynchronous Communications Interface Adapter (ACIA)
--- -

continuous Data Receive

5,mliar to the Continuous Data Trasit case, the normal read the data word before the next interrupt, otherwise the
Jperatlon of this mode is to assert IRQ when the ACIA has OVerWI condition occurs. Figure 6 shows the continuous Data
--led a full data word. This occurs at about ‘116 point through Receive Timing Relationship,
:m Stop Bit. The processor must read the Status Register and

CHAR # n CHAR *II*1 CHAR Sn+2 Cn*Rpn+3

1

PROCISSOR / \ \
INtERRUrT OCCURS/
PROCESSOR MUST READ I
ABOUT 0110 INTO \ \ RECEIVER DATA IN THIS
LAST STOP SIT.
PROCPSIOR READS STATUS TIME INTERVAL; OTblERWISE.
PARITY. OVERRUN.
REGISTER. CAUSES %8 OVERRUN OCCURS
AND FRAMING ERROR
TO CLEAR
ALSO, UPOATED

Figure6. Continuous Data Receive

Transmit Data Register Not Loaded by Processor

If the processor is unable to load the Transmit Data Register in When the processor finally loads new data, a Start Bit imme-
the allocated time, then the TxD line goes to the “MARK” con- diateiy occurs, the data word transmission is started, and another
dition until the data is loaded. IRQ interrupts continue to occur interrupt is initiated, signaling for the next data word. Figure 7
at the same rate as previously, except no data is transmitted. shows the timing relationship for this mode of operation.

CHAR#n CONTINUOUS “MARK” CHAR 5tn+l CklAR =n+2

TX0 FJz- ,m, -- ,mqq$5f

s:art So 8,

_ CHARACTER _
TIME
I
/
IRa
Iu , Ill

I
PROCESSOR
INTERRUPT
FOR DATA
REGISTER ’ ,&j
EMPTY
PROCESSOR NEW DATA, TRANShllSSION STARTS
READS NO DATA IS IMMEDIATELY AND INTERRUPT
STATUS TRANSMITTEO OCCURS, INDICATING TRANSMIT
REGISTER DATA REGISTER EMPTY

Flgure 7. TransmitDataRegisterNot Loadedby Processor

2-303
 R65C5 1 Asynchronous Communications Interface Adapter @CIA)

Effect of CTS on Transmitter

?f% is the Clear-to-Send signal generated by the modem. It is indicates that the Transmitter Data Register is not empty and
normally low (true state) but may go high in the event of some i% is not asserted. CTS is a transmit control line only, and has
modem problems. When this occurs, the TxD line goes to the no effect on the ACIA Receiver Operation. Figure 8 shows the
MARK” condition after the entire last character (including parity timing relationship for this mode of operation.
nd stop bit) have been transmitted. Bit 4 in the Status Register

CHAR tn CHAR=n+l CONTINUOUS “MARK”

TX0

IRQ
I I n-l m
f
IS NOT ASSERTED
AGAIN UNTIL m
NOT CLEAR-TO-SEND GOES ‘Ow
t

CLEAR-TO-SEND

Ffs GOES HIGH.

INDICATING MODEM
IS NOT READY TO
RE?%ibE DATA. TxO
GOES TO “MARK” CONDITION
AFTER COMPLETE CHARACTER
IS TRANSMITTED.

Figure 8. Effect of CTS on Transmitter

c Effect of Overrun on Receiver

lf the processor does not read the Receiver data Register in the but the Overrun status bit is set. Thus, the Data Register will
; allocated time, then, when the following interrupt occurs, the contain the last valid data word received and all following data
’ new data word is not transferred to the Receiver Data Register, is lost. Figure 9 shows the timing relationship for this mode.

CHAR=n CHARfin+ CHAR =n+2 CHAR In+3

Rx0 ~,~~,~I~lr~

PROCESSOR \
RECEIVER DATA REGISTER
INTERRUPT PROCESSOR
NOT UPDATED. BECAUSE
FOR RECEIVER
PROCESSOR DID NOT READ
DATA REGISTER
PREVIOUS DATA, OVERRUN
FULL REGISTER
BIT SET IN STATUS

I REGISTER

OVERRUN StT SET IN

STATUS REGISTER

Figure 9. Effect of Overrun on Receiver

RfjSCSf Asynchronous Communications Interface Adapter (ACIA)
-
EcnoMode Timing
p 2_w a,!oce.the TxD line re-transmits the data on the RxD
-. xoaved by ‘? of the bit time, as shown in Figure 10.

112 DATA BIT DELAY

Figure 10. Echo Mode Timing

Effect of CTS on Echo Mode Operation

‘n Echo Mode, the Receiver operation is unaffected by m, the Receiver Data Register is full in response to an R, so the
qowever. the Transmitter is affected when CTS goes high, i.e., processor has no way of knowing that the Transmitter has
:he TxD line immediately goes to a continuous “MARK” con- ceased to echo. See Figure 11 for the timing relationship of this
31t!on. In this case, however, the Status Request indicates that mode.

CHAR#tn CHAR#n+l CHARtin+ CHARtin+

Rx0 $‘l~~l:_I~,~,~

I I I
1

III I III I III

t NOTCLEAR-TO-SENO t

I
J
I I
CONTINUOUS “MARK” UNTIL Ffs GOES LOW
I I
/ I 1 ,
‘I I I \
1 r . . ..
TxO p Ist&=tl S,, 1 S, 1 1 ‘N 1 P

3 GOES
TO
“FALSE” CONDITION

NORMAL -
RECEIVER DATA
REGISTER FULL
INTERRUPTS

Figure 11. Effect of CTS on Echo Mode

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 a
R65CSl Asynchronous Communications Interface Adapter (ACM

Overrun in Echo Mode

If Overrun occurs in Echo Mode, the Receiver is affected the “MARK” condition until the first Start Bit after the Receiver Dar
same way as a normal overrun in Receive Mode. For the re- Register is read by the processor. Figure 12 shows the timir
transmitted data, when overrun occurs, the TxD line goes to the relationship for this mode.

/ i
) I
IRQ
\
t 1
\ nJ 1 RI
A
b

t
PROCESSOR PROCESSOR FINALLY TxO DATA
INTERRuFT READS RECEIVER RESUMES
FOR RECEIVER DATA REGISTER.
OATA REGISTER REAO RECEIVER LAST VALIO
CHARACTER (=nb
PROCESSOR
PROCESSOR
OVERRUNOCCURS INTERRUPT
REAOS
TxO GOES To FOR CHAR *JI
STATUS
“MARK” IN RECEIVER
REGISTER DATA REGISTER
CONDITION

Figure 12. Overrun in Echo Mode

Framing Error
Framing Error is caused by the absence of Stop Bit(s) on checked for the Framing Error. Subsequent data words a
received data. A Framing Error is indicated by the setting of bit tested for Framing Error separately, so the status bit will alwa
4 in the Status Register at the same time the Receiver Data reflect the last data word received. See Figure 13 for Framl
Register Full bit is set, also in the Status Register. In response Error timing relationship.
to m, generated by RDRF, the Status Register can also be

RX0
(EXPECTED)

RR0
(ACTUAL)

/
cl
MISSING
I
STOP
PROCESSOR
NOTES: 1. FRAMING ERROR DOES NOT SIT
INTERRUPT,
INHISIT RECEIVER OPERATION.
FRAMING
ERROR
2. IF NEXT DATA WORD IS OK.
BIT SET
FRAMING ERROR IS CLEARED.

Figure 13. Framing Error

fq6sCSf Asynchronous Communications Interface Adapter (ACIA)

gmt of on Receiver
:z J i
-ccem output Indicating the status of the carrier-fre- Once such a change of state occurs, subsequent transitions will
_;s;ec:.on clrcult of the modem. This line goes high for not cause interrupts or changes in the Status Register until the
, I=Q :! I-arr:er. Normally, when this occurs, the modem will first intermpt is serviced. When the Status Register is read by
s L.5, .- c:ng data some time later. The ACIA asserts IRQ the processor, the ACIA automatically checks the level of the
-be? 72
_ changes state and indicates this condition via DCD line, and if it has changed, another ii% occurs (see Figure
-.Js -9.*he Status Register. 14).

CONTINUOUS ‘MARK”

x
1 ’ III--T--

t t
NORMAL PROCESSOR
AS LONG AS NO INTERRUPT
PROCESSOR INTERRUPT
cicD IS HIGH. WILL OCCUR
FOR
INTSRRupT PROCESSOR NO FURTHER PROCESSOR HERE. SINCE
RECEIVER
INTERRUPT INTERRUPTS INTERRUPT RECEIVER IS NOT
DATA
FOR m FOR RECEIVER FOR DC0 ENAELEO UNTIL
GOING HIGH WILL OCCUR GOING LOW FIRST START BIT
DETECTED

Figure 14. Effect of DCD on Receiver

iming with 1% Stop Bits

‘s possible to select 1% Stop Bits, but this occurs only for trailing half-Stop Bit. Figure 15 shows the timing relationship for
.Dlt data words with no parity bit. In this case, the IRQ asserted this mode.
r Receiver Data Register Full occurs halfway through the

CHARtin CHARC~+I

1x1 m-1 m-L

t
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGHT THE 112
STOP BIT

Figure 15. Timing with 1 l/z Stop Bits

2-307
R65C51 Asynchronous Communications Interface Adapter (ACIA)

Transmit Continuous “BREAK”

This mode is selected via the ACIA Command Register and Note
causes the Transmitter to send continuous “BREAK” charac- If, while operating in the Transmit Continuous “BREAK”
ters, beginning with the next character transmitted. At least one mode, the CTS should go to a high, the TxD will be
full “BREAK” character will be transmitted, even if the processor overridden by the m and will go to continuous “MARK”
quickly re-programs the Command Register transmit mode. at the beginning of the next character transmitted after the
Later, when the Command Register is programmed back to CTS goes high.
normal transmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing rela-
tionship for this mode.

PERIOD DURING

I
WHICH PROCESSOR
-
- - SELECTS
CONTINUOUS POINT AT wnlcn ‘PROCESSOR’
“BREAK” MODE PROCESSOR INTERRUPT
NORMAL SELECTS TO LOAD
INTERRUPT NORMAL TRANSMIT
TRANSMIT DATA
MOGE

Figure 16. Transmit Continuous “BREAK”

Receive Continuous “BREAK”

In the event the modem transmits continuous “BREAK” char- shows the timing relationship for continuous “BREAt
acters, the ACIA will terminate receiving. Reception will resume characters.
only after a Stop Bit is encountered by the ACIA. Figure 17

-_ \
CONTINUOUS “BREAK”

RX0
rl
Sl
-_ I lsNl p lst~pli,,

I
1

I
PROCESSOR
PROCESSOR INTERRUPT
I WITH
/m-NO--j
MORE
INTERRUPTS
\NOlNTERRUPT
SINCE RECEIVER
DISABLE0 UNTIL
FIRST STOP BIT
NORMAL
I
RECEIVER
INTERRUPT
BREAK AND FRAMING ERROR SET. INTERFltJPl
FOR
RECEIVER EVEN PARITY CHECK WILL ALSO
DATA REGISTER GIVE A PARITYERROR BECAUSE
FULL AU ZEROS (CONTINUOUS BREAK)
REPRESENT EVEN PARITY.

Figure 17. Receive Continuous “BREAK”

 a

Asynchronous Communications Interface Adapter (ACIA)

~ATUS REGISTER OPERATION MISCELLANEOUS

*-_2 Z’ r-0 soecial funCtiOnS of the various status bits, there 1. If Echo Mode is selected, %!? goes low.
5 3 st;Sej:eo sequence for checking them. When an interrupt
2. If Bit 0 of Command Register (m) is 0 (disabled), then:
Lz_‘s. :“1 XIA should be interrogated, as follows:

a) All interrupts are disabled, including those caused by

za;c
_.. 5:&d-’ ‘s Register DCD and DSR transitions.
b) Transmitter is disabled immediately.
-- 3 ,-:era!:on automatically clears Bit 7 (m). Subsequent c) Receiver is disabled. but a character currently being
..lrs: crs cn DSR and DCD will cause another interrupt. received will be completed first.

sycK m (Bit 7) in the data read from the Status Register 3. Odd parity occurs when the sum of all the 1 bit? in the data
word (including the parity bit) is odd.
. not sel. :he interrupt source is not the ACIA.
4. In the receive mode, the received parity bit does not go into
:?eCK =c3 and DSR the Receiver Data Register, but generates parity error or no
parity error for the Status Register.
These must be compared to their previous levels, which must
lave oeen saved by the processor. If they are both 0 (modem 5. Transmitter and Receiver may be in full operation simulta-
on-line I and they are unchanged then the remaining bits neously. This is “full-duplex” mode.
qust be cnecked.
6. If the RxD line inadvertently goes low and then high right
Cfieck RDRF (Bit 3) after a Stop Bit, the ACIA does not interpret this as a Start
Bit, but samples the line again halfway into the bit to deter-
Check ior Receiver Data Register Full. mine if it is a true Start Bit or a false one. For false Start Bit
detection, the ACIA does not begin to receive data, instead,
Check Parity, Overrun, and Framing Error (Bits O-2) if the only a true Start Bit initiates receiver operation.
Receiver Data Register is full.
7. Precautions to consider with the crystal oscillator circuit:
Check TDRE (Bit 4)
a) The external crystal should be a “series” mode crystal.
b) The XTALI input may be used as an external clock input.
ChecK ior Transmitter Data Register Empty.
The unused pin (EXTALO) must be floating and may not
be used for any other function.
If none of the above conditions exist, then 5 must have
gone to the false (high) state.
8. m and DSR transitions, although causing immediate pro-
cessor interrupts, have no affect on transmitter operation.
Data will continue to be sent, unless the processor forces
transmitter to turn off. Since these are high-impedance inputs.
PROGRAM RESET OPERATION they must not be permitted to float (un-connected). If unused,
they must be terminated either to GND or Vcc.
A program reset occurs when the processor performs a write
speration ro the ACIA with RSO low and RSl high. The program
GENERATION OF NON-STANDARD BAUD RATES
‘eset operates somewhat different from the hardware reset
$RES pin) and is described as follows:
Divisors
The internal counter/divider circuit selects the appropriate divi-
1. Internal registers are not completely cleared. Check register sor for the crystal frequency by means of bits O-3 of the AClA
formats for the effect of a program reset on internal registers. Control Register, as shown in Table 2.

2. The DTR line goes high immediately. Generating Other Baud Rates
By using a different crystal, other baud rates mav be generated.
3. Receiver and transmitter interrupts are disabled immediately.
These can be determined by:
If IRQ ;s low when the reset occurs. rt stays low until ser-
viced. unless interrupt was caused by DCD or DSR transition.
Crystal Frequency
Baud Rate =
4. DCD and DSR interrupts are disabled immediately. If IRQ is Divisor
--
low and was caused by DCD or DSR. then it goes high, also
DCD and DSR status bits subsequently will follow the input Furthermore. it is possible to drive the ACIA with an offchIP
lines. although no interrupt will occur. oscillator to achieve other baud rates. In this case, XTALI (pin
6) must be the clock input and XTALO (pin 7) must be a no-
5. Overrun cleared. If set. connect.
 R65C51- Asynchronous Communications Interface Adapter (ACIA)

Table 2 Divisor Selection

Control Dlviaor Selected Baud Rete Genereted Baud Rete Generated
Regieter For The With 1.6432 Mljz with a crystal
Bite Internel Counter Crtstrl of Frequency (F)
3 2 1 0

I
0 0 0 0 I
I
No Divisor Selected
I
I
16 x External Clock
at
-. Pin RxC
..- I
16 x External Clock
at Pin RxC
1.6432 x lad F
/ 0 0 0 1 36.064 = 50
36,864 36,864
1.8432 x 106 F
0 0 1 0 24,576 = 75
24.576 24,576
i I I 1
I 1.8432 x 16 F
0 0
1
I I
1 1
I
I I
16,769
= 109.92
I
16,769
F

II
1.8432 x 106
0 1 0 0 13,704 = 134.51
13.704 13,704
k
1.8432 x 10 F
0 1 0 1 12,288 = 150
12,288 12,280
I
[ 1.8432 x l@ F
[ 0 1 1 0 6,144 f 300
1 6,144 6,144
t 1.8432 x 108 F
1 0 1 1 1 3,072 = 600
f 3,072 3,072
I 1.8432 x 106 F
i 10 0 0 1,536 = 1,200
1,536 1,536
1.6432 x 16 F
= 1,800
L 1,024 1.024
I I I
F

I
1.8432 x lO*
i 766 = 2.400
1 l0l0 1 I 768 I 768

ItIlOl1I 1 512
I 1.8432 x 10’
= 3,600
F

I 512 , 512
I
i I 1.8432 x 106 F
= 4,800
384 384
I 1.8432 x 108 F
1 1 0 1 256 = 7,200

!D 1.8432
256x 106 256
F
i 1 1 1 0 192 = 9,600
E 192 192
1.8432 x loa F

11
1

1 1 1 1 96 96 = 19,200 I 96
1

1
 Asynchronous Communications Interface Adapter (ACIA)
&@,osflC LOOP-BACK OPERATING MODES

ii g-3 -ec =
XK diagram for a system incorporating an ACIA loop-back operation. In this way, the processor can easily per-
i) $.m- ? =$Lre 18. form local loop-back diagnostic testing.

il _~ x cesiraole to include in the system a facility for “loop-

Remote loop-back does not require this circuitry, so LLB must
.ss;,rg. =f which there are two kinds:
:- be set low. However, the processor must select the following:

_-1. ,=s-Back
Control Register bit 4 must be 1, so that the transmitter clock
equals the receiver clock.
: _-~_~acK Yom the point of view of the processor. In this
_le :r,e ,Modem and Data Link must be effectively discon-
Command Register bit 4 must be 1 to select Echo Mode. ,
--L::ec ?,?a :he ACIA transmitter connected back to its own
.yYtr~r ~3 fhat the processor can perform diagnostic checks c
Command Register bits 3 and 2 must be 1 and 0, respec-
-- :l.e system. excluding the actual data channel. L
tively to disable IRQ interrupt to transmitter.

‘.- +To:e ioop-Back

Command Register bit 1 must be 0 to disable IRQ interrupt
for receiver.
,203-DaCK !rom the point of view of the Data Link and
’ t.@cem.In rhis case, the processor, itself, is disconnected
In this way, the system re-transmits received data without any
gc al received data is immediately Tetransmitted, so the
effect on the local system.
’ sys;em on rhe other end of the Data Link may operate inde-
xendent of !he local system. ,

!“?.e XIA does not contain automatic loop-back operating

;-zces. 3ut they may be implemented with the addition of a MICRO-
ji,-a:l amount of external circuitry. Figure 19 indicates the nec- PROCESSOR v
j!ssarl; logic to be used with the ACIA. The LLB line is the pos-
5.
:* ve-true signal to enable local loop-back operation. Essentially,
‘__3 = nigh does the following:

‘Disables outputs TxD, fi, and RTS (to Modem).

1. Disables inputs RxD, z, CTS, DSR (from Modem).

!. Connects transmitter outputs to respective receiver inputs

w I/O MODEM
II.e.. TxD to RxD, DTR to m, ATS to m). r-l
I I
4
TO DATA LINK
L
:- LB may be tied to a peripheral control pin (from an R65C21
i Figure 18. Simplified System Diagram
;: r R65C24. for example) to provide processor control of local
f_
I
j I A6551
_-__ I
I -- ---
Rx0 DC0 CTS DSR

*- MODEM
TxD
SEL 1Y
2Y DTR
I, STB 3Y RfS
1
1: 4Y -
74157
+5
i NOTES: 1. HIGH ON LLB SELECTS LOCAL LOOP-BACK MODE.
2. HIGH ON 74157 SELECT INPUT GATES “B” INPUTS
- 48 4A- TO “Y” OUTPUTS; LOW GATES “A” TO “Y”.
1 I

Figure 19. Loop-Back Circuit Schematic

3_111
R65C51 Asynchronous Communications Interface Adapter (AC

READ TIMING DIAGRAM

I kzCY
Timing diagrams for transmit with external clock, receive with I- tCH __i
XTLI
external clock, and m generation are shown in Figures 20, 21
(TRANSMIT
and 22, respectively. The corresponding timing characteristics CLOCK INPUT) j---i r
are listed in Table 3.
,c- tCL--
Table 3. Transmit/Receive Characteristics tDD -

TxD ‘K-

NOTE: TxD RATE IS 1116 TxC RATE

Figure 20. Transmit Timing with External Clock

Transmit/Receive fcli 175 - 175 - ns
Clock High Time
kCY
Transmit/ Receive tCL 175 - 175 - ns - -.tcH --a
Clock Low Time
XTLI to TxD t0D - 500 - 500 ns RxC
Propagation Delay (INPUT)
RTS Propagation l fmy I - l 500 I - I 500 I ns 1 IF--- tcL---
Delay
NOTE: Rx0 RATE IS 1116 RxC RATE
IRQ Propagation tlR0 - 500 - 500 ns
Delay (Clear)
Figure 21. Receive External Clock Timing
Notes:
[tR. tF = 10 to 30 ns)
1
‘The baud rate with external clocking is: B&d Rate =
16 x tccv

*tlRQ’
IRQ
(CLEAR)

Figure 22. Interrupt and Output Timing

f irr;sCSl Asynchronous

CHARACTERISTICS
1 MHz 2 MHz
parameter Symbol Mln Max Min Max Unit
22 :,c:e Yme
.
bYC 1000 - 500 ns

:2 -‘,.se .Vldth tc 400 200 ns

- - -
a:,~ Set-Up Time tACW 120 60 ns
:c:.5~s Aold Time bAl+ 0 - 0 - ns
a*,? +I-tip Time twcw 120 - 60 - nS

= a.5 -Oq Time kwn 0 0 - nS

~3~3 3~s Set-Up Time tclcw 120 60 ns

zala 3~s Hold Time 4+W 20 - 10 - ns
aeac Access Time (Valid Data) ’ km - 200 - 100 llS

leaa rold Time b!R 20 - 10 - flS

BUS %rfve Time (Invalid Data) (CDA 40 20 ns

Notes:
* v-z = 5.ov iwo.
2. T, = T, to T,.
3. t= ana tr = 10 to 30 ns.

#- VIH

VIH
CSO,B,, RSo, AS,
VIL

I
/
VIL
tDCW _!_--- tHW--.+i
t-
VIH
DATA BUS
VIL

Figure 23. Write Timing Diagram

/I
I--WCR- “IL
I
It---- tCQR-’

DATA BUS

Figure 24. Read Timing Characteristics

2-313
r
f
”
q

i; R65C51 Asynchronous Communications Interface Adapter (ACIA

ABSOLUTE MAXIMUM RATINGS’ ‘NOTE: Stresses above those listed may cause permaner
damage to the device. This is a stress rating only and functionc
operation of the device at these or any other conditions abov
those indicated in other sections of this document is not implies
Exposure to absolute maximum rating conditions for extende
periods may affect device reliability.

OPERATING CONDITIONS

DC CHARACTERISTICS
(Vcc = 5.OV f5%, Vss = 0, TA = TL to T”, unless otherwise noted)

I Parameter Symbol Mln TYP Max Unit Test Conditlons

I
j Input High Voltage VIH 2.0 - Vcc V

: Input Low Voltage VI, -0.3 - +0.8 V

! Input Leakage Current: IIN fl f2.5 fi v,, = ov to vcc

I 02, Rm. !?i%. CSO. a, RSO, RSI. i5fs, RxD, bFB, DSR V,, = 5.25V
Input Leakage Current (Three State Off) ITSI
- it2 f10 lLA V,, = 0.4V to 2.4V
: DO-07 V,, = 5.25V
j Output High Voltage: Von 2.4 - - V v,, = 4.75v
--
DO-07, TxD. RxC. RTS. DTR 1 ILOAD= -loo d
1 Output Low Voltage:
00-07. TxD. RxC. m. m. TBd
Output High Current (Sourcing): ‘OH -200 1 -400 - I /.A VOH = 2.4V
00-07. TxD, RxC, m. m
Output Low Current (Sinking):
---
DO-07. TxD, RxC, RTS. DTR. IRQ IOL 1.6 - - mA v,, = 0.4v

’ Output Leakage Current (off state): IRQ IOFF

- 10 d VOuT = 5.0V
Power Dissipation PO - 7 10 mW/MHz
Input Capacitance vcc = 5.ov
; All except 02 CCLK
- 20 PF vlN = ov

1 02 GIN
- 10 PF f = 2 MHz
T, 3: 25%
Output Capacitance COUT
- 10 PF
Notes:
1. All units are direct current (dc) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Tvolcal values are shown for Vrr = 5.OV and TA = 25°C.