UNIT-4

MICROCONTROLLER FUNDAMENTALS
FOR BASIC PROGRAMMING
I/O pin Multiplexing

– independently programmable individual i/o’s

– Any combination of input or output

– some devices may include additional port interrupts

– individually configurable pull up and pull down resistors

• Most GPIO ports contain 8 i/o lines

• each i/o line is individually configurable for pull up and pull down resistors.
 I/o Pull up/down

Switch̲ State Input ̲ Pin̲ State Switch̲ State Input ̲ Pin̲ State

Open(Not Pressed) Undefined Open(Not Pressed) Undefined

Closed (Pressed) High (Equal to VCC) Closed (Pressed) Low (Equal to GND)
 Switch̲ State Input ̲ Pin̲ State Switch̲ State Input ̲ Pin̲ State

Open(Not Pressed) Low Open(Not Pressed) High

Closed (Pressed) High (Equal to VCC) Closed (Pressed) Low (Equal to GND)
• By using a pull-up/pull-down resistor , the input always has a default
logic state, either “1” or “0” i.e high or low, depending on the position
of the switch, thus achieving the proper output function and
therefore preventing the input from floating.
GPIO Control:
General Purpose Input/output (GPIO) refers to pins on a board which are connected to
the microcontroller in a special configuration.
 GPIOs are extensively used in embedded systems designs to interface the microcontroller
to external sensors and driver circuits.
 GPIOs are used in devices like SoC, PLDs, and FPGAs, which inherit problems of pin scarcity.
 They are used in multifunction chips like audio codecs and video cards for connectivity
 The GPIO pins are flexibly multiplexed.
 5-V-tolerant in input configuration
 Tiva GPIOs

Ports A-F accessed through the Advanced Peripheral Bus (APB)

 I/O Pins in Tiva Microcontroller

I/O pins on Tiva  microcontrollers have a wide range of alternative functions:

•  UART                           Universal asynchronous receiver/transmitter
•  SSI                                Synchronous serial interface
•  I2C                                Inter-integrated circuit
•  Timer                            Periodic interrupts, input capture, and output compare
•  PWM                            Pulse width modulation
•  ADC                              Analog to digital converter, measure analog signals
•  Analog Comparator      Compare two analog signals
•  QEI                              Quadrature encoder interface
•  USB                              Universal serial bus
•  Ethernet                        High-speed network
•  CAN                             Controller area network
• UART - used for serial communication. It is asynchronous and allows for simultaneous
communication in both directions.
• SSI or SPI - It is used to interface medium-speed I/O devices.
• I2C - used to interface low speed peripheral devices.
• PWM - outputs will be used to apply variable power to motor interfaces.
• ADC -  will be used to measure the amplitude of analog signals and will be important
in data acquisition systems.
• QEI - used to interface a brushless DC motor. 
• USB is a high-speed serial communication channel.
• Ethernet port can be used to bridge the microcontroller to the Internet or a LAN.
• CAN creates a high-speed communication channel between microcontrollers
Memory mapped peripherals:

Addressing I/O devices:

• Memory mapped I/O (MMIO) : Same address bus to address both memory and
peripherals.
• Port mapped I/O (PMIO): Peripheral devices possess a separate address bus from
general memory devices.
Programming system registers:

Direction Register :
GPIO Direction (GPIODIR) register as an input or output.
• When the data direction bit=0  input
• When the data direction bit =1  Output 

Data Register :
GPIODATA register is the data register
 Watchdog Timer
• A watchdog timer is a hardware timing device that triggers a system reset if the main
program, due to some fault condition, such as a hang, neglects to regularly service the
watchdog.
• System restart or reset

– for S/W problem and

• Interval Timer

– Generate interrupts
Watchdog Timer:

• A watchdog timer counter enters a counter lapse or timeout after it reaches certain
count.
• Normal operation: the program running the system continuously resets the watchdog
timer.
• When the system enters an infinite loop or stops responding, it fails to reset the
watchdog timer.
• The TM4C123GH6PM microcontroller has two Watchdog Timer modules:
• Watchdog Timer 0 - Clocked by the system clock
• Watchdog Timer 1 - Clocked by the PIOSC
Need for Low Power Microcontroller
It is imperative for an embedded design to be low on its power consumption. Most
embedded systems and devices run on battery. Power demands are increasing rapidly, but
battery capacity cannot keep up with its pace. Therefore, a microcontroller which inherently
consumes very less power is always encouraging. However, embedded systems engineers
usually need to optimize between power and performance. Power and performance are
inversely proportional to each other.
Hibernation Module:
• Hibernation Module manages to remove and restore power
• reduces system power consumption.
• When the processor and peripherals are idle, power can be completely removed if the
Hibernation module is only the one powered.

Features of Hibernation (HiB) Module :

• (i) RTC to be used for wake events
• (ii) A battery backed SRAM for storing and restoring processor state.

The Hibernation module of TM4C provides two mechanisms for power control:
1. Uses internal switches to control power to the Cortex-M4F.
2. controls the power to the microcontroller with a control signal (HIB) that signals an external
voltage regulator to turn on or off.

Hibernate mode can be entered through one of two ways:

• The user initiates hibernation by setting the HIBREQ bit in the Hibernation Control (HIBCTL)
register.
• Power is arbitrarily removed from VDD while a valid VBAT is applied
Active Vs Standby Current Consumption:

TM4C123GH6PM operates in six power modes:

1. Run 2. Sleep 3. Deep Sleep 4. Hibernate with VDD3ON
5. Hibernate with RTC 6. Hibernate without RTC.
Ex: consider that the device is operating at 40 MHz system clock with PLL.
Active Vs Standby Current Consumption:

Fig:
Interrupts
Interrupts
 Types of interrupts
1. Software driven interrupts (SWI) :  
• SWIs are generated from within a currently executing program.
• A SWI will call a subroutine that allows a program to access certain lower level service.

2. Hardware driven interrupts (HWI):

• HWIs are signals from a device to the microprocessor.
• The device sets an interrupt line in the control bus high.
• Microprocessors have two types of hardware interrupts
 Non-maskable interrupt (NMI) ---------- very high priority
 Interrupt request (INTR).
 Interrupt Vector Table:

• When an interrupt occurs, the microprocessor runs an associated ISR.

• IRQ is an input signal to the microprocessor.
• Pushes the PC register onto the stack and load address of the ISR onto the PC
register.
• Executes the ISR.
• Easy to manage the ISRs if there is a lookup table where address locations of all
ISRs are listed.
• This lookup table is called Interrupt vector table.
• There are 256 interrupts.
• first 15 interrupts, INT0 to INT15 are called the predefined interrupts.
• Interrupt vector table is an on-chip module, called as Nested Vector Interrupt
Controller (NVIC).
Interrupt Vector Table:
Predefined Interrupts (INT0-INT15)
RESET
All ARM devices have a RESET pin which is invoked on device power-up or in case of warm reset.This
exception is a special exception and has the highest priority. On the assertion of Reset signal, the execution
stops immediately. When the Reset signal stops, execution starts from the address provided by the Reset
entry in the vector table i.e. 0x0000.0004. Hereby, to run a program on Reset, it is necessary to place the
program in 0x0000.0004 memory address.
NMI
In the ARM microcontroller, some pins are associated with hardware interrupts. They are often called IRQs
(interrupt request) and NMI (non-maskable interrupt). IRQ can be controlled by software masking and
unmasking. Unlike IRQ, NMI cannot be masked by software. This is why I is named as nonmaskable
interrupt. As shown in Table 2.9, "INT 02" in ARM Cortex-M is used only for NMI. On activation of NMI, the
microcontroller load memory location 0x0000008 to program counter.
Hard Fault
All the classes of fault corresponding to a fault handler cannot be activated. This may be a result of the
fault handler being disabled or masked.
• Memory Management Fault
• It is caused by a memory protection unit violation. The violation can be caused by attempting to write
• into a read only memory. An instruction fetch is invalid when it is fetched from non-executable region
• of memory. In an ARM microcontroller with an on-chip MMU, the page fault can also be mapped into
• the memory management fault.
• Bus Fault
• A bus fault is an exception that arises due to a memory-related fault for an instruction or data memory
• transaction, such as a pre-fetch fault or a memory access fault. This fault can be enabled or disabled.
• Usage Fault
• Exception that occurs due to a fault associated with instruction execution. This includes undefined
• instruction, illegal unaligned access, invalid state on instruction execution, or an error on exception
• return may termed as usage fault. An unaligned address of a word or half-word memory access or
• division by zero can cause a usage fault.
• SVCall
A supervisor call (SVC) is an exception that is activated by the SVC instruction. In an operating system,
applications can use SVC instructions to contact OS kernel functions and device drivers. This is a software
interrupt since it was raised from software, and not from a Hardware or peripheral exception.
• PendSV
PendSV is pendable service call and interrupt-driven request for system-level service. PendSV is used for
framework switching when no other exception is active. The Interrupt Control and State (INTCTRL) register is used
to trigger PendSV. The PendSV is an interrupt and can wait until NVIC has time to service it when other urgent
higher priority interrupts are being taken care.
• SysTick
A SysTick exception is generated by the system timer when it reaches zero and is enabled to generate an
interrupt. The software can also produce a SysTick exception using the Interrupt Control and State (INTCTRL)
register.
• User Interrupts
This interrupt is an exception signaled either by a peripheral or by a software request and fed through the NVIC
based on their priority. All interrupts are asynchronous to instruction execution. In the system, peripherals use
interrupts to communicate with the processor. An ISR can be also propelled as a result of an event at the
peripheral devices. This may include timer timeout or completion of analog-to-digital converter (ADC) conversion.
Each peripheral device has a group of special function registers that must be used to access the device for
configuration. For a given peripheral interrupt to take effect, the interrupt for that peripheral must be enabled.
 Interrupt programming
• To understand how exceptions/interrupts work
void Timer0IntHandler(void)
#include <stdint.h>
int main(void) {
{ uint32_t ui32Period; // Clear the timer interrupt
SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN); TimerIntClear(TIMER0_BASE,TIMER_TIMA_TIMEOU);
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
// Read the current state of the GPIO pin and
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
// write back the opposite state
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC); if(GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_2))
ui32Period = (SysCtlClockGet() / 10) / 2; {
TimerLoadSet(TIMER0_BASE, TIMER_A, ui32Period -1); GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|
IntEnable(INT_TIMER0A); GPIO_PIN_2|GPIO_PIN_3, 0);
TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT); }
IntMasterEnable();
TimerEnable(TIMER0_BASE, TIMER_A);
while(1)
{
}
}
Basic Timers/Counters:
•Generate fixed-period time events;
•Allow a periodic wakeup from sleep mode;
•Count transitional signal edges;
•Replace delay loops with timer calls to allow the CPU to sleep, consuming much less power.
Basic Timer provides :
–Clock for the LCD module
–Periodic Interrupts
–Clock signal to drive the Real-Time Clock
–Suitable for a RTC implementation;
–Basic interval timer;
–Simple interrupt capability.
Pre-scaler:
• Takes the basic timer clock frequency as an input and divides it by some value depending
upon the circuit requirements before feeding it to the timer
• Pre-scaler is used to set the clock rate of the timer.
• This provides a flexibility in resolution (high clock rate implies better resolution) and range
(high clock rate causes quicker overflow of timer).
Timer Register:
• N-bit up-counter
• The regular pulses which drive the timer, are called “ticks”.
Capture Registers:
• Used to capture a “snapshot” of the timer at the instant when the event occurs.
• Capture registers can be used to time intervals between pulses or input signals, to determine
the high and low times of input signals.
Compare/Match Registers:
• holds a value against which the current timer value is routinely compared and shoots to
trigger an event when the value in two registers matches.
 Real time clock (RTC)
• Provides real time clock and calender

RTC_A features include:

• Configurable for real-time clock with calendar function or general-purpose

counter

• Provides seconds, minutes, hours, day of week, day of month, month, and year in real-time clock with
calendar function

• Interrupt capability

• Selectable BCD or binary format in real-time clock mode

• Programmable alarms in real-time clock mode

• Calibration logic for time offset correction in real-time clock mode

 PWM Module
• A rectangular digital waveform
used to control an analog variable
• PWM is employed in a wide variety
of applications
The control block determines the
polarity of the PWM signals
TM4C controller contains two
PWM modules, each with four
generator blocks that generate
eight independent PWM signals
PWM Timer:
Timer PWM generator runs in two modes:
• Count-Down mode - the timer counts from the load value to zero, goes back to the load
value, and continues counting down.
• Count-Up/Down mode - the timer counts from zero up to the load value, back down to
zero, back up to the load value, and so on.
The timers output three signals in the PWM generation process:
• "dir" - the direction signal,
• "zero" - a single-clock-cycle-width High pulse when the counter is zero,
• "load" - a single-clock-cycle-width High pulse when the counter is equal to the load value.
PWM Comparators:
• PWM generator has two comparators
• when either comparator matches the counter, they output a single-
clock-cycle-width High pulse, labeled "cmpA" and "cmpB“
• When in Count-Up/Down mode, these comparators match both when
counting up and when counting down, and thus are qualified by the
counter direction signal.
• If either comparator match value is greater than the counter load
value, then that comparator never outputs a High pulse.
PWM Signal Generator:
• Each PWM generator takes the load, zero,
cmpA, and cmpB pulses and generates two
internal PWM signals, pwmA and pwmB.
• In Count-Down mode, there are four events
that can affect these signals: zero, load,
match A down, and match B down.
• In Count-Up/Down mode, there are six
events that can affect these signals: zero,
load, match A down, match A up, match B
down, and match B up.
• The match A or match B events are ignored
when they coincide with the zero or load
events.
• If the match A and match B events coincide,
the first signal, pwmA, is generated based
only on the match A event, and the second
signal, pwmB, is generated based only on
the match B event.
Dead-Band Generator

• The pwmA and pwmB signals produced by each PWM generator are passed to the dead-
band generator.
• If disabled, the PWM signals simply pass through to the pwmA' and pwmB' signals
unmodified.
• If enabled, the pwmB signal is lost and two PWM signals are generated based on the
pwmA signal.
• The first output PWM signal, pwmA' is the pwmA signal with the rising edge delayed by a
programmable amount.
• The second output PWM signal, pwmB', is the inversion of the pwmA signal with a
programmable delay added between the falling edge of the pwmA signal and the rising
edge of the pwmB' signal.
• The resulting signals are a pair of active high signals where one is always high, except for
a programmable amount of time at transitions where both are low.
• These signals are therefore suitable for driving a half-H bridge, with the dead-band
delays preventing shoot-through current from damaging the power electronics.
 Quadrature Encoder Interface (QEI):

• A quadrature encoder or a 2-channel

incremental encoder, converts linear
displacement into a pulse signal.
• By monitoring both the number of
pulses and the relative phase of the
two signals, you can track the position,
direction of rotation, and speed.
• In addition, a third channel, or index
signal, can be used to reset the
position counter.
• A classic quadrature encoder has a
slotted wheel like structure, to which a
shaft of the motor is attached and a
detector module that captures the
movement of slots in the wheel.
Interfacing QEI using Tiva TM4C123GH6PM
• The TM4C123GH6PM microcontroller includes two quadrature
encoder interface (QEI) modules.
• Each QEI module interprets the code produced by a quadrature
encoder wheel to integrate position over time and determine
direction of rotation.
• In addition, it can capture a running estimate of the velocity of the
encoder wheel.