Microprocessors - III

Yashar Hajiyev
Microprocessor Structural Organization
(architecture)
 General

OPCODE  part of instruction that specifies the operation to be performed is called the
operation code or Opcode;
OPERANDdata on which the operation is to be performed is called as an Operand.
General
The output of each register is connected to two multiplexers (MUX) to form the
two buses A and B.
The selection lines in each multiplexer select one register or the input data for the
particular bus.
The control must provide binary selection variables to the following selector
inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition A + B.
4. Decoder destination selector (SELD): to transfer the content of the output bus
into Rl.

Control Word
There are 14 binary selection inputs in the unit, and their combined value
specifies a control word.
The encoding of the register selections is specified in following Table.
The 3-bit binary code listed in the first column of the table specifies the binary
code for each of the three fields.
The register selected by fields SELA, SELB, and SELD is the one whose
decimal number is equivalent to the binary number
in the code.
The ALU provides arithmetic and logic
operations. In addition, the CPU must
provide shift
operations. The shifter may be placed in
the input of the ALU to provide a preshift
capability,
or at the output of the ALU to provide
postshifting capability.
 4 Instruction types 
- Data processing → instructions for computational capabilities for processing numeric data
→ performed in MP registers;
- Data instructions → to transfer programs and data into memory and the results to
user;
- Control instructions → to test the value of data word or status of computation storage
→ instructions for moving data between memory and registers;
- Data exchange through I/O ports;

7 Groups of Instruction commands 

► Moving data → between main memory and registers;
► Executing arithmetical and logical operations ;
► Regulation of conducting current programs;
► Relation with sub-programs ;
► Shift data in registers, clean up of registers, formatting of additional
codes;
► I/O instructions;
► Special instructions;

4 types of operands  Addresses; Numbers ( Integer or fixed point; floating

point; Decimal ); Floating point;
 General

Assembly language -- the native language of a microprocessor.

Microprocessor executes a collection of machine instructions that tell
the processor what to do.
Based on the instructions, a MP three basic things:
1.Using its ALU (Arithmetic/Logic Unit), a MP can perform mathematical operations

―addition, subtraction, multiplication and division. MPs contain complete floating point
processors to perform operations on large floating point numbers.

2. MP can move data from one memory location to another.

3.MPcan make decisions and jump to new set of instructions based on those decisions.
 Instruction Format
Memory addressing is simple. 
A 16 bit address is either built into the instruction, or taken from the HL Register.
The instruction set is simple and uniform making it easy to learn.
The OPCODES are all 8 bits long and these may contain Register fields and the
OPCODE may be followed by an 8 or 16 bit immediate value or 16 bit address. 

OPCODE+REGISTER
 <-------------------------- Byte --------------------->

OPCODE+X X X (operand)
 <------------------------- Byte --------------------->
<------------ 8 or 16 ----------->
 
Contents of all Registers including Accumulator and memory location pointed to
by (HL) may be incremented, decremented or loaded with an immediate value. 
 Instruction Format
 
All combinations of Register, Accumulator and Memory pointed to by (HL) may
be moved to another Register or Accumulator or Memory pointed to by (HL). 

The following arithmetic operations may take place between any Register, Memory
pointed to by (HL) or an immediate value as source and the Accumulator as
destination  -  ADD, SUB, AND, OR, XOR and Compare.

Register pairs (HL) can be incremented or decrement as a 16 bit value,  or a 16 bit

immediate value may be added to the HL pair which make 64K address
manipulation easy.
Rotate operations via Carry flag but no specific bit handling instructions.

There is a 16 bit Stack Pointer (SP).

Jumps, Calls and returns all have conditional versions (ie Jump on carry set) and
all jumps are to absolute 16 bit addresses. 

The Register pairs may be pushed to or popped from the stack.

 Instruction Format
Instruction is represented by a sequence of bits within computer.
Instruction is divided into group of bits called field.
The way of instruction is expressed is known as instruction format.
It is usually represented in form of rectangular box. The instruction
format may be of the following types.

Variable Instruction Formats

These are the instruction formats in which the instruction length varies on the basis of
opcode & address specifiers.
For Example, some instructions vary between 1 and 53 bytes while X86 instruction
vary between 1 and 17 bytes.
 Instruction Format
Variable Instruction Formats
These are the instruction formats in which the instruction length varies on the basis of
opcode & address specifiers.
For Example, VAX instruction vary between 1 and 53 bytes while X86 instruction
vary between 1 and 17 bytes.

Fixed Instruction Formats

In this type of instruction format, all instruction are same size.
ADVANTAGE  they are easy to decode & pipeline;
DRAWBACK  They don't have as good code density.
 Instruction Format
Hybrid Instruction Formats
In this type of instruction formats, we have multiple format length specified by opcode.
For example, IBM 360/70, MIPS 16, Thumb.

ADVANTAGE These compromise between code density & instruction of these type
are very easy to decode.
Addressing Modes
Addressing Modes
 Segment: Offset scheme in Memory
 When largest register in CPU was only 16-bits long → it could address directly only 65,536 bytes (64 KB) of memory.
If combine two registers into high and low pair of 32-bits → to reference up to 4 GB of memory in linear fashion.

Segment: Offset scheme

  
 Addressing Modes
Segment:Offset scheme in Memory
 Addressing Modes
Segment: Offset scheme in Memory
 Addressing Modes
Segment: Offset scheme in Memory
 Addressing Modes

Absolute  Memory Location  = (Segment value * 16) + Offset value

Absolute or Linear address for Segment: Offset pair, F000:FFFD can be computed

F0000 + FFFD ------ FFFFD or 1,048,573(decimal)

Another example: 923F:E2FF

923F0 + E2FF ------ A06EF or 657,135(decimal)
 Addressing Modes
Addressing Modes
Addressing mode provide different ways for access an address to given data to a
processor. Operated data is stored in the memory location, each instruction required
certain data on which it has operate.
Various techniques to specify address of data → called Addressing Modes.

►Direct addressing mode - address of operand is given in instruction and data

is available in memory location which is provided in instruction. We will move this
data in desired location.

►Indirect addressing mode - instruction specifies register which contain address of

operand. Both internal RAM and external RAM can be access via indirect addressing
mode.

►Immediate addressing mode - direct data is given in operand which move

the data in accumulator. It is very fast.

► Relative addressing mode - effective address is determined by index mode

by using program counter in stead of general purpose processor register.

► Index addressing mode - effective address of operand is generated by adding

a content value to the contents of the register.
Addressing Modes
Addressing Modes
Addressing Modes
Addressing Modes PIC
Addressing Modes
 Addressing Modes
6. The 8085 Addressing Modes
The instructions MOV B, A or MVI A, 82H
to copy data from source into destination.
Source can be register, an input port, or an 8-bit number (00H to FFH).
Destination can be a register or an output port. The sources and destination are
operands.
Various formats for specifying operands are called ADDRESSING MODES.
For 8085:
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
Immediate addressing
Data is present in the instruction. Load the immediate data to
the destination provided.
Example: MVI R,data
Register addressing
Data is provided through the registers.
Example: MOV Rd, Rs
 Addressing Modes
Direct Addressing →instruction supplies all exact memory address.

Instruction: "Load contents of memory address 1F2A into accumulator“

1F2A is direct address.

 Addressing Modes
Register Pair Addressing → memory address is specified by contents
of register pair.
For all 8080 instructions → H and L registers are used.
H register contains big 8 bits of referenced address, and the L register→
least significant 8 bits.

Two instructions of Intel-8080 use either Band C registers or the D and E

registers to address memory.

A one byte instruction which will load the accumulator with contents of memory
byte 1F2A would appear as follows
 Addressing Modes

6. The 8085 Addressing Modes

Direct addressing
Used to accept data from outside devices to store in accumulator or
send data stored in the accumulator to the outside device.
Accept the data from the port 00H and store them into accumulator or
Send the data from the accumulator to the port 01H.
Example: IN 00H or OUT 01H

Indirect Addressing
This means that Effective Address is calculated by processor and
the contents of address (and one following) is used to form a second address.
The second address is where the data is stored.
Note that this requires several memory accesses; two accesses to retrieve the 16-bit
address and a further access (or accesses).
to retrieve the data which is to be loaded into the register.
 Addressing Modes

The 8085 Addressing Modes

The instructions MOV B, A or MVI A, 82H are to copy data from a
source into a destination.

In these instructions the source can be a register, an input port, or an 8-bit

number (00H to FFH). Similarly, a destination can be a register or an output port.

The sources and destination are operands.

The various formats for specifying operands are

called the ADDRESSING MODES.

For 8085, they are:

1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
 Addressing Modes
The 8085 Addressing Modes
Immediate addressing
Data is present in instruction. Load the immediate data to destination provided.
Example: MVI R, data.

Register addressing
Data is provided through the registers.
Example: MOV Rd, Rs

Direct addressing
Used to accept data from outside devices to store in accumulator or send the
data stored in accumulator to outside device.
Accept the data from the port 00H and store them into accumulator or
send the data from accumulator to port 01H.
Example: IN 00H or OUT 01H

Indirect Addressing
Effective Address is calculated by processor. And contents of address
(and one following) is used to form a second address.
The second address  is where the data is stored.
This requires several memory accesses; → two accesses to retrieve the 16-bit address and a
further access (or accesses) to retrieve data which is to be loaded into the register.
 Instruction Set Classification
Instruction  is a binary pattern →designed inside a microprocessor
to perform a specific function.

The entire group of instructions  called Instruction Set,

determines what functions the microprocessor can perform.
Instruction classified into five functional categories:
► data transfer (copy) operations;
► arithmetic operations;
► logical operations;
► branching operations;
► machine-control operations;
 Data Transfer (copy) Operations

Instructions  to copy data from Source (initial location)

to Destination (final location);
Data retained without any modification upon transfer (copy)
 Instructions on Arithmetic Operations
Instructions  to perform arithmetic operations 
♦addition, ♦subtraction, ♦increment, and ♦decrement;
Addition 
8-bit number, or contents of register or contents of a memory location can
be added to contents of accumulator, and the sum is stored in accumulator.
No two other 8-bit registers can be added directly (e.g., contents of
register B cannot be added directly to contents of register C).
The instruction DAD is an exception;→ it adds 16-bit data directly in register pairs.

Subtraction 
8-bit number, or contents of register, or contents of memory location can
be subtracted from contents of accumulator; and results are stored in
accumulator.
The subtraction is performed in 2's compliment, and the results if negative,
are expressed in 2's complement.
No two other registers can be subtracted directly.
 Instructions on Arithmetic Operations
Instructions  to perform arithmetic operations 
♦addition, ♦subtraction
examples
Mnemoni Opcode Numbe Format /Addressing Symbols Indicators
c r of
bytes
addition

ADI C6 h Two Opcode + Operand (A)←(A)+(2nd byte) Z, CY

(immediate)
bytes
ADD H 84 h One Opcode (A)←(A) + (H) Z, CY
(register)
byte
ADD M 86 h One Opcode (A)←(A) + ((H) (L)) Z, CY
(indirect)
byte

subtractio
n
SUB L 95 h Opcode (A)←(A) – (L) Z, CY
(register)

SUB M 96 h Opcode (A)←(A) - ((H) (L)) Z, CY

(indirect)
 Instructions on Arithmetic Operations
Instructions  to perform arithmetic operations 
♦increment, &, ♦decrement;
Increment/Decrement 
The 8-bit contents of register or a memory location can
be incremented or decrement by 1.
Similarly, the 16-bit contents of register pair (such as BC) can
be incremented or decrement by 1.
Increment/decrement operations differ from addition and
subtraction in important way;→ i.e., they can be
performed in any one of registers or in memory location.

Mnemonic Opcode Number Format /Addressing Symbols Indicators

of bytes
INR A 3C h 1-byte Opcode (A)← (A) + 1 Z
(register)
Increment accumulator
DCX H 2B h 1-byte Opcode (HL)←(HL) – 1
(register)
Decrement HL registers
 Instructions on Logical Operations
Instructions 
to perform various logical operations with
contents of accumulator 
♦AND, ♦OR, ♦Exclusive-OR, ♦Rotate, ♦Compare, ♦Complement

AND, OR, Executive-OR

Any 8-bit number, or contents of register, or of memory location
can be logically AND-ed, Or-ed, or Exclusive-OR-ed with
contents of accumulator.
The results are stored in accumulator.

Rotate 
Each bit in accumulator can be shifted either left or right to
next position.
 Instructions on Logical Operations
examples ♦AND, ♦ OR, ♦Executive-OR
Mnemonic Opcode Number Format /Addressing Symbols Indicators
of bytes
AND

ANA H A4 h 1-byte Opcode (A)← (A)*(H) CY, Z

A&H (register)
ANA M A6 h 1-byte Opcode (A)←(A) * ((H) (L)) CY, Z
A & loc(HL) (non-direct registry)
OR

ORI F6 h 2-bytes Opcode + data (A)←(A) + 2nd byte CY, Z

A or data (immediate)
ORA M B6 h 1-byte Opcode (A)←(A) + ((H)(L)) CY, Z
A or loc(HL) (non-direct registry)
Executive-OR

XRA A AF h 1-byte Opcode (A)←(A)  (A) Z=1

A exclusive (register) CY
or A
XRI EE h 2-bytes Opcode + data (A)←(A)  (2nd bait) Z
A exclusive (immediate) CY
or A
 Instructions on Logical Operations
Instructions 
to perform various logical operations with contents of
accumulator 
♦Rotate, ♦Compare, ♦Complement

Rotate 
Each bit in accumulator can be shifted either left or right to
the next position.

Compare 
Any 8-bit number, or contents of register, or memory location can be
compared for equality, greater than, or less than, → with contents of
accumulator.

Complement 
Contents of accumulator can be complemented.  All 0-s are replaced
by 1-s and all 1-s are replaced by 0-s;
 Instructions on Logical Operations
examples  ♦Rotate, ♦ Compare, ♦ Complement 
Mnemonic Opcode Number Format /Addressing Symbols Indicators
of bytes
Rotate
RAR 1F h 1-byte Opcode CY
shift right (register)
RA L 17 h 1-byte Opcode CY
shift left (register)
Compare
CPI FE h 2-bytes Opcode + data (A)← 2nd byte Z=1, if
Compare A (immediate) A=2nd byte;
with operand CY=1, if
A2nd byte
CMP L BD h 1-byte Opcode (A) ─ (L) Z=1, if
A or loc(HL) (registry) (A)=(L);
CY=1, if
(A)(L)
Complement
XRA A AF h 1-byte Opcode (A)←(A)  (A) Z=1
A exclusive (register) CY
or A
XRI EE h 2-bytes Opcode + data (A)←(A)  (2nd bait) Z
A exclusive (register) CY
or A
 Instructions for Branching Operations
Instructions  to alter the sequence of program execution
either conditionally or unconditionally 
Jump 
Conditional jumps are an important aspect of the decision-making process in the
programming.
These instructions test for a certain conditions (e.g., Zero or Carry flag) and alter
the program sequence when the condition is met. In addition, the instruction set
includes an instruction called unconditional jump.

Call, Return, and Restart 

These instructions change the sequence of a program either by calling a
subroutine or returning from a subroutine.
The conditional Call and Return instructions also can test condition flags.
 Instructions on Branching and Transitions
Commands
examples  ♦ Jump ♦ Call, Return, and Restart, 
Mnemonic Opcode Number Format /Addressing Symbols Indicators
of bytes
Jump
JMP C3 h 3-bytes Opcode +low address (PC) ←(address 2 bytes)
go to LOC + high address
(direct) no-conditional
JZ CA h 3-bytes Opcode +low (PC) ← (address 2 if Z=0
go to LOC, address + high address bytes)
if 0 (direct) conditional
JC DA h 3-bytes Opcode +low address (PC) ← (address 2 if CY=1
go to LOC, if + high address bytes)
carrying over (direct) conditional
Call & Return
CALL C11 h 3-bytes Opcode +low address ((SP)-1)← PC H)
Move address + high address) ((SP)-2)← PC L)
from PC to (immediate) (SP) ← (SP-2)
stack zone (PC) ← (address)
RET C9 h 1-byte Opcode (PCL) ← ((SP))
Move address (registry) (PCH) ← ((SP)+1)
from stack
zone to PC (CP) ← (SP)+2)
RST C7 h 1-byte contents of PC moved (SP)← (PC)
Move address to stack, providing a
from stack return address for
zone to PC later use by RETURN
 Microprocessor Operations Related
to Data Manipulation
MP related to data manipulation is summarized in
four functions:

1. copying data

2. performing arithmetic operations

3. performing logical operations

4. testing for a given condition and alerting the

program sequence
 Important Aspects of Instructions
Some important aspects of the instruction set are noted below:

1. In data transfer, the contents of source are not destroyed;

only contents of the destination are changed.
The data copy instructions do not affect the flags.
2. Arithmetic and Logical operations are performed with
contents of
accumulator, and the results are stored in the accumulator
(with some expectations). The flags are affected according
to the results.

3. Any register including memory can be used for increment

and decrement.

4. A program sequence can be changed either conditionally or

by testing for a given data condition.
 Machine Control Operations
Instructions for control of machine functions 

Halt, Interrupt, or do nothing.

 Instruction Format

An instruction is a command to MP to perform a given

task on specified data.
Each instruction has two parts:  1st→is task to be
performed →the operation code (opcode);
 2nd→is data to be operated on, called the operand.

The operand (or data) can be specified in various ways.

It may include 8-bit (or 16-bit ) data, an internal register,
a memory location, or 8-bit (or 16-bit) address.

In some instructions, the operand is implicit (неявный).

 Instruction Format
Instruction word size

The 8085 instruction set is classified into following three

groups according to word size:

1. One-word or 1-byte instructions

2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions

In 8085, "byte" and "word" are synonymous

because it is an 8-bit microprocessor.

However, instructions are commonly referred to in

terms of bytes rather than words.
 Instruction Format  1-byte instruction
One byte Instruction → opcode and operand in same byte.
In one-byte operand → internal register and are coded into instruction.

All these are 1-byte instructions performing three different tasks.

In first instruction → both operand registers are specified.

In second instruction → operand B is specified and accumulator is assumed.

In third instruction → accumulator is assumed to be implicit operand.

These instructions are stored in 8-bit binary format in memory;

each requires one memory location.
 Instruction Format  1-byte instruction
Example: MOV D, S
Rregister D <─ Rregister S  copies contents of S-register into D-register.
Coded as 01 ddd sss
where ddd →is a code for one of 7 general registers
which is destination of data,
sss→is code of source register.

Example: MOV A,B 78h

Rregister A ⇐ Rregister B copies contents of A-register to B-register
Coded as 01111000 = 78h = 170 octal (восьмеричный)
where [111] → is code of A register;
[000] → is code of B register;

Example: ADD R
RregisterA <─Rregister A + Rregister R  summation contents of A-register with
content of R-register and result is move to A-register, again.
 Instruction Format  2-bytes instructions
Two byte Instructions → 1st byte specifies → operation code;
→ 2nd byte →specifies operand.
Source operand is a data byte immediately following opcode.

Instruction requires → two memory locations to store in memory.

MVI R,data
rregister R <─ data  data moves to R-register.
Instruction Format  2-bytes instructions
MVI R,data
Rregister R <─ data  data moves to R-register.

Example: → MVI A,30h has code as

3Eh (opcode)+30h(operand) as two bytes.
This is an immediate addressing.
Example: → ADI data C6h(opcode)
A <─ A + data

Example: → OUT port D3h(opcode)

Content of accumulator (A) to be send to I/O port.
Where number of port  is 8-bit device (port) address.
port ⇐(A)  the 2nd byte is not data
it is number/address of port where of Accumulator
will be moved.
This is called direct addressing.
Instruction Format  three-bytes instructions
 Instruction Format  3-bytes instructions
LXI rp, data 16 ← it is common form
rp is one of pairs of registers — BC, DE, HL used as 16-bit registers.

The two data bytes are 16-bit data in LH order of significance.

rp <─ data16

Example:→ LXI H,0520H 21h(opcode)+20h(operand)+05h(operand)

(HL) registers to be loaded by two bytes of data
Coded as [21H 20H 50H] in three bytes.
This is also immediate addressing.

LDA addr
A <-- (addr) Addr is a 16-bit address in L H order.

Example: → LDA 2134H 3A h(opcode)+21h(operand)+34h(operand)

Accumulator (A) to be loaded by data, that placed in address indicated by
2 operands
coded as [3AH 34H 21H]
This is also direct addressing.

.
 Sample programs1
Write an assembly program to add Write an assembly program to
two numbers Program multiply a number by 8 program

► MVI D, 8Bh move data to D-reg ► MVI A, 30H move data to A-reg
► MVI C, 6Fh move data to C-reg ► RRC shift of (A) content to right with carry
► RRC shift of (A) content to right with carry
► MOV A, C move data from C-reg to A-reg
► RRC shift of (A) content to right with carry
► ADD D sum up (A) with (D)
► OUT PORT1
► OUT PORT1 content of (A) to Port 1 ► HLT
► HLT stop MP

.
 Sample programs2
Write an assembly program to find greatest between
two numbers.
Program
► MVI B, 30h move data to B-reg;
► MVI C, 40h move data to C-reg;
► MOV A, B move data from B-reg to A-reg;
► CMP C compare content of A-reg with C-req;
► JZ EQU jump if equal (A)=(C) ;
► JC GRT jump if carry;
► OUT PORT1 move content of A-reg to Port 1;
► HLT stop microprocessor;

► EQU: MVI A, 01h move O1H to A-reg;

► OUT PORT1 move content of A-reg to Port 1;
► HLT stop microprocessor;
► GRT: MOV A, C move data from C-reg to A-reg;
► OUT PORT1 move content of A-reg to Port 1;
► HLT stop microprocessor;

.
 Sample programs 3
Summing up of three summands
 Sample programs 3
Summing up of three summands and placing result to 4th cell
 Sample programs 4
Compare of two numbers and placing of biggest one to cell 2040 H
 Sample programs 4
To place 0-9 numbers to cells 2040 H÷ 2048 H
 Registers

MP 8085/8080A  six general-purpose registers to store 8-bit data; 

B,C,D,E,H, and L.
They can be combined as register pairs - BC, DE, and HL - to perform 16-bit
operations.
The programmer can use these registers to store or copy data into registers by
using data copy instructions.
 Registers
Program Counter (PC)  16-bit register is memory pointer. Memory locations have
16-bit addresses,
MP uses this PC to sequence the execution of instructions.
Function of PC is to point to memory address from which the
next byte is to be fetched.

After fetching of byte (machine code) the PC is incremented by

one to point to next machine code location in memory.

Stack Pointer (SP) 16-bit register used as a memory pointer.

It points to memory location in R/W memory, called the stack.
The beginning of stack is defined by loading  16-bit address
in SP.
 Flag Register
Flags  five flip-flops, → to be set/reset after operation according to data conditions
of result in accumulator or registers .    Zero(Z), Carry (CY), Sign (S), Parity
(P), and Auxiliary Carry (AC) flags;
MP uses flags to test data conditions.
If sum in accumulator > 8 bits  Carry flag (CY) – is to set to one.

If O is in accumulator  Zero (Z) flag is to set to 1;

Flag register  8-bit register. Five bit positions in register out of eight are used
by programmer to examine these flags or data conditions. Flags is important in
decision-making process of MP.

Instruction JC (Jump on Carry) is implemented to change sequence

of program when CY flag is set.
 Flag Register
Status Bit Conditions
It is sometimes convenient to supplement the ALU circuit in the CPU with a status
register where status bit conditions can be stored for further analysis.
Status bits are also called condition-code bits or flag bits.

The four status bits are symbolized by C, S, Z, and V.

The bits are set or cleared as a result of an operation performed in the ALU.
1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is O.
2. Bit S (sign) is set to 1 if the highest-order bit F? is 1. It is set to 0 if the bit is 0.
3. Bit Z (zero) is set to 1 if the output of the ALU contains all 0's.
It is cleared to 0 otherwise.
In other words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1,
and cleared to 0 otherwise.

This is the condition for an overflow when negative numbers are in 2's complement.
For the 8-bit ALU, V = 1 if the output is greater than +127 or less than -128.
Flag Register
General Definition
General Definition
General Definition
General Definition
General Definition