Question Bank Class Test -2

Department of Information Technology

Subject:- DTM
Class:- IF3A-B-C

1. State the functions of the following pins of 8086 microprocessor. i) ALE ii) DT/ R
iii) M/ Io iv) HOLD v) NMI vi) INTR vii) BHE’/S7 viii)MN/MX’ ix) DEN’
x)TEST’ xi)Ready
ANS:
i. ALE:- Address Latch Enable: This output signal indicates the availability of
valid address on the address/data bus, and is connected to latch enable input of
latches.

ii. DT/R:- Data transmit/Receive: This output signal is used to decide the direction
of date flow through the bi- directional buffer. DT / R* = 1 Indicates transmitting
and DT / R* = 0 indicates receiving the data.

iii. M/IO:- This signal selects either memory operation or I/O operation. This line
indicates that the microprocessor address bus contains either a memory address
or an I/O port address. The signal high at this pin indicates a memory operation.
This line is logically equivalent to S2 in maximum mode.

iv. HOLD:- The hold input requests a direct memory access (DMA). If the hold
signal is at logic 1, the micro process stops its normal execution and places its
address, data and control bus at the high impedance state.

v. NMI:- Non-maskable Interrupt: The non-maskable interrupt input is similar to

INTR except that the NMI interrupt does not check for interrupt enable flag is at
logic 1, i.e, NMI is NOT maskable internally by software. If NMI is activated, the
interrupt input uses interrupt vector 2.

vi. INTR:- Interrupt Request: Interrupt request is used to request a hardware

interrupt of INTR is held high when interrupt enable flag is set, the 8086 enters
an interrupt acknowledgement cycle after the current instruction has completed
its execution.

vii. BHE/S7:- The bus high enable (BHE) signal is used to indicate the transfer of
data over the higher order D15 - D8 data bus. It goes low for the data transfer
over D15 - D8 and is used to derive chip select of odd address memory bank or
peripherals.
viii. MN/MX:- The minimum/maximum mode signal to select the mode of operation
either in minimum or maximum mode configuration. Logic 1 indicates minimum
mode.

ix. DEN:- Data Enable: Data bus enable signal indicates the availability of valid
data over the address/data lines.

x. TEST:- This input is tested by “WAIT” instruction. If the TEST input goes low;
execution will continue. Else the processor remains in an idle state.

xi. READY:- This is the acknowledgement from the slow devices or memory that
they have completed the data transfer operation. This signal is active high.

2. List any 8 features of 8086 microprocessor.

ANS:
1. It is 16-bit microprocessor
2. It has a 16-bit data bus, so it can read data from or write data to memory and ports
either 16-bit or 8-bit at a time.
3. It has 20-bit address bus and can access up to 220 memory locations (1 MB).
4. It can support up to 64K I/O ports
5. It provides 14, 16-bit registers
6. It has multiplexed address and data bus AD0-AD15 & A16-A19
7. Prefetches up to 6 instruction bytes from memory and queues them in order to
speed up the processing.
8. 8086 supports 2 modes of operation:
Minimum mode
Maximum mode

3. Interpret the given program and specify the o/p for the following situations:

MOV AX, 3459 H,

MOV BX, 3A69H
a) Rotate Right through carry contents of BX by 4 positions.
b) Shift left content of BX by 6 positions
4. State the function of linker and debugger.

5. State the function of STC, AAA, AAM, IMUL, DAA instructions of 8086
microprocessor
ANS:-
STC: This instruction sets the carry flag.
AAA:
AAM:
IMUL: this instruction is used for the multiplication of signed numbers.
DAA: (decimal adjust for addition)
It makes the result impact BCD form after BCD addition is performed
6. List the logical instruction
ANS:
i. NOT destination
ii. And destination, source
iii. Or destination, source
iv. Ex- OR destination, source
v. Test destination source

7. Explain the process of physical address calculation and calculate the physical
address of the following.
(1) 4370 H : 561E H
(2) 7A32 H : 6028 H.
ANS: While addressing any location in the memory bank, the physical address is
calculated from two parts

Physical address= segment address * 10H + offset address

The first is segment address, the segment registers contain 16-bit segment base
addresses, related to different segment.
The second part is the offset value in that segment.
Physical address is calculate as below:
Ex: Segment address (CS) = 1005H
Offset address -- (IP) = 5555H

Physical address = CS * 10 H + IP
= 1005 H * 10 H + 5555 H
= 10050 H + 5555 H
= 155A5 H

8. Explain String Instructions of 8086 Microprocessors

ANS:
i. A string is a series of bytes stored sequentially in the memory. String
instructions operate on such “strings”.
ii. For referring to a string two parameters are required, <a> starting or end address
of the string <b> length of the string
iii. Source element is taken from the data segment using SI register
iv. Destination element is in the extra segment pointed by the DI register
1) MOVS: MOVSB / MOVSW(move string)
 It is used to transfer a word / byte from data segment to extra segment.

2) LODS: LODSB / LODSW(load string)

It is used to load AL / AX register with a byte / word from data segment.

3) STOS: STOSB / STOSW(store string)

It is used to store the contents of AL / AX in the extra segment.

4) CMPS: CMPSB / CMPSW(compare string)

It is used to compare a byte / word present in the data segment with a
byte / word present in extra segment.

5) SCAS: SCASB / SCASW(scan string)

It is used to compare the contents of AL /AX with a byte /word present
in extra segment.

6) REP(repeat) :-
i. This is an instruction prefix, which can be used in string instruction.
ii. It causes the instruction to be repeated CX number of times.
iii. After each execution, the SI and DI registers are incremented /
decremented based on the DF(direction flag) and CX is decremented.

9. Explain Addressing modes of 8086 microprocessor with an example

ANS: Addressing mode is the way of specifying the operand (data). There are 8
addressing modes.
i. Immediate addressing mode:- In this mode the operand is directly specified in
the instruction itself.
ii. Direct addressing mode :- In this mode the address of the operand is specified in
the instruction.
iii. Register addressing mode:-In this mode the operand is specified using register.
iv. Register indirect addressing mode:- in this mode the address of the operand is
specified using register.
v. Register relative addressing mode:- In this mode the operand address is
calculated by using base register and 8 or 16 bit displacement.
vi. Base index addressing mode :- In this mode the operand address is calculated
using base register and index register.
vii. Base index relative addressing mode :- In this mode operand address is
calculated using base register, index register and 8 or 16 bit displacement.
viii. Implied addressing mode :- In this mode operand is implied and not specified in
the instruction.
10. Draw architectural block diagram of 8086 microprocessor and describe the function
of each block
ANS:

The 8086 CPU is divided into two independent functional parts

o Bus Interface Unit (BIU)
o Execution Unit (EU)
• The Execution Unit (EU):
i. The execution unit of the 8086 tells the BIU where to fetch instructions or data
from, decodes instructions, and executes instructions.

ii. The EU contains control circuitry, which directs internal operations.

iii. A decoder in the EU translates instructions fetched from memory into a series of
actions, which the EU carries out.

iv. The EU has a 16-bit arithmetic logic unit (ALU) which can add, subtract, AND,
OR, XOR, increment, decrement, complement or shift binary numbers.

v. The main functions of EU are:

Decoding of Instructions
Execution of instructions

• Bus Interface Unit (BIU):

The BIU sends out addresses, fetches instructions from memory, reads data from ports
and memory, and writes data to ports and memory. In simple words, the BIU handles all
transfers of data and addresses on the buses for the execution unit.
11. Write an assembly language program to find the largest number among the series of
N number.
ANS:
• Model small
• Data
Array db 08H,04H,02H,08H
• Code
Entrypoint:
mov ax, @data
mov ds, ax
mov cx, 0003H
lea si, array
mov al, [si]
up: inc si
cmp al, [si]
jnb down
mov al,[si]
down : dec cx
jnz up
mov ah, 4ch
int 21h
ends
end entrypoint

12. Draw maximum mode configuration of 8086 and explain any four-control signal
generated by bus controller
ANS:
All control signals for memory and IO are generated by 8288 on behalf of 8086

Control signals are generated 8288 bus controller according to requirement of 8086 as
informed by S2, S1 and S0.

Along with control signals like IO/Memory read and write 8288 also generates 𝐼𝑁𝑇𝐴̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅
signal in response to interrupt on INTR.

S2 S1 S0 8086 wants 8288

to perform generates a
signal to
fulfill 8086
requirement

0 0 1 Acknowledge 𝐼𝑁𝑇𝐴̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅

INTR

0 1 0 Read from 𝐼𝑂𝑅𝐶̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅

IO device
̅̅̅̅̅̅̅
0 1 1 Write into IO 𝐼𝑂𝑊𝐶̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ and
̅̅̅̅̅̅̅
device 𝐴𝐼𝑂𝑊𝐶̅̅̅̅̅̅̅̅̅̅̅̅̅̅

1 0 0 Halt None
̅̅̅̅̅̅̅
1 0 1 Instruction 𝑀𝑅𝐷𝐶̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
fetch
̅̅̅̅̅̅̅
1 1 0 Read from 𝑀𝑅𝐷𝐶̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Memory

1 1 1 Write into 𝑀𝑊𝑇𝐶̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅ and

Memory 𝐴𝑀𝑊𝑇𝐶

13. Write an assembly language program to arrange given numbers in ascending order.

14. Compare the following terms

i) RCR and RCL ii) JUMP and CALL
ANS:
• RCR:- Rotate right with carry
This instruction rotates the destination operand to the right through the carry flag. The
LSB moves into carry flag and carry flag into MSB.
Eg: RCR BL, 01H
• RCL:- Rotate left with carry
This instruction rotates the destination operand to the left through the carry flag. The
MSB moves into carry flag and carry flag into LSB.
Eg. RCL BL,01H

• JUMP
i. JMP(unconditional jump):-
In this case the execution control is transferred to the specified location independent
of any status or condition.
For example:-
JMP UP
ii. J condition (conditional jump)
I. This is a conditional branch instruction.
II. In where's the control is transferred to the specified location if the
provided condition is specified.
III. If the condition is false then branch does not take place and the next
sequential instruction is executed.
IV. For example : JNC next

• CALL:
i. This instruction is used to call a subroutine (sub-program) from the main
program.
ii. CALL is an instruction that transfers the program control to a subroutine, with
the intention of coming back to the main program.
iii. Thus in CALL 8086 saves the address of the next instruction into the stack
before branching to the subroutine.
iv. At the end of the subroutine, control transfers back to the main program using
the return address from the stack.

15. Write 8086 assembly language program with algorithm to add two 16 bit numbers.
ANS:
• Model small
• Data
a dw 1234H
b dw 4321H
• Code
Entrypoint:
mov ax, @data
mov ds, ax
mov ax, a
mov bx, b
 add ax, bx
mov ah, 4ch
int 21h
ends
end entrypoint

16. State and explain concept of memory segmentation and pipelining.

ANS:
i. The memory in an 8086 based system is organized as segmented memory.

ii. The CPU 8086 can access 1MB of physical memory. The complete 1MB of
memory can be divided into 16 segments, each of 64KB size and is addressed
by one of the segment registers.

iii. The 16-bit contents of the segment register actually point to the starting location of
a particular segment. The address of the segments may be assigned as 0000H to
F000h respectively.

iv. To address a specific memory location within a segment, we need an offset address.
The offset address values are from 0000H to FFFFH so that the physical addresses
range from 00000H to FFFFFH.

17. Explain concept of pipelining with neat diagram.

ANS:

Fetching the next instruction while the current instruction executes is called pipelining

i. As shown in the figures a non-pipelined processor (8085) for fetching and

executing 5 instructions, 10-time cycles are required.
ii. While in 8086, for fetching and executing 5 instructions 6-time cycle is required.
In the pipeline, while one instruction is being executed side by side the next
instruction is being fetched.
iii. While the EU is decoding an instruction or executing an instruction, which does
not require use of the buses, the BIU fetches up to six instruction bytes for the
following instructions.
iv. The BIU stores these pre-fetched bytes in a first-in-first-out register set called a
queue.
v. When the EU is ready for its next instruction from the queue in the BIU. This is
much faster than sending out an address to the system memory and waiting for
memory to send back the next instruction byte or bytes.
 vi. 8086 has a 16-bit data bus thus code is refilled in the queue when at least 2 bytes
are empty.
Drawbacks:
1. Data dependency-
2. Branching-
Advantages:
1. Pipelining boost performance.
2. Fetching and executing is done alongside at the same time.
3. Saves time.
4. Fewer instruction cycles are required.

18. Draw flag register format of 8086 microprocessor

ANS: