5.1 - Microcontroller and Microprocessor Architecture
5.1 - Microcontroller and Microprocessor Architecture
INTRODUCTION TO MICROCONTROLLER
At the end of this chapter, the
students should be able to.…
Controller
Intel 8085 – 8-bit
Intel 8086/8088 – 16-bit Intel 8051 – 8-bit
Intel 8096 – 16-bit
Microprocessors and
Microcontrollers
Microprocessors and
Microcontrollers
CPU
CONTROL/
FETCH, DECODE
MONITOR
AND EXECUTE AN
(INPUT/OUTPUT)
INSTRUCTION
DEVICES
THE BUSES:
ADDRESS, DATA,
AND CONTROL
Terminology used for microcontrollers
Machine Cycle
To execute an instruction–the processor
must:
1. Fetch the instruction from memory
2. Decode the instruction
3. Execute the instruction
4. Store the result back in the memory.
CPU (Central
ONE machine cycle = ‘X’ clock cycles (‘X’
depends on the particular
instruction being executed).
Processing Unit)
•Brain of the computer
•Admin all activities in the system
•Perform all data operations based
on instruction set (set of binary PROCE
codes) Faster SSOR
•Fetching executio IS
•Executing Time to n of
FASTE
complet instructi
R!
Clock e a cycle ons
↓
Terminology used for microcontrollers
Fetching and
Executing an
Instruction
•Fetching involves the following steps:
•Contents of PC are placed on address bus.
•READ signal is activated.
•Data (instruction opcode) are read from RAM and placed on data bus.
•Opcode is latched into the CPU’s internal instruction register.
•PC is incremented to prepare for the next fetch from memory.
•Execution involves: decoding the opcode and generating control signals to gate internal
registers in and out of the ALU and to signal the ALU to perform the specified operation
Terminology used for microcontrollers
CONTROL/MONITOR
(INPUT/OUTPUT) DEVICES
INTERNAL
BUS MEMORY INSTRUCTION ARCHITECTUR
Microcontrollers SET E
can be classified WIDTH
on the basis of
internal bus
width,
architecture,
memory and
instruction set.
FAMILY
Types of Microcontrollers
EMBEDDED MICROCONTROLLERS
When an embedded system has an microcontroller unit that has all the
ON functional blocks (including program as well as data memory)
S ED RY available on a chip is called an embedded microcontroller. For
BA EMO example, 8051 having Program & Data Memory, I/O Ports, Serial
M
Communication, Counters and Timers and Interrupt Control logic on
the chip is an embedded microcontroller.
ON N
SED TIO
BA RUC RISC (REDUCED INSTRUCTION SET COMPUTER)
ST ET
IN S ARCHITECTURE MICROCONTROLLERS
The industry trend for microprocessor design is for Reduced
Instruction Set Computers (RISC) designs. When a microcontroller
has an instruction set that supports fewer addressing modes for the
arithmetic and logical instructions, and for data transfer
instructions, the microcontroller is said to be of RISC architecture.
D ON E
E R
BAS ECTU
IT
Von-Neumann
Harvard
C H
AR
(Princeton)
•Harvard Architecture refers to a memory structure
where the processor is connected to two different •A Von-Neumann Machine, in contrast to
memory banks via two sets of buses the Harvard Architecture provides one data
•This is to provide the processor with two distinct path (bus) for both instruction and data
data paths, one for instruction and one for data •As a result, the CPU can either be fetching
•Through this scheme, the CPU can read both an
These instruction and data from the respective memory an instruction from memory, or
banks at the same time read/writing data to it
architectures •This inherent independence increases the •Other than less complexity of hardware, it
differ in the way throughput of the machine by enabling it to always allows for using a single, sequential
pre-fetch the next instruction
data and •The Harvard Architecture executes instructions in
memory.
•The Von-Neuman architecture’s main
programs are fewer instruction cycles than the Von-Neumann
architecture advantage is that it simplifies the
stored and •The cost of such a system is complexity in microcontroller design because only one
accessed hardware memory is accessed.
•Commonly used in DSPs
Types of Microcontrollers
Harvard
D ON E
E
BAS ECTU
R and
IT
ARC H von-Neumann Architecture
Design Operation of Memory
The Design and Operation of Memory
Memory in a microprocessor system is where information
(data and instructions) is kept. It can be classified into two
main types:
Main memory (RAM and ROM)
Storage memory (Disks , CD ROMs, etc.)
24
Accessing Information in Memory
For the microprocessor to access (Read or Write)
information in memory (RAM or ROM), it needs to do the
following:
Select the right memory chip (using part of the address bus).
Identify the memory location (using the rest of the address bus).
Access the data (using the data bus).
25
The Basic Memory Element
The basic memory element is similar to a D latch.
This latch has an input where the data comes in. It has an
enable input and an output on which data comes out.
Enable
EN
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The Basic Memory Element
However, this is not safe.
Data is always present on the input and the output is always set
to the contents of the latch.
To avoid this, tri-state buffers are added at the input and output
of the latch.
WR RD
Enable
EN
27
The Basic Memory Element
The WR signal controls the input buffer.
The bar over WR means that this is an active low signal.
So, if WR is 0 the input data reaches the latch input.
If WR is 1 the input of the latch looks like a wire connected to
nothing.
The RD signal controls the output in a similar manner.
28
A Memory “Register”
If we take four of these latches and connect them together,
we would have a 4-bit memory register
I0 I1 I2 I3
WR
D D D D
Q Q Q Q
EN EN EN EN
EN
RD O0 O1 O2 O3
29
A group of memory registers
D0 D1 D2 D3
o o o o
WR
D Q D Q D Q D Q
EN EN EN EN
D Q D Q D Q D Q
EN EN EN EN
Expanding on this
scheme to add more D Q D Q D Q D Q
EN EN EN EN
o o o o
RD
D0 D1 D2 D3
30
A group of Memory Registers
If we represent each memory location (Register) as a block we
get the following
I I I I
0 1 2 3
W Input Buffers
R
EN Memory Reg. 0
EN
0 Memory Reg. 1
EN
1 Memory Reg. 2
EN
2 Memory Reg. 3
3
Output Buffers
RD
O O O2 O
0 1 3
31
The Design of a Memory Chip
Using the RD and WR controls we can determine the
direction of flow either into or out of memory. Then using
the appropriate Enable input we enable an individual
memory register.
32
The Enable Inputs
How do we produce these enable line?
Since we can never have more than one of these enables active
at the same time, we can have them encoded to reduce the
number of lines coming into the chip.
These encoded lines are the address lines for memory.
33
The Design of a Memory Chip
So, the previous diagram would now look like the following:
I I I I
0 1 2 3
W Input Buffers
R
A D Memory Reg. 0
A1 d e Memory Reg. 1
d c
Memory Reg. 2
A0 r o
e d Memory Reg. 3
s e
RD s r Output Buffers
O O O2 O
0 1 3
34
The Design of a Memory Chip
Since we have tri-state buffers on both the inputs and
outputs of the flip flops, we can actually use one set of
pins only.
The chip would now look like this:
W Input Buffers
R
A D Memory Reg. 0 D0 D0
A1 d e A1
Memory Reg. 1 D1 D1
d c
Memory Reg. 2
A0 r o D2 A0 D2
e d Memory Reg. 3
D3 D3
s e
RD s r Output Buffers
RD W
R
35