Cpu
Cpu
Cpu
P-1V P-111
To improve thermal conductivity, the PPGA uses a nickel plated copper heat slug
on top of the processor. The PPGA package is used by early Intel Celeron
processors, which have 370 pins.
S.E.C.C. is short for Single Edge Contact Cartridge
The S.E.C.C. package was used in the Intel Pentium II processors, which have
242 contacts and the Pentium® II Xeon™ and Pentium III Xeon processors, which
have 330 contacts.
L2 Cache memory is added inside the package
In the original PC design (the IBM XT), the CPU,
RAM and I/O devices (which we will come to later)
were connected on one and the same bus, and
everything ran synchronously (at a common speed).
The CPU decided which clock frequency the other
devices had to work at:
In this architecture, the I/O bus is separate from the system
bus (80386).
The I/O devices (graphics card, hard disk, etc.) were
separated from the system bus and placed on a separate low
speed bus. This was because they couldn’t keep up with the
clock frequencies of the new CPU versions.
The connection between the two buses is managed by a
controller, which functions as a “bridge” between the two
paths.
Clock doubling
An external clock frequency
An internal clock frequency
486 was given a built-in L1 cache, to reduce the
imbalance between the slow RAM and the fast processor
Overclocking
In the case of the Pentium II and III, the system bus was increased
to 100 and 133 MHz, with the internal clock frequency set to a
multiple of these.
Gigantic cooler with two fans and pure silver contact surfaces.
Silverado, a German product which is used for overclocking CPU’s
Single Pentium 4 logically can function as if there are physically two
processors in the pc. The processor core (with its long pipelines) is
simply so powerful that it can, in many cases, act as two processors
A dual core processor with Hyper Threading operates as virtual quad-processor.
Intel also produces EE-versions of the Pentium 4. EE is for Extreme Edition, and
these processors are extremely speedy versions carrying 2 MB of L2 cache.
16 bits
8088 1979 29,000 3 5 MHz 0.33
8-bit bus