This document discusses Lab 6 on flip flops and counters. [1] It defines flip flops and clocked flip flops, explaining how clock signals control state changes. [2] It examines the J-K and D flip flops in detail, providing their input equations and examples. [3] It explores asynchronous and synchronous counters, including MOD-8 and MOD-<2^n> configurations. Students are instructed to complete the lab experiments in SimullDE, attaching their work and conclusions to a written report to submit for grading.
This document discusses Lab 6 on flip flops and counters. [1] It defines flip flops and clocked flip flops, explaining how clock signals control state changes. [2] It examines the J-K and D flip flops in detail, providing their input equations and examples. [3] It explores asynchronous and synchronous counters, including MOD-8 and MOD-<2^n> configurations. Students are instructed to complete the lab experiments in SimullDE, attaching their work and conclusions to a written report to submit for grading.
This document discusses Lab 6 on flip flops and counters. [1] It defines flip flops and clocked flip flops, explaining how clock signals control state changes. [2] It examines the J-K and D flip flops in detail, providing their input equations and examples. [3] It explores asynchronous and synchronous counters, including MOD-8 and MOD-<2^n> configurations. Students are instructed to complete the lab experiments in SimullDE, attaching their work and conclusions to a written report to submit for grading.
This document discusses Lab 6 on flip flops and counters. [1] It defines flip flops and clocked flip flops, explaining how clock signals control state changes. [2] It examines the J-K and D flip flops in detail, providing their input equations and examples. [3] It explores asynchronous and synchronous counters, including MOD-8 and MOD-<2^n> configurations. Students are instructed to complete the lab experiments in SimullDE, attaching their work and conclusions to a written report to submit for grading.
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VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRICAL ENGINEERING
DIGITAL LOGIC DESIGN LABORATORY
COURSE ID: IT099IU
INSTRUCTOR: M. ENG NGUYEN HOANG AN
1 Lab 5 Reviews In the fifth Lab, you were studying: The working principles of the DeMultiplexers 2-to-1, 4-to-1, and 8-to-1 DEMUX, with their characteristics and truth table, respectively. Building up the DEMUX circuits using logic gates and the ICs, respectively. Then, building circuits made up of DEMUX ICs based on the requirements . The practice of building the above circuits using SimullDE program. Practice building up the above circuit using Laboratory equipments. Reminding Submit your Lab report and simulation files for Lab 5 on Blackboard. Late submission will be receiving penalty of 20% per day of late submission. VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRICAL ENGINEERING
LAB 6 FLIP FLOPS and COUNTERS LABORATORY
INSTRUCTOR: M. ENG NGUYEN HOANG AN 3
II Discussion of Fundamentals 1a. Flip-flop definition Sequential logic circuit is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its inputs. Synchronous sequential circuits: the state of the device changes only at discrete times in response to a clock signal. Asynchronous sequential circuits: the state of the device can change at any time in response to changing inputs
Flip-flop (FF) has only two outputs, labelled and , that are inverse of each other while the inputs can be one or more inputs. A FF has two allowed operating states: HIGH and LOW, or 1 and 0, or SET and RESET (or CLEAR).
The inputs cause the FF to switch back and forth (“flip-flop”) between its two output states. The SET input sets to HIGH (or 1) state; the RESET input clears to the LOW (or 0) state. 4 1b. Clock Signal and Clocked Flip-flops – Clock Signal
5 1b. Clock Signal and Clocked Flip-flops – Clocked Flip-flops
6 2a. Clocked J-K Flip-Flop
7 2a. Clocked J-K Flip-Flop - Example
8 2a. Clocked J-K Flip-Flop – PRESET and CLEAR
9 2a. Clocked J-K Flip-Flop – PRESET and CLEAR example
10 2b. Clocked D Flip-Flop
11 2b. Clocked D Flip-Flop
12 2b. Clocked D Flip-Flop
13 3. Counters
14 3a. Counters – MOD-8 asynchronous counters
15 3a. Counters – MOD-8 asynchronous down counters
24 Present State Next State Q1 Q0 J1 K1 J0 K0 Q1 Q0 Write the excitation (trigger) input equations of all flip-flops: J0 = …………………...............; K0 = ….……………............... J1 = …………………...............; K1 = ….……………............... 3. Lab report
• Use SimullDE Software to conduct the experiment
• Follow the instruction procedure • Capture the simulation circuits and output waveforms, attach them into the lab report • Conclude about the experiments • Submit via Blackboard before the day of the next Lab • Plagiarism violation: similarity score must be less than 30%. • Note: Remember to follow the Template for LAB report • Instruction: Put your simulation files for each problems and the report (PDF format) in a folder named as: • DLDLab_Name1st_Name2nd_Lab# • Then compress as *.rar or *.zip file and submit via Blackboard.
