Module 5.

Basic
Processing Unit
Overview
 Instruction Set Processor (ISP)
 Central Processing Unit (CPU)

 A typical computing task consists of a series

of steps specified by a sequence of machine

instructions that constitute a program.
 An instruction is executed by carrying out a

sequence of more rudimentary operations.

Some Fundamental
Concepts
Fundamental Concepts
 Processor fetches one instruction at a time and
perform the operation specified.
 Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
 Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
 Instruction Register (IR)
Executing an Instruction
 Fetch the contents of the memory location pointed
to by the PC. The contents of this location are
loaded into the IR (fetch phase).
IR ← [[PC]]
 Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
 Carry out the actions specified by the instruction in
the IR (execution phase).
Processor Organization Internal processor
bus
Control signals

PC

Instruction
Address
decoder and
lines
MDR HAS MAR control logic
TWO INPUTS Memory
AND TWO bus
OUTPUTS MDR
Data
lines IR

Datapath
Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP

Z
Textbook Page 413

Figure 7.1. Single-bus organization of the datapath inside a processor.

Executing an Instruction
 Transfer a word of data from one processor
register to another or to the ALU.
 Perform an arithmetic or a logic operation
and store the result in a processor register.
 Fetch the contents of a given memory
location and load them into a processor
register.
 Store a word of data from a processor
register into a given memory location.
Register Transfers Riin
Internal processor
bus

Ri

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
Register Transfers
 All operations and data transfers are controlled by the processor clock.
Bus

D Q
1
Q
Riout

Ri in
Clock

Figure 7.3.
Figure 7.3.Input
Inputand
andoutput
output gating
gating for one register
register bit.
bit.
Performing an Arithmetic or
Logic Operation
 The ALU is a combinational circuit that has no
internal storage.
 ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
 What is the sequence of operations to add the
contents of register R1 to those of R2 and store the
result in R3 i.e. ADD R1,R2,R3?
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in
Fetching a Word from Memory
 Address into MAR; issue Read operation; data into MDR.
Memory-bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure 7.4.
Figure 7.4. Connection and control
Connection and controlsignals
signalsfor
forregister
registerMDR.
MDR.
Fetching a Word from Memory
 The response time of each memory access varies
(cache miss, memory-mapped I/O,…).
 To accommodate this, the processor waits until it
receives an indication that the requested operation
has been completed (Memory-Function-Completed,
MFC).
 Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]
The following control signals are activated
R1 ,MAR
out in , READ

MDR , WMFC
inE

MDR ,, R2in,
out
 Step 1 2 3

Timing Clock

MARin MAR ← [R1]

Assume MAR
is always available Address
on the address lines
of the memory bus. Start a Read operation on the memory bus
Read

MR

MDRinE

Data

Wait for the MFC response from the memory

MFC

MDR out Load MDR from the memory bus

R2 ← [MDR]

Figure 7.5. Timing of a memory Read operation.

Storing a word in memory
 Address-> MAR
 Data-> MDR

 Write operation is initiated

 Load the contents of MDR into memory

 Wait for the MFC response from memory

 Instruction Move R2,(R1) requires the

following control signals
 R1out,MARin
 R2out, MDRin, Write
 MDRoutE, WMFC
Execution of a Complete
Instruction
 Add (R3), R1
Executing this instruction requires following
operation
 Fetch the instruction

 Fetch the first operand (the contents of the

memory location pointed to by R3)

 Perform the addition

 Load the result into R1

 Execution of a Complete
Instruction Internal processor
bus

Add (R3), R1 Control signals

PC

Instruction
Step Action Address
decoder and
lines
MAR control logic

1 PC out , MAR in , Read, Select4,Add, Zin Memory

bus

2 Zout , PC in , Y in , WMF C MDR

Data
IR
3 MDRout , IR in lines

4 R3out , MAR in , Read Y

R0
5 R1out , Y in , WMF C Constant 4

6 MDRout , SelectY,Add, Zin Select MUX

7 Zout , R1in , End Add

A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP
Figure7.6. Control sequence
forexecutionof theinstructionAdd (R3),R1.
Z

Figure 7.1. Single-bus organization of the datapath inside a processor.

Execution of Branch
Instructions
A branch instruction replaces the contents of
PC with the branch target address, which is
usually obtained by adding an offset X given
in the branch instruction.
 The offset X is usually the difference between

the branch target address and the address

immediately following the branch instruction.
 Conditional branch
Execution of Branch
Instructions

StepAction

1 PCout , MAR in , Read,Select4,Add, Zin

2 Zout, PCin , Yin, WMF C
3 MDRout , IR in
4 Offset-field-of-IR
out, Add, Zin

5 Zout, PCin , End

Branch on Negative (Branch<0) then

Offset-field-of IR out, Add, Zin , if N=0 then END

Figure 7.7. Control sequence for an unconditional branch instruction.

Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

PC

Register
file

Constant 4

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory bus Address

data lines lines

Figure 7.8. Three-b us organization of the datapath.

Multiple-Bus Organization
 Add R4, R5, R6

StepAction

1 PCout, R=B, MAR in , Read, IncPC

2 WMFC
3 MDRoutB, R=B, IR in
4 R4outA, R5outB, SelectA,Add, R6in, End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
Hardwired Control
Overview
 To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.
 Two categories: hardwired control and

microprogrammed control
 Hardwired system can operate at high speed;

but with little flexibility.

Control Unit Organization
CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Figure 7.10. Control unit organization.

Detailed Block Description
CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS 1
External
INS 2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

Generating Zin
 Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
Generating End
 End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…
Branch<0
Add Branch
N N

T7 T5 T4 T5

End

Figure 7.13. Generation of the End control signal.

A Complete Processor
Instruction Integer Floating-point
unit unit unit

Instruction Data
cache cache

Bus interface
Processor

System bus

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processor.

Microprogrammed
Control
Overview
 Control signals are generated by a program similar to machine
language programs.
 Control Word (CW); microroutine; microinstruction

MDRout

WMFC
MAR in

Select
PCout

R1out

R3out
Micro -

Read
PCin

R1 in
Z out
Add

End
IRin
Yin
instruction

Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An example of microinstructions for Figure 7.6.

Overview

Step Action

1 PC out , MAR in , Read, Select4,Add, Zin

2 Zout , PC in , Y in , WMF C
3 MDRout , IR in
4 R3out , MAR in , Read
5 R1out , Y in , WMF C
6 MDRout , SelectY,Add, Zin
7 Zout , R1in , End

Figure7.6. Control sequence

forexecutionof theinstructionAdd (R3),R1.
Overview
 Control store
Starting
IR address
generator One function
cannot be carried
out by this simple
organization.

Clock P C

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

Overview
 The previous organization cannot handle the situation when the control
unit is required to check the status of the condition codes or external
inputs to choose between alternative courses of action.
 Use conditional branch microinstruction.
Address
Microinstruction

0 PCout , MAR in , Read,Select4,Add, Zin

1 Zout , PCin , Yin , WMF C
2 MDRout , IRin
3 Branchtostartingaddress ofappropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, thenbranchtomicroinstruction
0
26 Offset-field-of-IR
out , SelectY,Add, Zin

27 Zout , PCin , End

Figure 7.17. Microroutine for the instruction Branch<0.

Overview External
inputs

Starting and
branch address Condition
IR codes
generator

Clock  PC

Control
store CW

Figure 7.18. Organization of the control unit to allow

conditional branching in the microprogram.