PIPELINING

• Pipelining is a technique of decomposing a

sequential process into sub-operations,
with each sub-process being executed in a
segment that operates concurrently with
all other segment.
Example for Pipeline Processing
Operations in each pipeline stage
General Four-Segment Pipeline
Pipeline Speedup

cpe 252: Computer Organization 5

Q1. In certain scientific computation it is necessary to perform
the arithmetic operation (Ai+Bi)*(Ci*Di)
a. Specify the pipeline configuration to carry out this task.
b. List the content of all registers of all the registers in the
pipeline for i=1 to 6.

Q2. Draw a space time diagram for a six-segment pipeline

showing the time it takes to process eight tasks.

Q3. A non-pipelined system takes 50ns to process a task. The

same task can be processed in a six-segment pipeline with a
clock cycle of 10ns. Determine the speedup ratio of the pipeline
for 100 tasks.
 Computer Instructions
• The basic computer has three instruction code formats.

• Each format has 16 bits.

• The operation code(op-code) part of the instruction contains three bits and
the meaning of remaining 13 bits depends upon the op-code encountered.
Computer Instruction Set
 Instruction Cycle
• The program is executed in the computer by going thru a
cycle for each instruction.

• In basic computer, each instruction cycle consists of the

following phases:

1. Fetch an instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory.

4. Execute the instruction.

Instruction Cycle
 Instruction Cycle
• Micro-operations for fetch & decode
 Data transfer between two
registers:
Transfer the contents of R1 to R4.
1. Enable output of register R1 by setting
R1out=1. This places the contents of R1
on the processor bus.
2. Enable input of register R4 by setting
R4in=1. This loads the data from the
processor bus into register R4.
 Performing an Arithmetic or
Logic Operation
• The ALU is a combinational circuit that has no
internal storage.
• ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
• What is the sequence of operations to add the
contents of register R1 to those of R2 and store the
result in R3?
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in
 Fetching a Word from Memory
Memory -bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure 7.4. Connection and control signals for

gister
re MDR.

• Address into MAR; issue Read operation; data into MDR.

Figure 7.4. Connection and control signals for register MDR.

 Fetching a Word from Memory
• The response time of each memory access varies
(cache miss, memory-mapped I/O,…).
• To accommodate this, the processor waits until it
receives an indication that the requested operation
has been completed (Memory-Function-Completed,
MFC).

• Example: Move (R1), R2

➢ MAR ← [R1]
➢ Start a Read operation on the memory bus
➢ Wait for the MFC response from the memory
➢ Load MDR from the memory bus
➢ R2 ← [MDR]
 Fetching a Word from
Memory
Example: Move (R1), R2
➢MAR ← [R1]
➢Start a Read operation on the memory bus
➢Wait for the MFC response from the memory
➢Load MDR from the memory bus
➢R2 ← [MDR]
Assume MAR is always available on the address lines of the memory
bus.
⚫ Move (R1), R2

1. R1out, MARin, Read

2. MDRinE, WMFC
3. MDRout, R2in
 Storing a word in memory
• Address is loaded into MAR
• Data to be written loaded into MDR.
• Write command is issued.

• Example: Move R2,(R1)

R1out,MARin
R2out,MDRin,Write
MDRoutE, WMFC
 Execution of a Complete
Instruction
• Example: Add (R3), R1
• Fetch the instruction
• Fetch the first operand (the contents of the
memory location pointed to by R3)
• Perform the addition
• Load the result into R1
 Execution of a Complete
Internal processor
bus
Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R( n - 1)
control ALU
lines
Carry -in
XOR TEMP

Instruction
Figure 7.1. Single-bus organization of the datapath inside a processor.

Add (R3), R1
 Micro-Operation
• Computer system micro-operations are of four types:

– Register transfer micro-operations

– Arithmetic micro-operations

– Logic micro-operations

– Shift micro-operations
Arithmetic Micro-operations
Logical Micro-operations
 Shift Micro-operations
➢R  shl R Shift-left register R

➢R shr R Shift-right register R

➢R cil R Circular shift-left register R

➢R  cir R Circular shift-right register

R

➢R  ashl R Arithmetic shift-left R

➢R  ashr R Arithmetic shift-right R

 Shift Microoperations

LOGICAL SHIFT
• In a logical shift the serial input to the shift
is a 0.
0

• A right logical shift operation:

0

• A left logical shift operation:

 Shift Microoperations

CIRCULAR SHIFT
• In a circular shift the serial input is the bit
that is shifted out of the other end of the
register.

• A right circular shift operation:

• A left circular shift operation:

Logical versus Arithmetic Shift
• A logical shift fills the newly created bit position with zero:

0
CF

• An arithmetic shift fills the newly created bit position with a

copy of the number’s sign bit:

CF

Arithmetic Right Shift Process

 Shift Microoperations

ARITHMETIC SHIFT
• An left arithmetic shift operation must be
checked for the overflow
sign
0
bit

Before the shift, if the leftmost two bits differ, the shift will
result in an overflow

• In a RTL, the following notation is used

– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
 Logic Microoperations

APPLICATIONS OF LOGIC
• LogicMICROOPERATIONS
micro-operations can be used to
manipulate individual bits or a portions of a
word in a register.

• Consider the data in a register A. In another

register B is bit data that will be used to
modify the contents of A.
 Logic Microoperations

SELECTIVE SET
• In a selective set operation, the bit
pattern in B is used to set certain bits in
A.

1100 A
1010 B (A  A + B)
OR Operation
1110 A
 Logic Microoperations

SELECTIVE COMPLEMENT
• In a selective complement operation, the
bit pattern in B is used to complement
certain bits in A.

1100 A
1010 B (A  A  B)
XOR Operation
0110 A
 Logic Microoperations

SELECTIVE CLEAR
• In a selective clear operation, the bit
pattern in B is used to clear certain bits
in A.

1100 A
1010 B (A  A  B’)
0100 A
 Logic Microoperations

MASK OPERATION
• The mask operation is similar to selective-
clear operation except that the bits of A are
cleared only where there are corresponding
0’s in B.

1100 A
1010 B (A  A  B)
AND Operation
1000 A
 Logic Microoperations

INSERT OPERATION
• An insert operation inserts a new value into
a group of bits. This is done by first
masking the bits and then ORing them with
the required value.

• Example: A register contains eight bits

0110 1010. To replace the four leftmost bits
by the value 1001, we first mask the four
unwanted bits.
 Question

• Register A holds the 8-bit binary

11011001. Determine the B operation and
the logic microoperation to be performed
in order to change the value in A to :
01101101, 11111101
Basic Processing Unit
 Fundamental Concepts
• Processor fetches one instruction at a time and
perform the operation specified.
• Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
• Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
• Instruction Register (IR)
 Executing an Instruction
• Fetch the contents of the memory location pointed
to by the PC. The contents of this location are
loaded into the IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
(where each instruction comprises 4 bytes)
• Carry out the actions specified by the instruction in
the IR (execution phase).
Processor Organization
Registers:
❖ The processor registers R0 to Rn-1 vary considerably from one
processor to another.
❖ Registers are provided for general purpose used by
programmer.
❖ Registers Y, Z & TEMP are temporary registers used by
processor during the execution of some instruction.
Multiplexer:
❖ Select either the output of the register Y or a constant value 4
to be provided as input A of the ALU.
❖ Constant 4 is used by the processor to increment the contents
of PC.
ALU:
Used to perform arithmetic and logical operation.
Data Path:
The registers, ALU and interconnecting bus are
collectively referred to as the data path.
Register Transfers Internal processor
bus
Riin

Ri

Riout

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
• The input and output gates for register Ri
are controlled by signals is Rin and Riout .
• If Rin is set to1 - data available on common
bus are loaded into Ri.
• If Riout is set to1 - the contents of register
are placed on the bus.
• Riout is set to 0 – the bus can be used for
transferring data from other registers .
 Data transfer between two
registers:
Transfer the contents of R1 to R4.
1. Enable output of register R1 by setting
R1out=1. This places the contents of R1
on the processor bus.
2. Enable input of register R4 by setting
R4in=1. This loads the data from the
processor bus into register R4.
 Performing an Arithmetic or
Logic Operation
• The ALU is a combinational circuit that has no
internal storage.
• ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
• What is the sequence of operations to add the
contents of register R1 to those of R2 and store the
result in R3?
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in
 Fetching a Word from Memory
Memory -bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure 7.4. Connection and control signals for

gister
re MDR.

• Address into MAR; issue Read operation; data into MDR.

Figure 7.4. Connection and control signals for register MDR.

 Fetching a Word from Memory
• The response time of each memory access varies
(cache miss, memory-mapped I/O,…).
• To accommodate this, the processor waits until it
receives an indication that the requested operation
has been completed (Memory-Function-Completed,
MFC).

• Example: Move (R1), R2

➢ MAR ← [R1]
➢ Start a Read operation on the memory bus
➢ Wait for the MFC response from the memory
➢ Load MDR from the memory bus
➢ R2 ← [MDR]
 Fetching a Word from
Memory
Example: Move (R1), R2
➢MAR ← [R1]
➢Start a Read operation on the memory bus
➢Wait for the MFC response from the memory
➢Load MDR from the memory bus
➢R2 ← [MDR]
Assume MAR is always available on the address lines of the memory
bus.
⚫ Move (R1), R2

1. R1out, MARin, Read

2. MDRinE, WMFC
3. MDRout, R2in
 Storing a word in memory
• Address is loaded into MAR
• Data to be written loaded into MDR.
• Write command is issued.

• Example: Move R2,(R1)

R1out,MARin
R2out,MDRin,Write
MDRoutE, WMFC
 Execution of a Complete
Instruction
• Example: Add (R3), R1
• Fetch the instruction
• Fetch the first operand (the contents of the
memory location pointed to by R3)
• Perform the addition
• Load the result into R1
 Execution of a Complete
Internal processor
bus
Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R( n - 1)
control ALU
lines
Carry -in
XOR TEMP

Instruction
Figure 7.1. Single-bus organization of the datapath inside a processor.

Add (R3), R1
 Question
• Write the control sequence to execute

1. Add the (immediate) number NUM to register R1.

2. Add the contents of memory location NUM to register

R1.

3. Add the contents of memory location whose address is

at memory location NUM to register R1.
 Solution 1
• PC out, MAR in, Read, Select4, Add , Zin
• Zout, PCin, Yin, WMFC
• MDRout, IR in,
• IR NUMout , Yin
• R1 out, Select Y, Add, Zin
• Zout, R1in, End

•
 Solution 2
• PC out, MAR in, Read, Select4, Add , Zin
• Zout, PCin, Yin, WMFC
• MDRout, IR in,
• IRNUM out, MAR in, Read
• R1out, Yin, WMFC
• MDRout, Select Y, Add, Zin
• Zout, R1in, End
 Solution 3
• PC out, MAR in, Read, Select4, Add , Zin
• Zout, PCin, Yin, WMFC
• MDRout, IR in
• IRNUM out, MAR in, Read
• WMFC
• MDRout, MAR in, Read
• R1out, Yin, WMFC
• MDRout , SelectY, Add, Zin
• Zout, R1in, End
Execution of Branch Instructions
• A branch instruction replaces the contents
of PC with the branch target address,
which is usually obtained by adding an
offset X given in the branch instruction.
• The offset X is usually the difference
between the branch target address and
the address immediately following the
branch instruction.
• UnConditional branch
Execution of Branch Instructions

Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in WMF C
,
3 MDR out , IR in

4 Offset-field-of-IR out , Select Y , Add, Z in

5 Z out , PC in , End

Figure 7.7. Control sequence for an unconditional branch instruction.

 Memory Organization
• Memory Hierarchy
– Memory hierarchy in a computer system :
• Main Memory : memory unit that communicates
directly with the CPU (RAM)
• Auxiliary Memory : device that provide backup
storage (Disk Drives)
• Cache Memory : special very-high-speed memory
to increase the processing speed (Cache RAM)
Auxiliary memory
Magnetic
tapes
Main
I/O processor
memory
Magnetic
disks

Cache
CPU
memory
 Memory Organization
– Multiprogramming
• enable the CPU to process a number of
independent program concurrently
– Memory Management System :
• supervise the flow of information between auxiliary
memory and mainRegister
memory
Cache

Main Memory

Magnetic Disk

Magnetic Tape

Memory Hierarchy is to obtain the highest possible access speed while minimizing
the total cost of the memory system
Random
– RAM Chips Access Memory (RAM)
– Static RAM
• Consists of Flip-flops to store binary information.
• Static RAM is easier to use and having short Read/Write cycles
• Used mostly in Cache memory.

– Dynamic RAM
▪ Stores binary information in the form of electric charge stored inside the
capacitor.
▪ The capacitors are provided by MOS transistors.
▪ Refreshing circuit is required to refresh the memory.
• Dynamic RAM offers reduced power consumption and large storage
capacity.
• It is used to construct main memory.
 Three State Buffer
Normal input A Output Y=A if C=1
High-impedence if C=0
Control input C

Select S1 0
S0 1
2×4 A0
Decoder 2
Enable E
3

B0

C0

Bus line with three-state buffer (replaces

MUX0 in the previous diagram)
D0
 Main Memory

MAIN MEMORY
RAM and ROM Chips
Typical RAM chip

Chip select 1 CS1

Chip select 2 CS2
Read RD 128 x 8 8-bit data bus
RAM
Write WR
7-bit address AD 7

CS1 CS2 RD WR Memory function State of data bus

0 0 x x Inhibit High-impedence
0 1 x x Inhibit High-impedence
1 0 0 0 Inhibit High-impedence
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inhibit High-impedence

Typical ROM chip

Chip select 1 CS1

Chip select 2 CS2
512 x 8 8-bit data bus
ROM
9-bit address AD 9
 Main Memory

MEMORY ADDRESS MAP

Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

Hexadecimal Address bus

Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
ROM 0200 - 03FF 1 x x x x x x x x x

Memory Connection to CPU

- RAM and ROM chips are connected to a CPU
through the data and address buses

- The low-order lines in the address bus select

the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs
 Main Memory

CONNECTION OF MEMORY TO CPU

Address bus CPU
16-11 10 9 8 7-1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2

Data
RD 128 x 8
RAM 1
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 2
WR
AD7

CS1
CS2

Data
RD 128 x8
RAM 3
WR
AD7

CS1
CS2
RD 128 x 8 Data
RAM 4
WR
AD7

CS1
CS2
Data

1- 7 512 x 8
8
9 } AD9 ROM
 Numerical Problems
Q1. a) How many 128x8 RAM chips are needed to provide a memory capacity of 2048
bytes.
b) How any lines of the address bus must be used to access 2048 bytes of memory. How
many of these lines will be common to all chips.
c) How many lines must be decoded for chip select? Specify the size of decoders.

Q2. Extend the memory system of Fig.1 to 4096 bytes of RAM and 4096 bytes of RAM.
List the memory-address map and indicate what size decoders are needed.

Q3. A computer employs RAM chips of 256x8 and ROM chips of 1024x8. The computer
system needs 2K bytes of RAM, 4K bytes of ROM, and four interface units each with four
registers. A memory-mapped I/O configuration used. The two highest-order bits of the
address bus are assigned 00 for RAM, 01 for ROM, and 10 for interface registers.

How many RAM and ROM chips are needed.

Draw a memory-address map for the system.
Give the address range in hexadecimal for RAM, ROM and interface.
• 12-5
Cache
Cache Memory
Memory
– Locality of Reference
• the references to memory tend to be confined within a few localized
areas in memory

– Cache Memory : a fast small memory

• keeping the most frequently accessed instructions and data in the fast
cache memory

– Hit Ratio
• the ratio of the number of hits divided by the total CPU references (hits +
misses) to memory
– hit : the CPU finds the word in the cache
– miss : the word is not found in cache (CPU must read main memory)

– A computer with cache access time of 100ns, a main memory access time of
1000 ns, a hit ratio of 0.9 is having average access time of 200ns.
 Types of Mapping of Cache
Memory
– Mapping
• The transformation of data from main memory to cache memory
– 1) Associative mapping
– 2) Direct mapping
– 3) Set-associative mapping

– Associative Mapping:
main memory : 32 K x 12 bit word (15 bit address lines)
cache memory : 512 x 12 bit word
– CPU sends a 15-bit address to cache
» Hit : CPU accepts the 12-bit data from cache
» Miss : CPU reads the data from main memory (then data
is written to cache)
 Associative Mapping
Main memory
CPU
32K×12 Cache memory
512×12

CPU address(15 bits)

Argument register

Address Data

0 1 0 0 0 3 4 5 0

0 2 7 7 7 6 7 1 0

2 2 3 4 5 1 2 3 4
Direct mapping :
Direct Mapping
n bit memory address
Tag field (n - k) : Index field (k)
2k words cache memory + 2n words main memory
Tag = 6 bit (15 - 9), Index = 9 bit

6 bits 9 bits
Tag Index

00 000 000
512×12
32K×12
Cache memory
Octal
Hex Main memory address
Address = 9 bits
Address
Data = 12 bits
1FF
Address = 15 bits
3F 1FF Data = 12 bits
 Direct Mapping Direct mapping cache with block size of
Memory Index 8 words :
address Memory data address Tag Data
000000 1220 000 00 1220 » 64 block x 8 word = 512
cache words size
Index Tag Data 6 6 3

00777 2340 000 01 3450 Tag Block Word

Block 0
01000 3450 007 01 6578
Index
010
Block 1
01777 4560 777 02 6710
017
02000 5670
(b) Cache memory

02777 6710

770 02
Block 63
777 02 6710
(a) Main memory
Set-Associative Mapping
Set-associative mapping : (two-way)

Index Tag Data Tag Data

000 01 3450 02 5670

777 02 6710 00 2340

 Questions
• A two-way set associative cache memory uses blocks of four words. The
cache can accommodate a total of 2048 words from main memory. The
main memory size is 128Kx32. Formulate all pertinent information required
to construct the cache memory. What is the size of cache memory.

• A computer has a memory unit of 64Kx16 and a cache memory of 1K

words. The cache uses direct mapping with a block size of four words. How
many bits are there in the tag, index, block, and words fields of the address
format. How many bits are there in each word of cache, and how are they
divided into functions? Include a valid bit. How many blocks can the cache
accommodate?

• The access time of a cache memory is 100ns and that of main memory is
1000ns. It is estimated that 80 percent of the memory requests are for read
and the remaining 20 percent for write. The hit ratio for read access only is
0.9. A write-through procedure is used. What is the average access time of
the system considering only memory read cycles. What is the average
access time of the system for both read and write requests. What is the hit
Answer
Answer
– Replacement Algorithm : cache miss or full
• 1) LRU (Least Recently Used):
• 2) Random Replacement:
• 3) FIFO (First-In First-Out) :

– Writing to Cache :
– 1) Write-through :
– 2) Write-back :

– Cache Initialization
• Cache is initialized :
– 1) When power is applied to the computer
– 2) When main memory is loaded with a complete set of
programs from auxiliary memory
– 3) Cache is initialized by clearing all the valid bits to 0.
 Virtual Memory

VIRTUAL MEMORY

Give the programmer the illusion that the system has a very large memory,
even though the computer actually has a relatively small main memory

Address Space(Logical) and Memory Space(Physical)

address space memory space

virtual address Mapping

(logical address) physical address

address generated by programs actual main memory address

 Virtual Memory

PAGE REPLACEMENT ALGORITHMS

FIFO Reference string
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 2 4 4 4 0 0 0 7 7 7
0 0 0 3 3 3 2 2 2 1 1 1 0 0
1 1 1 0 0 0 3 3 3 2 2 2 1
Page frames

FIFO algorithm selects the page that has been in memory the longest time

Optimal Replacement (OPT) - Lowest page fault rate of all algorithms

Replace that page which will not be used for the longest period of time
Reference string
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 2 2 2 7
0 0 0 0 4 0 0 0
1 1 3 3 3 1 1

Page frames
 Virtual Memory

PAGE REPLACEMENT ALGORITHMS

LRU
- OPT is difficult to implement since it requires future knowledge

Replace that page which has not been

used for the longest period of time

Reference string
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 4 4 4 0 1 1 1
0 0 0 0 0 0 3 3 3 0 0
1 1 3 3 2 2 2 2 2 7
Page frames
 Question
The page request are in following order. If
there are three memory frames, show the
execution of the following pages using
a. FIFO b. Optimal c. LRU

6 0 1 3 2 5 0 4 7 1 3 2 6 0 4
 Input-Output Organization

❑Peripheral Devices: Input & Output

devices attached to computer are called
Peripheral.
❑Input and output devices communicate
alphanumeric information by using ASCII
7bit code.
❑To use computer efficiently, large number
 Input-Output Interface
❑ The purpose of interfacing are as follows:
– Peripherals are electromechanical & electromagnetic devices
and are interacting with electronics devices(CPU).

– Data transfer rate of peripherals is usually slower than transfer

rate of CPU.

– Data codes and formats in peripherals differ from word format in

CPU

– Operating modes of peripherals are different from each other

and each one must be controlled without disturbing other.
 Input-Output Interface
❑ To resolve these differences, computer system includes
Interface units between CPU and peripherals to supervise and
synchronize all input and output transfers.

❑ Each peripheral has its own controller that operates a

particular electromechanical device.

❑ To communicate with a particular device, the processor

places a device address on the address lines.
Input-Output Interface
 Input-Output Interface

❑When the interface detects it own address,

it activates path between bus lines and the
device.
❑At the time address is made available in
address lines, the processor provides
function code(I/O command) in the control
lines.
 I/O versus Memory Bus
❑ In addition to communicating to I/O, processor must also
communicate with memory unit.

❑ There are three ways that computer buses can be used to

communicate with memory and I/O:
❖ Use two separate buses, one for memory and one for I/O. (IOP)

❖ Use one common bus for both memory and I/O but have
separate control lines for each. (Isolated I/O)

❖ Use one common bus for memory and I/O with common control
lines. (Memory Mapped I/O)
 Input-Output Transfer (IOP)
❑An IOP takes care of input and output tasks.
❑The CPU is assigned the task of initiating all
operations, but I/O instructions are executed
in IOP.
❑When an I/O operation is required, the CPU
informs the IOP where to find the I/O
program and then leaves the transfer details
to the IOP.
Input-Output Transfer (IOP)
 Isolated I/O
❑The distinction between memory and I/O
transfer is made through separate read and
control lines.

❑I/O read and I/O write are enabled during I/O

transfer and Memory read/write are enabled
during memory transfer.

❑In the isolated I/O configuration, CPU have

 Isolated I/O
❑When the CPU fetches and decodes the
Memory instruction, it places the address
associated with the instruction on the
common address lines and enables Memory
read or Memory write control line.

❑The isolated I/O method isolates memory

and I/O addresses.
 Memory Mapped I/O

❑In this configuration, same address space

is used for both memory and I/O.

❑The computer treats interface register

(I/O) as a part of memory system.

❑The assigned address cannot be used for

storing memory words, which reduces
Memory Mapped I/O
 Modes of Transfer
• Data transfer between the CPU and the
I/O devices may be handled in variety of
modes. Some modes use the CPU as an
intermediate path and others transfer the
data directly to and from the memory unit.

• Data transfer to and from peripherals may

be handled in three ways:
– Programmed I/O
 Programmed I/O
• Programmed I/O operations are the result of
I/O instructions. Each data item transfer is
initiate by an instruction in the program.

• Usually the transfer is to and from a CPU

register and peripheral. Other instructions
are needed to transfer data between memory
and CPU.

• Once a data transfer is initiated, the CPU is

Programmed I/O
 Interrupt Initiated I/O
• In the programmed I/O CPU stays in
program loop until the I/O indicates that it
is ready for data transfer.

• This is time consuming process since it

makes CPU busy needlessly.

• This can be avoided by using an interrupt

facility.
Direct Memory Access (DMA)
• The transfer of data between a fast
storage device such as magnetic disk and
memory often limited to the speed of CPU.

• Removing the CPU and letting the

peripheral device manage the memory bus
directly improve speed of transfer.

• Such transfer technique is called Direct

Memory Access (DMA).
 DMA

• Data transfer ways:

– Burst Transfer: Here number of words are transferred in a block.

Example: Magnetic disk.

– Cycle stealing: Allows the DMA controller to transfer one data word
at a time after it must return the control of buses to CPU.
DMA Controller
 Initialization of DMA

• The CPU initializes the DMA by sending the following

information through the data bus.

– The starting address of the memory block where data are

available(for read) or where data are to be stored(for write).

– The word count, which is the number of words in the memory

block.

– Control to specify the mode of transfer such as read or write.

– A control to start the DMA transfer.

DMA Transfer in a computer
system
 Bus Arbitration
• The device that is allowed to initiate data
transfers on the bus at any given time is
called Bus master.

• Bus arbitration is the process by which the

next device becomes Bus master and will
do the data transfer.

• Two approaches: Centralized Arbitration

and Distributed Arbitration.
 Types of Interrupt
• Major types of Interrupt are:
– External Interrupt: It comes from I/O devices, from timing device, or
from any other external source.
– Internal Interrupt: It includes register overflow, invalid operation
code, stack overflow etc.
– Software Interrupt or Hardware Interrupt: External and Internal
interrupts are initiated from signals that occur in the hardware of
the CPU. A software interrupt is initiated by executing an
instruction.
– Priority Interrupt: In case several sources will request service
simultaneously, in this case system must decide which device to
service first. For ex: Polling, Daisy Chain.
 Buses
• Data Bus: Bi-directional and transfers data.
• Address Bus: Uni-directional and sends the
address.
• Control Bus: R/W, BR,BG etc.

• Bus Structure: Single bus

 Buses
• Bus Structure: Multi bus
 Synchronous or Asynchronous
Data Transfer
• Internal operations in a digital system are
synchronized by means of clock pulses
supplied by common pulse generator.

• If the registers in the interface share a

common clock with the CPU registers, the
transfer is synchronous.

• Asynchronous data transfer requires that

control signals be transmitted between
 Strobe Control
• Strobe control:
– It employs single control line.
– It can be activated either by source or destination unit.
Handshaking