Lesson 1.

2 Structure of HDL Module

CPEHDL 311
STRUCTURE OF HDL MODULE

 MODULE: THE WORD MEANING IS COMPARTMENTS OR PARTS, IT

MEANS “PARTS OF A HDL PROGRAM”.

 THE MODULES ARE DIFFERENT IN VHDL AND VERILOG HDL.

STRUCTURE OF THE VHDL MODULE:

VHDL module consists of 2 major parts. They are entity and architecture.

Entity:
It shows the inputs and outputs of the system to be described. Entity
is given an identifier (name) by the user. The inputs and the outputs are
called the input ports and the output ports. The inputs and the outputs are
named by the user.
 VHDL SYNTAX “ENTITY”

Things to remember:
1.The identifier name should start with
The syntax is as follows:
an alphabet and can have only one
special character ”_”.
entity <entityidentifier> is 2.VHDL is case insensitive. The different
port( <portidentifier>: in bit; types of ports are in, out, buffer, inout.
<portidentifier>: out bit); 3.Semi colon ; should be placed after
end <entityidentifier>; every executable line.
4.The word entity, port, end are
predefined words(key words).
VHDL SYNTAX “ARCHITECTURE”
• Example of Entity Architecture
Architecture includes details about
the relation between the inputs
and the outputs and must be entity example is
bound (meaning: attached) to an port (I1, I2 : in bit; O1, O2 : out bit);
entity. More than one architecture end;
can be bound to one entity.
architecture dtfl_ex of example is
begin
O1 <= I1 xor I2; -- statement 1
O2 <= I1 and I2; -- statement 2

end dtfl_ex;
STRUCTURE OF THE VERILOG MODULE
THE VERILOG MODULE HAS DECLARATION AND A BODY.

Declaration: The syntax is simpler than VHDL

In the declaration identifier, name of module <module identifier>

input, name of outputs are listed. (<input, output identifiers>);
input <identifier>;
output<identifier>;
endmodule
THE “BODY”

THE BODY SHOWS THE RELATION BETWEEN THE INPUTS AND

THE OUTPUTS.

Things to remember:
1.The identifier name should start with a alphabet and can have only one
special character ”_”.
2.Verilog HDL is case sensitive. The different types of ports are input,
output, inout.
3.Semi colon ; should be placed after every executable line.
4.The word module, assign, endmodule are predefined words(key words).
SAMPLE VERILOG CODING

module half_adder (I1, I2, O1, O2);

input I1;
input I2;
output O1;
output O2;
//Blank lines are allowed

assign O1 = I1 ^ I2; //statement 1

assign O2 = I1 & I2; //statement 2
endmodule
 MODULE OPERATORS AND DATA TYPES

OPERATORS

Operators perform
a wide range of
functions. In HDL
operators are classified
into 4 categories:
Logical operators:
These operators perform logical operations such as AND, OR, NOT,
NOR, NOT, EX-OR.
Logical Operators and Example
• AND: Performs a logical AND • NAND: Performs a logical NAND
operation. operation.
Ex: result <= A and B; // VHDL Ex: result <= not (A and B); // VHDL
result = A & B; // Verilog result = ~(A & B); // Verilog
• OR: Performs a logical OR • NOR: Performs a logical NOR
operation. operation.
Ex: result <= A or B; // VHDL Ex: result <= not (A or B); // VHDL
result = A | B; // Verilog result = ~(A | B); // Verilog
Logical Operators and Example (Cont)
• XOR: Performs a logical exclusive • NOT: Performs a logical negation.
OR operation.
• Ex: result <= not A; // VHDL
Ex: result <= A xor B; // VHDL
result = !A; // Verilog
result = A ^ B; // Verilog
Summary:
• (XNOR): Performs a logical •VHDL uses keywords like and, or, xor,
exclusive NOR operation. not, and their combinations (e.g., nand,
Ex: result <= not (A xor B);// VHDL nor).
result = ~(A ^ B);// Verilog •Verilog uses symbols like &, |, ^, !, and
their negations.
Relational operators:
Relational operators are used to compare the values of two objects.
The result is Boolean i.e true(1) or false(0).
VHDL Example Verilog Example
if A = B then if (A == B) begin
-- Execute logic if // Execute logic if
A equals B A equals B
elsif A < B then end else if (A < B)
begin
-- Execute logic if
A is less than B // Execute logic if
A is less than B
end if;
end
Arithmetic operators:
Arithmetic operators are used to perform a wide variety of
operations such as addition, subtraction, multiplication and division.
Summary

Operator Description VHDL Syntax Verilog Syntax

+ Addition C <= A + B; C = A + B;
- Subtraction C <= A - B; C = A - B;
* Multiplication C <= A * B; C = A * B;
/ Division C <= A / B; C = A / B;
mod Modulus (Remainder) C <= A mod B; C = A % B;
rem Remainder C <= A rem B; (Not explicitly available in Verilog)
** Exponentiation C <= A ** B; (Not available in Verilog)
Arithmetic Operators and Example

VHDL Verilog
signal A, B, C: integer; integer A, B, C;

C <= A + B; -- Addition C = A + B; // Addition

C <= A - B; -- Subtraction C = A - B; // Subtraction
C <= A * B; -- Multiplication C = A * B; // Multiplication
C <= A / B; -- Division C = A / B; // Division
C <= A mod B; -- Modulus C = A % B; // Modulus
(Remainder)
Shift and Rotate operators:
Shift operators are unary operators. They operate on single
operand. They are used to shift the bits by some positions.
VHDL Shift and Rotate Operators Example
• Logical Shift left • Arithmetic Shift Left • Rotate Left
result <= A sll B; //VHDL result <= A sla B; //VHDL result <= A rol B;//VHDL
result = A << B; //Verilog result = A >>> B; //Verilog result = {A[SIZE-2:0],
A[SIZE-1]}; //Verilog

• Logical Shift Right

• Rotate
result <= A srl B; //VHDL
result <= A ror B;//VHDL
result = A >> B; //Verilog
result = {A[0], A[SIZE-1:1]};
//Verilog
Summary
• Shift Operators are used to move bits left or right, with different
behaviors for preserving the sign in arithmetic shifts.
• Rotate Operators achieve circular shifting of bits, where bits shifted
out on one end are reintroduced on the other. VHDL requires
manual implementation using concatenation, while Verilog supports
it directly.
Next topic: Data types and Description in VHDL and Verilog