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RISC Programming
Problem 1 Consider the load/store architecture, where only load and store instructions move data between the registers and memory. The following table gives some sample instructions for a load/store machine. Using the instructions, write a code that will emulate the following expression. Note you have only two size- independent registers, R1 and R2, available in the machine.
Expression: A = B + C * D – E + F + A
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RISC Programming
Solution
load R1,C ; load C
load R2,D ; load D mult R1,R1,R2 ; R1 = C*D load R2,B ; load B add R1,R1,R2 ; R1 = B + C*D load R2,E ; load E sub R1,R1,R2 ; R1 = B + C*D - E load R2,F ; load F add R1,R1,R2 ; R1 = B + C*D - E + F load R2,A ; load A add R1,R1,R2 ; R2 = B + C*D - E + F + A store A,R1 ; store the result in A
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RISC Programming
Problem 2 Now consider each load and store instruction takes two memory accesses: one to fetch the instruction and the other to access the data value. The arithmetic instructions need only one memory access to fetch the instruction as the operands are in registers. How many memory access will be required to compute the code in Problem 1?
Solution
Instruction Type No. of occurrence Memory access/ per instruction Total
Load 6 2 12
Store 1 2 2
Add 3 1 3
Sub 1 1 1
Mult 1 1 1
Grand Total 19
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Pipelining
Problem 3 For R-type instructions, pipelining will require only 4 stages: IF, ID, EX, and WB (MEM is not required). What will happen if we try to pipeline loads of the following program? Note that each functional unit can only be used once per instruction. In case of a clash, how to solve it?
Instruction Steps required
add $sp, $sp, -4 beq IF ID EX sub $v0, R-type IF ID EX WB $a0, $a1 sw IF ID EX MEM lw $t0, lw IF ID EX MEM WB 4($sp) or $s0, $s1, $s2 lw $t1, 8($sp)
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Pipelining
Solution 3
All arithmetic or logical instructions are R-type instructions since it will operate only on registers.
Given the pipelining data, we can fill the clock cycles using the pipelining stages as:
Clock cycle 1 2 3 4 5 6 7 8 9 add $sp, $sp, IF ID EX WB -4 sub $v0, IF ID EX WB $a0, $a1 lw $t0, IF ID EX ME WB 4($sp) M or $s0, $s1, IF ID EX WB $s2 lw $t1, IF ID EX MEM WB 8($sp)
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Pipelining
Solution 3 continued… Clock cycle
1 2 3 4 5 6 7 8 9 add $sp, $sp, IF ID EX WB Clash -4 sub $v0, IF ID EX WB $a0, $a1 lw $t0, IF ID EX ME WB 4($sp) M or $s0, $s1, IF ID EX WB $s2 How to solve it? lw • Enforce$t1, uniformity IF ID EX MEM WB 8($sp) • Make all instructions take 5 cycles in pipelining. • Make them have the same stages in the same order • Some stages will do nothing for some instructions: NOP state • Revised R-type instruction pipelining stage
R-type IF ID EX NOP WB
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Solution 3 continued…
Revised instruction pipelining stages will be
Clock cycle 1 2 3 4 5 6 7 8 9 add $sp, $sp, IF ID EX NOP WB -4 sub $v0, IF ID EX NOP WB $a0, $a1 lw $t0, IF ID EX ME WB 4($sp) M or $s0, $s1, IF ID EX NOP WB $s2 lw $t1, IF ID EX MEM WB 8($sp) Note: Store and branch instructions also have NOP stages too…
store IF ID EX MEM NOP
branch IF ID EX NOP NOP 9
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Multiplication - Rules 1. LSB of multiplier is 1 – write down the multiplicand and shift left by one place
2. LSB of multiplier is 0 – write down as many zeros as size of
multiplicand and shift left by one place
3. For each bit of multiplier repeat either (1) or (2)
4. Add all partial products
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Multiplication
• Multiply two n- bit numbers results in a
maximum of 2n bit number. • Multiply a m-bit number by n-bit result in a maximum of m+n bit number
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Computer Arithmetic • Multiplication Example 1: (1010)2 × (1101)2
Machine Implementation Pen and Pencil Method
12
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Exercises • Multiplication: Booth’s Algorithm
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• Example: Booth’s Algorithm (7× 3)
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Restoring Division
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION Exercises
Practice Problems • -5 7 • -5 -8 • 39 6
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