Instruction Set-II (1)

ARM INSTRUCTION SET-II
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CONTENTS
• Branch Instructions
• Load Store Instructions
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BRANCH INSTRUCTIONS
• A branch instruction changes the flow of

execution or is used to call a routine.
• The change of execution flow forces the
program counter pc to point to a new address.
• This type of instruction allows programs to
have
• subroutines,
• if-then-else structures, and
• loops.
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The ARM instruction set includes four different
branch instructions.
SYNTAX: B{<cond>} label
BL{<cond>} label
BX{<cond>} Rm
BLX{<cond>} label | Rm
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 T refers to the Thumb bit in the cpsr.
When instructions set T, the ARM switches to
Thumb state.
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An Illustration Of Branch Instruction
 This example shows a forward and backward branch. The
forward branch skips three instructions. The backward
branch creates an infinite loop.
 B forward
ADD r1, r2, #4
ADD r0, r6, #2
ADD r3, r7, #4
forward
SUB r1, r2, #4
backward
ADD r1, r2, #4
SUB r1, r2, #4
ADD r4, r6, r7
B backward 6
• Most assemblers hide the details of a branch
instruction encoding by using labels.
• Here forward and backward are the labels.
• Labels are placed at the beginning of the line
and are used to mark an address that can be
used later by the assembler to calculate the
branch offset.
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CONTD….BL Branch Instruction
 The branch with link, or BL, instruction is similar to the B
instruction but overwrites the link register lr with a return
address. It performs a subroutine call.
 To return from a subroutine, you copy the link register to
the pc.
 BL subroutine ; branch to subroutine
CMP r1, #5 ; compare r1 with 5
MOV EQ r1, #0 ; if (r1==5) then
r1 = 0
:
subroutine
<subroutine code>
MOV pc, lr ; return by moving pc =
lr 8
CONTD….
The branch exchange (BX) and branch exchange with

link (BLX) are the third type of branch instruction.
The BX instruction uses an absolute address stored in
register Rm. It is primarily used to branch to and from
Thumb code.
The T bit in the cpsr is updated by the least significant bit
of the branch register.
Similarly the BLX instruction updates the T bit of the
cpsr with the least significant bit and additionally sets the
link register with the return address
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LOAD STORE INSTRUCTIONS
Load-store instructions transfer data between

memory and processor registers.
There are three types of load-store instructions:
 stack
 swap
 single-register transfer
 multiple-register transfer
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STACK OPERATIONS
• The ARM architecture uses the load-store multiple

instructions to carry out stack operations.
• The pop operation (removing data from a stack)
uses a load multiple instruction;
• The push operation (placing data onto the stack)
uses a store multiple instruction.
• When using a stack you have to decide whether
the stack will grow up or down in memory.
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CONTD….
 A stack is either ascending (A) or descending (D).

Ascending stacks grow towards higher memory
addresses
Descending stacks grow towards lower memory
addresses.
When you use a full stack (F), the stack pointer sp
points to an address that is the last used or full location
(i.e., sp points to the last item on the stack).
If you use an empty stack (E) the sp points to an
address that is the first unused or empty location (i.e., it
points after the last item on the stack).
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• There are a number of load-store multiple
addressing mode aliases available to support stack
operations.
• In Fig,next to the pop column is the actual load
multiple instruction equivalent.
• For example, a full ascending stack would have
the notation FA appended to the load multiple
instruction—LDMFA. This would be translated
into an LDMDA instruction
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The STMFD instruction pushes registers onto the
stack, updating the sp. A push onto a full
descending stack. You can see that when the stack
grows the stack pointer points to the last full entry
in the stack.
PRE r1 = 0x00000002
r4 = 0x00000003
sp = 0x00080014
STMFD sp!, {r1,r4}
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ARM has specified an ARM-Thumb Procedure
Call Standard (ATPCS) that defines how routines
are called and how registers are allocated. In the
ATPCS, stacks are defined as being full descending
stacks.
 Thus, the LDMFD and STMFD instructions
provide the pop and push functions, respectively
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SWAP INSTRUCTIONS
The swap instruction is a special case of a load-store

instruction.
It swaps the contents of memory with the contents of
a register.
This instruction is an atomic operation—it reads and
writes a location in the same bus operation,
preventing any other instruction from reading or
writing to that location until it completes.
Swap cannot be interrupted by any other instruction
or any other bus access. We say the system “holds
the bus” until the transaction is complete.
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CONTD…
Syntax: SWP{B}{<cond>} Rd,Rm,[Rn]
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An Illustration Of Swap Instruction
PRE
mem32[0x9000] = 0x12345678
r0 = 0x000000
r1 = 0x11112222
r2 = 0x00009000
SWP r0, r1, [r2]
POST
mem32[0x9000] = 0x11112222
r0 = 0x12345678
r1 = 0x11112222
r2 = 0x00009000
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CONTD…
The swap instruction loads a word from memory

into register r0 and overwrites the memory with
register r1.
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Program Status Register Instructions
• The ARM instruction set provides two instructions to directly
control a program status register (psr).
• The MRS instruction transfers the contents of either the cpsr or spsr
into a register and vice versa.
• MSR instruction
- Transfer the contents of general-purpose register to PSR.
• Together these instructions are used to read and write the cpsr and
spsr.
• Fields can be any combination of control(c), extension (x), status (s),
and flags (f ). These fields relate to particular byte regions in a psr.
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• Syntax: MRS{<cond>} Rd,<cpsr|spsr>
• MSR{<cond>} <cpsr|spsr>_<fields>,Rm
• MSR{<cond>} <cpsr|
spsr>_<fields>,#immediate
PSR byte fields
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ARM INSTRUCTION SET-II

• A branch instruction changes the flow of

The branch exchange (BX) and branch exchange with

Load-store instructions transfer data between

• The ARM architecture uses the load-store multiple

 A stack is either ascending (A) or descending (D).

The swap instruction is a special case of a load-store

Syntax: SWP{B}{<cond>} Rd,Rm,[Rn]

The swap instruction loads a word from memory

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