MPMC-1

Microprocessor Architecture
1
Historical Background
• The Mechanical Age
• The Electrical Age
• The Microprocessor Age
• The Intel Age – The Modern Microprocessor
– 1970s
– 1980s
– 1990s
– 2000s
The Mechanical Age
Dream: calculating with a machine

•The idea of computing system existed long before modern electrical and
electronics devices were developed.
•The idea of calculating with a machine dates to 500 BC when the

Babylonians invented the abacus, the first mechanical calculator, Abacus-string
of beads used to perform calculations.
Babylonians invented the calculating device Abacus
4
The mathematician Blaise Pascal invented a calculator in 1642
that was constructed of gears and wheels
5
In the early 1870s, Bomar introduced the first small hand –held electronic calculator.
In 1889, Herman Hollerith developed the punched card for storing data.
In 1896, Hellerith formed a company called the Tabulating Machine Company, which
developed a line of machines that was used punched cards for tabulation.
After a number of mergers, the Tabulating Machine Company was formed into
International Business machines Corporation, now it is referred more commonly as
IBM.
The punched cards used in computer systems are often called Hollerith cards.
6
• The first Electronic calculating machine was invented by Konrad Zuse
(German) in 1941. It has recently been discovered that the first electronic
computer was placed into operation in 1943.This first electronic
computing system, which used Vacuum tubes, was invented by Alan
Turing .It was a fixed program computer system, today which is often
called a special- purpose compute
• The first general –purpose programmable electronic computer system was

developed in 1946 at the University of Pennsylvania. The first modern
computer was called the ENIAC (Electronics Numerical Integrator and
Calculator).The ENIAC was a huge machine, containing over 17,000
vacuum tubes and over 500 miles of wires. This machine weighted over 30
tons, yet performed only about 1, 00,000 operations per second. Another
problem with the ENIAC was the life of the vacuum tube components,
which required frequent maintenance
7
8
The Electrical Age
•First electronic (digital ) computer- ENIAC-(Electronic numerical integrator
calculator)
• Designed and developed at the U. of Pennsylvania, 1946
• contained over 18,000 vacuum tubes, weighed more than 30 tons, and
required 1500 square feet of floor space and over 500 miles of wires
• It was programmed by setting up to 6000 switches and connecting cables

between the various units of the computer.
• first modern (general-purpose, programmable) electronic computer

performing about 100,000 operations per second
• programmed by rewiring its circuits

The Microprocessor Age
• Before the invention of microprocessors, most digital design problems were

solved using the same set of tools.
• Combinational circuits were derived from Boolean logic equations, truth

tables, and Karnaugh maps.
• Sequential designs utilized flip-flop excitation tables and state diagrams.
• Designers then chose “off the shelf” logic components —typically 7400
family integrated circuits—to implement these equations in hardware.
• If the design specifications changed, the process was repeated and the
hardware was modified or rebuilt.
The Microprocessor Age cotd..
• Release of a new logic component called the microprocessor in the early

1970s changed all of this.
• Rather than implement a rigid set of logic equations, the microprocessor

fetches from a memory unit,
“instructions” about the problem to be solved.
• These instructions are called the control program. Release of a new
• A microcomputer system is built around the microprocessor.

Microprocessor Fifth Generation Pentium
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 12
multiplexed Intel 8085 (8 bit processor)
After development of Transistors in 1948 at Bell Labs and
invention of the Integrated Circuits in 1958 by Jack Kilby of
Texas Instruments.
The Intel Corporation introduced the first Microprocessor

4004 in 1971.
The device that started the Microprocessor revolution that

continues today at an ever-accelerating pace.
13
Intel 4004- 4 bit
• World’s First microprocessor released in 1971
• Could execute 45 instructions
• 4096 location addressable (4 Kbytes) (212)
• Weighed much less than one ounce  28gms.
• Initial clock speed: 108KHz
• Transistors: 2,300
Intel 4040- 4 bit
• Later Intel released 4040, updated version of 4004,

which operated at higher speed
• Initial clock speed: 800 kHz
• Transistors-3500
• Lacked improvement in the word width and memory
size. (4 bit, 4 Kbytes of memory)
Intel 8008- 8 bit
• Introduced in 1972
• Could execute 16kbytes of memory and
48 instructions.
• Initial clock speed-2 MHz
• Transistors-4500
•Limitations:
• small memory size, slow speed, limited
instruction set
• To overcome the limitations, Intel released 8080,Ist
modern 8bit microprocessor-1973
• About 6 months later Motorola released MC6800,
other companies began to release their own versions
of 8 bit microprocessor.
Block diagram of Simple micro
computer
17
Block diagram of Microprocessor based computer system
18
Microprocessor Functional blocks
Various conditions of the

Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register
Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP
Control Bus Address Bus
Generates control signals for

internal and external Decodes instructions; sends
operations of the information to the timing and
control unit 19
microprocessor
Historical Perspective
20
8086
Microprocessor Overview
First 16- bit processor released by Addressable memory space is

INTEL in the year 1978 organized in to two banks of 512 kb
each; Even (or lower) bank and Odd (or
higher) bank. Address line A0 is used to
Originally HMOS, now manufactured select even bank and control signal
using HMOS III technique is used to access odd bank
Uses a separate 16 bit address for I/O

Approximately 29, 000 transistors, 40 mapped devices  can generate 216 =
pin DIP, 5V supply 64 k addresses.
Operates in two modes: minimum

Does not have internal clock; external mode and maximum mode, decided by
asymmetric clock source with 33% duty the signal at MN and pins.
cycle
20-bit address to access memory  can

address up to 220 = 1 megabytes of
memory space.
21
Types of Architecture
●What is architecture?
● Types
Harvard Architecture- Separate Program memory
and data memory
Von Neumann Architecture- Same memory space

for Program and Data storage
22
Von Neumann and Harvard Architecture
23
Comparison between Von Neumann and
Harvard architecture
Aspect Von Neumann Architecture Harvard Architecture
Single memory for instructions Separate memory for instructions

Memory
and data and data
CPU accesses instructions and CPU accesses instruction and data

Access
data through a shared bus memory spaces separately
Can become a bottleneck if too Improved performance because the

Performance many devices are connected to CPU can access both instruction and
the shared bus data memory simultaneously
Easier to modify programs as More difficult to modify programs

Modification instructions and data are stored in that require the CPU to modify its
the same memory own code
Easy to share data between More difficult to share data between

Data sharing different parts of a program. different parts of a program.
It uses CISC Architecture It uses RISC Architecture
Suitable for general-purpose Suitable for embedded systems

Applications computing where flexibility is where performance is critical and
required code is not frequently modified
General purpose micro controllers,

Examples 8085, 8086, MC6800
Special DSP chips etc 24
MICROPROCESSORS Vs MICROCONTROLLERS
S.No Microprocessors Microcontrollers

Microprocessor is the heart of the
Microcontroller is the heart of the embedded
computer system, which fetches the
1 system, designed to perform a specific task
instructions from memory and
by executing a fixed program stored in ROM
executes them.
µp is a central processing unit µc has a CPU, in addition with RAM, ROM

(CPU) on a single chip, which and other peripherals like I/O ports, Serial
2
consists of ALU, Registers, and port, Timers/Counters, Interrupt controller,
Timing and control units. etc all embedded on a single chip
3 Less no. of on-chip registers More no. of on-chip registers

Less no. of Bit manipulation
4 More no. of Bit manipulation instructions
instructions
Size, power and cost of the system
Low size, Low power and Low cost, due to
5 increases due to external
less no. of external components.
components.
Microprocessors are used for
Microcontrollers are used for executing
6 executing general purpose
specific applications.
applications
Used in desktop PC's, Laptops, Used in embedded applications like Washing
7
Notepads etc machine, DVD player, AC, etc
25
Introduction 8085
• Intel 8085 is an 8 bit microprocessor

introduced by Intel in 1977.
• The 8085 follows the von Neumann
architecture with a 16 bit address
bus and 8 bit data bus.
• It can access 216 (65536) individual 8
bit memory locations (64KB)
• Has built in register:
– A (accumulator), B,C,D,E,H and L (8 bit)
– Special purpose register: 16 bit program
counter, stack pointer, and 8 bit flag
register 26
Intel 8085
27
28
Reduced Instruction Set Architecture (RISC)

The main idea behind this is to simplify hardware by using an
instruction set composed of a few basic steps for loading,
evaluating, and storing operations just like a load command will
load data, a store command will store the data.
Characteristics of RISC
•Simpler instruction, hence simple instruction decoding.
•Instruction comes undersize of one word.
•Instruction takes a single clock cycle to get executed.
•More general-purpose registers.
•Simple Addressing Modes.
•Fewer Data types.
•A pipeline can be achieved
29
Advantages of RISC
•Simpler instructions: RISC processors use a smaller set of simple
instructions, which makes them easier to decode and execute quickly.
This results in faster processing times.
•Faster execution: Because RISC processors have a simpler instruction
set, they can execute instructions faster than CISC processors.
•Lower power consumption: RISC processors consume less power than
CISC processors, making them ideal for portable devices.
Disadvantages of RISC
•More instructions required: RISC processors require more instructions
to perform complex tasks than CISC processors.
•Increased memory usage: RISC processors require more memory to
store the additional instructions needed to perform complex tasks.
•Higher cost: Developing and manufacturing RISC processors can be
more expensive than CISC processors.
30
Complex Instruction Set Architecture (CISC)
The main idea is that a single instruction will do all loading,

evaluating, and storing operations just like a multiplication
command will do stuff like loading data, evaluating, and storing it,
hence it’s complex.
Characteristics of CISC
•Complex instruction, hence complex instruction decoding.
•Instructions are larger than one-word size.
•Instruction may take more than a single clock cycle to get
executed.
•Less number of general-purpose registers as operations get
performed in memory itself.
•Complex Addressing Modes.
•More Data types.
31
Complex Instruction Set Architecture (CISC)
Advantages of CISC
•Reduced code size: CISC processors use complex instructions that
can perform multiple operations, reducing the amount of code
needed to perform a task.
•More memory efficient: Because CISC instructions are more
complex, they require fewer instructions to perform complex tasks,
which can result in more memory-efficient code.
•Widely used: CISC processors have been in use for a longer time
than RISC processors, so they have a larger user base and more
available software.
Disadvantages of CISC
•Slower execution: CISC processors take longer to execute
instructions because they have more complex instructions and need
more time to decode them.
•More complex design: CISC processors have more complex
instruction sets, which makes them more difficult to design and
manufacture.
•Higher power consumption: CISC processors consume more
32
power than RISC processors because of their more complex
Pins and signals
8086
Microprocessor Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are

multiplexed with data.
When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.
When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are

multiplexed with status signals
34
8086
BHE (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the

processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation.

It is an output signal.
It is active when low.
35
8086
TEST
input is tested by the ‘WAIT’ instruction.
8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the is
made low by an active hardware.
This is used to synchronize an external

activity to the processor internal
operation.
READY
This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.
The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high. 36

8086
RESET (Input)
Causes the processor to immediately

terminate its present activity.
The signal must be active HIGH for at

least four clock cycles.
CLK
The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.
INTR Interrupt Request
This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request
is pending, the processor enters the
interrupt acknowledge cycle.
This signal is active high and internally

synchronized. 37
8086
Microprocessor Pins and Signals Min/ Max Pins
The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.
In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.
Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.
38
8086
Microprocessor Pins and Signals Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ is tied to

VCC (logic high)
8086 itself generates all the bus control signals
DT/ (Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers
(Data Enable) Output signal from the processor

used as out put enable for the transceivers
ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches
M/ Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.
Write control signal; asserted low Whenever

processor writes data to memory or I/O port
(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
39
8086
Microprocessor Pins and Signals Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ is tied to

VCC (logic high)
8086 itself generates all the bus control signals
HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.
Usually used by the DMA controller to get the

control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the
control of the bus through HOLD.
The acknowledge is asserted high, when the

processor accepts HOLD.
40
8086
Microprocessor Pins and Signals Maximum mode signals
During maximum mode operation, the MN/ is

grounded (logic low)
Pins 24 -31 are reassigned
,, Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.
41
8086

, (Queue Status) The processor provides the status

of queue in these lines.
The queue status can be used by external device

to track the internal status of the queue in 8086.
The output on QS0 and QS1 can be interpreted as

shown in the table.
42
8086

, (Bus Request/ Bus Grant) These requests are used

by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.
These pins are bidirectional.
The request on will have higher priority than
An output signal activated by the LOCK prefix

instruction.
Remains active until the completion of the

instruction prefixed by LOCK.
The 8086 output low on the pin while executing

an instruction prefixed by LOCK to prevent other
bus masters from gaining control of the system
bus.
43
Architecture
8086
Execution Unit (EU) Bus Interface Unit (BIU)
EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
45
8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Dedicated Adder to
generate 20 bit address
Four 16-bit segment

registers
Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Segment Registers >> 46

8086
Microprocessor
Segment
Registers
8086’s 1-megabyte The 8086 can directly Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.
47
8086
Microprocessor
Segment Code Segment Register

Registers
16-bit
CS contains the base or start of the current code

segment; IP contains the distance or offset from this
address to the next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then
offset is added provided by the IP.
48
8086
Microprocessor
Segment Data Segment Register

Registers
16-bit
Points to the current data segment; operands for most

instructions are fetched from this segment.
The 16-bit contents of the Source Index (SI) or Destination

Index (DI) or a 16-bit displacement are used as offset for
computing the 20-bit physical address.
49
8086
Microprocessor
Segment Stack Segment Register

Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the
Base Pointer (BP).
50
8086
Microprocessor
Segment Extra Segment Register

Registers
16-bit
Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.
String instructions use the ES and DI to determine the 20-

bit physical address for the destination.
51
8086
Microprocessor
Segment Instruction Pointer

Registers
16-bit
Always points to the next instruction to be executed

within the currently executing code segment.
So, this register contains the 16-bit offset address

pointing to the next instruction code within the 64Kb of
the code segment area.
Its content is automatically incremented as the execution

of the next instruction takes place.
52
8086
Microprocessor
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.
This mechanism is known

as pipelining.
53
8086
Architecture Execution Unit (EU)
Microprocessor
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
16-bit ALU for

performing arithmetic
and logic operation
Four general purpose

registers(AX, BX, CX, DX);
Pointer registers (Stack

Pointer, Base Pointer);
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 54
DX can be used as DH and DL
8086
Microprocessor
EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,

and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or

AL.
55
8086
Microprocessor
EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.
This is the only general purpose register whose contents

can be used for addressing the 8086 memory.
All memory references utilizing this register content for

addressing use DS as the default segment register.
56
8086
Microprocessor
EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte

of the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.
Example:
The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.
If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.
57
8086
Microprocessor
EU Data Register (DX)

Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
When combined, DL register contains the low order byte

of the word, and DH contains the high-order byte.
Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 16 division and the 16-bit reminder after division.
58
8086
Microprocessor
EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during

execution of instructions that involve the stack segment
in the external memory.
SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.
BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.
59
8086
Microprocessor
EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.
60
8086
Microprocessor
EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.
61
8086
Microprocessor
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case of
subtraction. subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 62
8086
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register

63
8086
Microprocessor Architecture Registers and Special Functions
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations
BX Base register Used to hold base value in base addressing mode

to access memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions
DX Data Register Used to hold data for multiplication and division

operations
SP Stack Pointer Used to hold the offset address of top stack

memory
BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory
SI Source Index Used to hold index value of source operand (data)

for string instructions
DI Data Index Used to hold the index value of destination

operand (data) for string operations 64
ADDRESSING MODES
&
Instruction set
8086
Microprocessor Introduction
Program
A set of instructions written to solve
a problem.
Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.
Computer language
High Level Low Level
Machine Language Assembly Language
 Binary bits  English Alphabets

 ‘Mnemonics’
 Assembler
Mnemonics  Machine
Language 66
Program Development Steps
Major steps in developing an assembly

language program
• Defining the Problem
• Representing program operations
• Finding the right instructions
• Writing a program
68
Defining the problems
• Find out the problem.
For example:
Sensing temperature,
detecting fire,
detecting smock,
decoder-encoder,
Intelligent machine controller etc.
69
Representing program operations
• Formula or sequence of operations

used to solve a programming problem is
called as the
algorithm.
• There are two ways of representing

algorithms:
- Flowchart
- Structured programming and pseudo
code 70
Finding the right instructions
Instructions in 8086 are mainly divided into
following categories
• Data Transfer Instructions

• Arithmetic Instruction
• Bit manipulation Instruction
• String Instruction
• Program execution transfer Instruction
• Processor control Instruction
71
Writing a program
• We need to do the following steps to write the program
effectively:
- INITIALIZATION INSTRUCTIONS: used to initialize various
parts of the program like segment registers, flags and
programmable port devices.
- STANDARD PROGRAM FORMAT: it’s a tabular format

containing ADDRESS, DATA OR CODE, LABELS, MNEM,
OPERAND(S) and COMMENTS as the columns.
- DOCUMENTATION: you should document the program. E.g.

each page of the document contains page number and name of the
program, heading block containing the abstract about the program,
comments should be added wherever necessary.
72
ADDRESSING MODES
8086
Microprocessor Addressing Modes
Every instruction of a program has to operate on a data.

The different ways in which a source operand is denoted
in an instruction are known as addressing modes.
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports
11. Relative Addressing Group IV : Relative Addressing mode
12. Implied Addressing Group V : Implied Addressing mode

74
8086 Group I : Addressing modes for
Microprocessor Addressing Modes register and immediate data
1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL
7. Based Index Addressing (CL)  (DH)
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
75
8086 Group I : Addressing modes for
Microprocessor Addressing Modes register and immediate data
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
Example:
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
7. Based Index Addressing (DL)  08H

MOV AX, 0A9FH
10. Indirect I/O port Addressing The 16-bit data (0A9FH) given in the instruction is
moved to AX register
(AX)  0A9FH
76
8086
Microprocessor Addressing Modes : Memory Access
20 Address lines  8086 can address up to

220 = 1M bytes of memory
However, the largest register is only 16 bits
Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto the
address bus.
Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)
Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 16 10), then add the contiguous memory
required offset to form the 20- bit address
89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
78
8086 Group II : Addressing modes
Microprocessor Addressing Modes for memory data
2. Immediate Addressing
Here, the effective address of the memory
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
The square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location. When
executed, this instruction will copy the contents
11. Relative Addressing of the memory location into BX register.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
80
1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.
3. Direct Addressing Registers used to hold EA are any of the following

registers:
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
address calculation.
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer
MOV CX, [BX]
to content of register/
9. Direct I/O port Addressing memory
Operations:
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA +1)
81
1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-
2. Immediate Addressing bit or unsigned 16-bit displacement will be
specified in the instruction.
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.
5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is
used.
Example:
MOV AX, [BX + 08H]
Operations:
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA
(AX)  (MA) or,
(AL)  (MA) 82
(AH)  (MA + 1)
1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.
5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.

Example:
MOV CX, [SI + 0A2H]
Operations:
FFA2H  A2H (Sign extended)
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA + 1)
83
1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
Example:
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
000AH  0AH (Sign extended)
8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA
(DX)  (MA) or,
(DL)  (MA)
12. Implied Addressing (DH)  (MA + 1)
84
1. Register Addressing Employed in string operations to operate on

string data.
The effective address (EA) of source data is
3. Direct Addressing stored in SI register and the EA of destination is
stored in DI register.
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES

Example: MOVS BYTE
Operations:
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA
11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) +85 1
8086 Group III : Addressing
Microprocessor Addressing Modes modes for I/O ports
1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.
4. Register Indirect Addressing Example: IN AL, [09H]
5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
7. Based Index Addressing Content of port with address 09H is

moved to AL register
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)
(PORT)  (AX)
Content of AX is moved to port

whose address is specified by DX
register. 86
8086 Group IV : Relative
Microprocessor Addressing Modes Addressing mode
3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
Operations:
8. String Addressing 000AH  0AH (sign extend)
9. Direct I/O port Addressing If ZF = 1, then
10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
MA = BA + EA
If ZF = 1, then the program control jumps to
new address calculated above.
If ZF = 0, then next instruction of the

program is executed.
87
8086 Group IV : Implied
Microprocessor Addressing Modes Addressing mode
5. Based Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
operated by the instruction.
Example: CLC
This clears the carry flag to zero.
88
INSTRUCTION SET
8086
Microprocessor Instruction Set
8086 supports 6 types of instructions.
1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. String manipulation Instructions
5. Process Control Instructions
6. Control Transfer Instructions
90
8086
Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.
Generally involve two operands: Source operand and

Destination operand of the same size.
Source: Register or a memory location or an immediate data

Destination : Register or a memory location.
The size should be a either a byte or a word.
A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.
91
8086
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem
MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)
MOV reg/ mem, data
MOV reg, data (reg)  data

MOV mem, data (mem)  data
XCHG reg2/ mem, reg1
XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)
92
8086
PUSH reg16/ mem
PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)
PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)
POP reg16/ mem
POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2
POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2 93
8086
IN A, [DX] OUT [DX], A
IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)
IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)
IN A, addr8 OUT addr8, A
IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)
IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)
94
8086
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem
ADC reg2, reg1 (reg2)  (reg1) + (reg2)

ADC reg2, mem (reg2)  (reg2) + (mem)
ADC mem, reg1 (mem)  (mem)+(reg1)
ADD reg/mem, data
ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data
ADD A, data
ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16
95
8086
ADC reg2/ mem, reg1/mem
ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF
ADC reg/mem, data
ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF
ADDC A, data
ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF
96
8086
SUB reg2/ mem, reg1/mem
SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)
SUB reg/mem, data
SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data
SUB A, data
SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16
97
8086
SBB reg2/ mem, reg1/mem
SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF
SBB reg/mem, data
SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF
SBB A, data
SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF
98
8086
INC reg/ mem
INC reg8 (reg8)  (reg8) + 1
INC reg16 (reg16)  (reg16) + 1
INC mem (mem)  (mem) + 1
DEC reg/ mem
DEC reg8 (reg8)  (reg8) - 1
DEC reg16 (reg16)  (reg16) - 1
DEC mem (mem)  (mem) - 1
99
8086
MUL reg/ mem
MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)
MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
IMUL reg/ mem
IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)
IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
100
8086
DIV reg/ mem
DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder
For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
101
8086
IDIV reg/ mem
IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
102
8086
CMP reg2/mem, reg1/ mem
CMP reg2, reg1 Modify flags  (reg2) – (reg1)
If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0
CMP reg2, mem Modify flags  (reg2) – (mem)
If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0
CMP mem, reg1 Modify flags  (mem) – (reg1)
If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0
103
8086
CMP reg/mem, data
CMP reg, data Modify flags  (reg) – (data)
If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0
CMP mem, data Modify flags  (mem) – (mem)
If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0
104
8086
CMP A, data
CMP AL, data8 Modify flags  (AL) – data8
If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0
CMP AX, data16 Modify flags  (AX) – data16
If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0
105
8086
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
106
8086
107
8086
108
8086
109
8086
110
8086
111
8086
112
8086
113
8086
4. String Manipulation Instructions
 String : Sequence of bytes or words
 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.
 REP instruction prefix : used to repeat execution of string instructions
 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.
 Offset or effective address of the source operand is stored in SI register

and that of the destination operand is stored in DI register.
 Depending on the status of DF, SI and DI registers are automatically

updated.
 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.
 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.
114
8086

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE While CX  0 and ZF = 1, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) – 1
ZF = 0)
REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) - 1
ZF = 1)
115
8086

MOVS
MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
(MAE)  (MA)
If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1
MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1)  (MA; MA + 1)

116
8086

Compare two string byte or string word
CMPS
CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
Modify flags  (MA) - (MAE)
If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0
For byte operation

For word operation

117
8086

Scan (compare) a string byte or word with accumulator
SCAS
SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)
If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1
SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 2 118

8086

Load string byte in to AL or string word in to AX
LODS
LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)
If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1
LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)
If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2
119
8086

Store byte from AL or word from AX in to string
STOS
STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)
If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1
STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)
If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2
120
8086
5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1
CLC Clear CF  0
CMC Complement carry CF  CF/
STD Set direction flag DF  1
CLD Clear direction flag DF  0
STI Set interrupt enable flag IF  1
CLI Clear interrupt enable flag IF  0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
ESC opcode mem/ reg Used to pass instruction to a coprocessor

which shares the address and data bus
with the 8086
LOCK Lock bus during next instruction 121

8086
Transfer the control to a specific destination or target instruction

Do not affect flags
 8086 Unconditional transfers
CALL reg/ mem/ disp16 Call subroutine
RET Return from subroutine
JMP reg/ mem/ disp8/ disp16 Unconditional jump
122
8086

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions
Checks flags
If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP
123
8086

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions
Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0
JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or Jump if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not Jump if below Jump if not above
greater than or or equal
equal
JLE disp8 JNG disp8 JBE disp8 JNA disp8
Jump if less than Jump if not Jump if below or Jump if not above
or equal greater equal 124
8086
 8086 conditional branch instructions affecting individual

flags
JC disp8 Jump if CF = 1
JNC disp8 Jump if CF = 0
JP disp8 Jump if PF = 1
JNP disp8 Jump if PF = 0
JO disp8 Jump if OF = 1
JNO disp8 Jump if OF = 0
JS disp8 Jump if SF = 1
JNS disp8 Jump if SF = 0
JZ disp8 Jump if result is zero, i.e, Z = 1
JNZ disp8 Jump if result is not zero, i.e, Z = 1
125
Assembler directives
8086
Microprocessor Assemble Directives
Instructions to the Assembler regarding the program being

executed.
Control the generation of machine codes and organization of

the program; but no machine codes are generated for
assembler directives.
Also called ‘pseudo instructions’
Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
127
8086
DB Define Byte
DW Define a byte type (8-bit) variable
SEGMENT Reserves specific amount of memory

ENDS locations to each variable
ASSUME Range : 00H – FFH for unsigned value;

00H – 7FH for positive value and
ORG
END 80H – FFH for negative value
EVEN
EQU General form : variable DB value/ values
PROC
FAR Example:
NEAR
LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 128
8086
DB Define Word
DW Define a word type (16-bit) variable
SEGMENT Reserves two consecutive memory locations

ENDS to each variable
ASSUME Range : 0000H – FFFFH for unsigned value;

0000H – 7FFFH for positive value
ORG
END and 8000H – FFFFH for negative value
EVEN
EQU General form : variable DW value/ values
PROC
FAR Example:
NEAR
ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 129
8086
DB SEGMENT : Used to indicate the beginning of

a code/ data/ stack segment
DW
ENDS : Used to indicate the end of a code/
SEGMENT data/ stack segment
ENDS
General form:
ASSUME
ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
Segnam ENDS
ENDP
SHORT
MACRO User defined name of

the segment
ENDM 130
8086
DB Informs the assembler the name of the

program/ data segment that should be used
DW for a specific segment.
SEGMENT General form:

ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME
ORG
User defined name of
END Segment Register
the segment
EVEN
EQU
PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA
MACRO
ENDM 131
8086
ORG (Origin) is used to assign the starting address

DB
(Effective address) for a program/ data segment
DW END is used to terminate a program; statements

after END will be ignored
SEGMENT
ENDS EVEN : Informs the assembler to store program/
data segment starting from an even address
ASSUME
EQU (Equate) is used to attach a value to a
variable
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200 H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 132
8086
PROC Indicates the beginning of a procedure

DB
ENDP End of procedure
DW
FAR Intersegment call
SEGMENT
ENDS NEAR Intrasegment call
General form
ASSUME
ORG
procname PROC[NEAR/ FAR]
END
EVEN …
Program statements of the
…
EQU … procedure
Last statement of the

PROC RET
procedure
ENDP
FAR procname ENDP
NEAR
SHORT User defined name of

the procedure
MACRO
ENDM 133
8086
DB
Examples:
DW
SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is

ENDS declared as NEAR and so the assembler will
… code the CALL and RET instructions involved
… in this procedure as near call and return
ASSUME …
RET
ORG ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR RET
NEAR CONVERT ENDP
SHORT
MACRO
ENDM 134
8086
DB Reserves one memory location for 8-bit

signed displacement in jump instructions
DW
Example:
SEGMENT
ENDS
ASSUME JMP SHORT The directive will reserve one

AHEAD memory location for 8-bit
displacement named AHEAD
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM 135
8086
DB MACRO Indicate the beginning of a macro
DW ENDM End of a macro
SEGMENT General form:

ENDS
ASSUME macroname MACRO[Arg1, Arg2 ...]

Program
… statements in
ORG … the macro
END …
EVEN
EQU macroname ENDM
PROC
ENDP
FAR User defined name of
NEAR the macro
SHORT
MACRO
ENDM 136
137
Interfacing memory and i/o ports
8086
Microprocessor Memory
Processor Memory
 Registers inside a microcomputer
 Store data and results temporarily
 No speed disparity
 Cost 
Primary or Main Memory

 Storage area which can be directly
Memory accessed by microprocessor
 Store programs and data prior to
Store
execution
Programs  Should not have speed disparity with
and Data
processor  Semi Conductor
memories using CMOS technology
 ROM, EPROM, Static RAM, DRAM
Secondary Memory
 Storage media comprising of slow
devices such as magnetic tapes and
disks
 Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 139
8086
Microprocessor Memory organization in 8086
Memory IC’s : Byte oriented
8086 : 16-bit
Word : Stored by two

consecutive memory locations;
for LSB and MSB
Address of word : Address of

LSB
Bank 0 : A0 = 0  Even
addressed memory bank
Bank 1 : = 0  Odd
addressed memory bank
140
8086
Operation A0 Data Lines Used
1 Read/ Write byte at an even address 1 0 D7 – D 0
2 Read/ Write byte at an odd address 0 1 D15 – D8
3 Read/ Write word at an even address 0 0 D15 – D0
4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation

byte from odd bank is
transferred
1 0 D7 – D0 in first operation byte
from odd bank is transferred
141
8086
Available memory space = EPROM + RAM
Allot equal address space in odd and even

bank for both EPROM and RAM
Can be implemented in two IC’s (one for

even and other for odd) or in multiple IC’s
142
8086
Microprocessor Interfacing SRAM and EPROM
Memory interface  Read from and write in

to a set of semiconductor memory IC chip
EPROM  Read operations
RAM  Read and Write
In order to perform read/ write operations,
Memory access time  read / write time of

the processor
Chip Select (CS) signal has to be generated
Control signals for read / write operations
Allot address for each memory location
143
8086
Typical Semiconductor IC Chip
No of Memory capacity Range of

Address address in
pins hexa
In Decimal In kilo In hexa
20 220= 10,48,576 1024 k = 1M 100000 00000

to
FFFFF
144
8086
Memory map of 8086
EPROM’s are mapped at FFFFFH

 Facilitate automatic execution of monitor programs
and creation of interrupt vector table
RAM are mapped at the beginning; 00000H is allotted to

RAM
145
8086
Monitor Programs
 Programing 8279 for keyboard scanning and display

refreshing
 Programming peripheral IC’s 8259, 8257, 8255,

8251, 8254 etc
 Initialization of stack
 Display a message on display (output)
 Initializing interrupt vector table
Note : 8279 Programmable keyboard/ display controller
8257 DMA controller
8259 Programmable interrupt controller
8255 Programmable peripheral interface
146
8086
Microprocessor Interfacing I/O and peripheral devices
I/O devices
 For communication between microprocessor and

outside world
 Keyboards, CRT displays, Printers, Compact Discs

etc.
 Ports / Buffer IC’s

Microprocessor I/ O devices
(interface circuitry)
 Data transfer types

Memory mapped
Programmed I/ O
Data transfer is I/O mapped
accomplished through an I/O port
controlled by software
Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by 147
bypassing the
8086
Microprocessor 8086 and 8088 comparison
Memory mapping I/O mapping

20 bit address are provided for I/O 8-bit or 16-bit addresses are
devices provided for I/O devices
The I/O ports or peripherals can be Only IN and OUT instructions can be
treated like memory locations and used for data transfer between I/O
so all instructions related to device and processor
memory can be used for data
transmission between I/O device
and processor
Data can be moved from any Data transfer takes place only
register to ports and vice versa between accumulator and ports
When memory mapping is used for Full memory space can be used for
I/O devices, full memory address addressing memory.
space cannot be used for
addressing memory.  Suitable for systems which
require large memory capacity
 Useful only for small systems
where memory requirement is less
For accessing the memory mapped For accessing the I/O mapped
devices, the processor executes devices, the processor executes I/O
memory read or write cycle. read or write cycle.
 M / is asserted high  M / is asserted low 148

8086 and 8088 comparison
8086
Microprocessor 8086 and 8088 comparison
8086 8088
Similar EU and Instruction set ; dissimilar BIU
16-bit Data bus lines obtained by 8-bit Data bus lines obtained by
demultiplexing AD0 – AD15 demultiplexing AD0 – AD7
20-bit address bus 8-bit address bus
Two banks of memory each of 512 Single memory bank

kb
6-bit instruction queue 4-bit instruction queue
Clock speeds: 5 / 8 / 10 MHz 5 / 8 MHz
In MIN mode, pin 28 is assigned the In MIN mode, pin 28 is assigned the
signal M / signal IO /
To access higher byte, signal is No such signal required, since the

used data width is only 1-byte
150
8087 Coprocessor
8086
Microprocessor Co-processor – Intel 8087
Multiprocessor A microprocessor system comprising of two or more

processors
system
Distributed processing: Entire task is divided in to
subtasks
Advantages Better system throughput by having more than one

processor
Each processor have a local bus to access local

memory or I/O devices so that a greater degree of
parallel processing can be achieved
System structure is more flexible.

One can easily add or remove modules to
change the system configuration without affecting
the other modules in the system
152
8086
8087 Specially designed to take care of mathematical

calculations involving integer and floating point data
coprocessor
“Math coprocessor” or “Numeric Data Processor
(NDP)”
Works in parallel with a 8086 in the maximum mode
Features 1) Can operate on data of the integer, decimal and real

types with lengths ranging from 2 to 10 bytes
2) Instruction set involves square root, exponential,

tangent etc. in addition to addition, subtraction,
multiplication and division.
3) High performance numeric data processor  it can

multiply two 64-bit real numbers in about 27s and
calculate square root in about 36 s
4) Follows IEEE floating point standard
5) It is multi bus compatible
153
8086
16 multiplexed address / data pins

and 4 multiplexed address / status
pins
Hence it can have 16-bit external

data bus and 20-bit external address
bus like 8086
Processor clock, ready and reset

signals are applied as clock, ready
and reset signals for coprocessor
154
8086
BUSY
BUSY signal from 8087 is connected

to the input of 8086
If the 8086 needs the result of some

computation that the 8087 is doing
before it can execute the next
instruction in the program, a user
can tell 8086 with a WAIT instruction
to keep looking at its pin until it
finds the pin low
A low on the BUSY output indicates

that the 8087 has completed the
computation
155
8086
The request / grant signal from the

8087 is usually connected to the
request / grant ( / or / ) pin of the
8086
The request / grant signal from the

8087 is usually connected to the
request / grant pin of the
independent processor such as 8089
156
8086
INT
The interrupt pin is connected to the

interrupt management logic.
The 8087 can interrupt the 8086

through this interrupt management
logic at the time error condition
exists
157
8086
-
Status
1 0 0 Unused
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
QS0 – QS1
QS0 QS1 Status

0 0 No operation
0 1 First byte of opcode
from queue
1 0 Queue empty
1 1 Subsequent byte of
opcode from queue
158
8086
8086 and 8087 reads 8087 keeps track for ESC

instruction bytes and instruction by monitoring
8087 puts them in the - and AD0 – AD15 of
instructions respective queues 8086.
are inserted
in the 8086 NOP Also keeps track of QS0 –
program QS1.
8087 instructions have
11011 as the MSB of
Q status 00; does
their first code byte
nothing
Q status 01; 8087

compares the five MSB
bits with 11011
If there is a match, then

the ESC instruction is
fetched and executed by
Memory read/ write 8087
Additional words : -
8087 BUSY pin high If there is error during
decoding an ESC
WAIT instruction, 8087 sends
an interrupt request
159
Ref: Microprocessor, Atul P. Godse, Deepali A. Gode, Technical publications, Chap 11
8086
8086/ 8088 Coprocessor
Wake up the
coprocessor
Monitor
ESC 8086/
8088
Deactivate the
Execute the host’s TEST pin
8086 and execute
instructions the specific
operation
Activate
WAIT the TEST
pin
Wake up the
8086/ 8088
160
161

MPMC-1

Uploaded by

Copyright:

Available Formats

MPMC-1

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MPMC-1

Uploaded by

Copyright:

Available Formats

Microprocessor Architecture

Dream: calculating with a machine

•The idea of calculating with a machine dates to 500 BC when the

• The first general –purpose programmable electronic computer system was

• Designed and developed at the U. of Pennsylvania, 1946

• It was programmed by setting up to 6000 switches and connecting cables

• first modern (general-purpose, programmable) electronic computer

• programmed by rewiring its circuits

• Before the invention of microprocessors, most digital design problems were

• Combinational circuits were derived from Boolean logic equations, truth

• Sequential designs utilized flip-flop excitation tables and state diagrams.

• Release of a new logic component called the microprocessor in the early

• Rather than implement a rigid set of logic equations, the microprocessor

• These instructions are called the control program. Release of a new

• A microcomputer system is built around the microprocessor.

The Intel Corporation introduced the first Microprocessor

The device that started the Microprocessor revolution that

• Later Intel released 4040, updated version of 4004,

Various conditions of the

Register array or Data Bus

Control Bus Address Bus

Generates control signals for

First 16- bit processor released by Addressable memory space is

Uses a separate 16 bit address for I/O

Operates in two modes: minimum

20-bit address to access memory  can

Von Neumann Architecture- Same memory space

Single memory for instructions Separate memory for instructions

CPU accesses instructions and CPU accesses instruction and data

Can become a bottleneck if too Improved performance because the

Easier to modify programs as More difficult to modify programs

Easy to share data between More difficult to share data between

Suitable for general-purpose Suitable for embedded systems

General purpose micro controllers,

S.No Microprocessors Microcontrollers

µp is a central processing unit µc has a CPU, in addition with RAM, ROM

3 Less no. of on-chip registers More no. of on-chip registers

• Intel 8085 is an 8 bit microprocessor

Reduced Instruction Set Architecture (RISC)

The main idea is that a single instruction will do all loading,

Low order address bus; these are

When AD lines are used to transmit

When data are transmitted over AD lines

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

This pin signal indicates what mode the

RD (Read) (Active Low)

The signal is used for read operation.

input is tested by the ‘WAIT’ instruction.

8086 will enter a wait state after

This is used to synchronize an external

This is the acknowledgement from the

The signal made available by the devices

The signal is active high. 36

Causes the processor to immediately

The signal must be active HIGH for at

The clock input provides the basic timing