default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Embedded Computing Systems, Volume 22
Volume 22, Number 1, January 2023
- Xuyi Cai
, Ying Wang, Lei Zhang:
Optimus: An Operator Fusion Framework for Deep Neural Networks. 1:1-1:26 - Deok-Jae Oh, Yaebin Moon, Do Kyu Ham, Tae Jun Ham, Yongjun Park, Jae W. Lee, Jung Ho Ahn, Eojin Lee:
MaPHeA: A Framework for Lightweight Memory Hierarchy-aware Profile-guided Heap Allocation. 2:1-2:28 - David Monniaux, Cyril Six:
Formally Verified Loop-Invariant Code Motion and Assorted Optimizations. 3:1-3:27 - Elliott Wen, Gerald Weber, Suranga Nanayakkara:
WasmAndroid: A Cross-Platform Runtime for Native Programming Languages on Android. 4:1-4:19 - Weiwei Chen, Ying Wang, Ying Xu, Chengsi Gao, Cheng Liu, Lei Zhang:
A Framework for Neural Network Architecture and Compile Co-optimization. 5:1-5:24 - May Young, Alan J. Hu, Guy G. F. Lemieux:
Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators. 6:1-6:25 - Gianluca Brilli, Roberto Cavicchioli, Marco Solieri, Paolo Valente, Andrea Marongiu:
Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs. 7:1-7:25 - Satyajit Das, Kevin J. M. Martin, Thomas Peyret, Philippe Coussy:
An Efficient and Flexible Stochastic CGRA Mapping Approach. 8:1-8:24 - Iman Saberi, Fathiyeh Faghih, Farzad Sobhi Bavil:
A Passive Online Technique for Learning Hybrid Automata from Input/Output Traces. 9:1-9:24 - Rachel Cleaveland, Stefan Mitsch, André Platzer:
Formally Verified Next-generation Airborne Collision Avoidance Games in ACAS X. 10:1-10:30 - Anindan Mondal, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen, Anupam Chattopadhyay:
Hardware Trojan Detection using Transition Probability with Minimal Test Vectors. 11:1-11:21 - Pascal Fradet, Alain Girault, Ruby Krishnaswamy, Xavier Nicollin, Arash Shafiei:
RDF: A Reconfigurable Dataflow Model of Computation. 12:1-12:30 - Alëna Rodionova, Lars Lindemann, Manfred Morari, George J. Pappas:
Temporal Robustness of Temporal Logic Specifications: Analysis and Control Design. 13:1-13:44 - Zirui Xu, Fuxun Yu, Chenchen Liu, Xiang Chen:
LanCeX: A Versatile and Lightweight Defense Method against Condensed Adversarial Attacks in Image and Audio Recognition. 14:1-14:24 - Wenbo Huang, Lei Zhang, Shuoyuan Wang, Hao Wu, Aiguo Song:
Deep Ensemble Learning for Human Activity Recognition Using Wearable Sensors via Filter Activation. 15:1-15:23 - Salah Hessien, Mohamed Hassan:
PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems. 16:1-16:27 - Po-Chen Yeh, Chin-Hsien Wu, Yung-Hsiang Lin, Ming-Yan Wu:
A Write-Related and Read-Related DRAM Allocation Strategy Inside Solid-State Drives (SSDs). 17:1-17:32 - Ali J. Ben Ali, Marziye Kouroshli, Sofiya Semenova, Zakieh Sadat Hashemifar, Steven Y. Ko, Karthik Dantu:
Edge-SLAM: Edge-Assisted Visual Simultaneous Localization and Mapping. 18:1-18:31 - Jaime Koh, Bruno Bodin:
K-Periodic Scheduling for Throughput-Buffering Trade-Off Exploration of CSDF. 19:1-19:28
Volume 22, Number 2, March 2023
- Rolf Ernst, Dominik Stöhrmann, Alex Bendrick, Adam Kostrzewa:
Application-centric Network Management - Addressing Safety and Real-time in V2X Applications. 20:1-20:25 - Roger Pujol, Josep Jorba, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Vector Extensions in COTS Processors to Increase Guaranteed Performance in Real-Time Systems. 21:1-21:26 - Mir Md Sajid Sarwar, Rajarshi Ray, Ansuman Banerjee:
A Contrastive Plan Explanation Framework for Hybrid System Models. 22:1-22:51 - Ferhat Erata, Eren Yildiz, Arda Goknil, Kasim Sinan Yildirim, Jakub Szefer, Ruzica Piskac, Gökçin Sezgin:
ETAP: Energy-aware Timing Analysis of Intermittent Programs. 23:1-23:31 - Maria Rafaela Gkeka, Alexandros Patras, Nikolaos Tavoularis, Stylianos Piperakis, Emmanouil Hourdakis, Panos E. Trahanias, Christos D. Antonopoulos, Spyros Lalis, Nikolaos Bellas:
Reconfigurable System-on-Chip Architectures for Robust Visual SLAM on Humanoid Robots. 24:1-24:29 - Xinyi Hu, Debiao He, Min Luo, Cong Peng, Qi Feng, Xinyi Huang:
High-Performance Implementation of the Identity-Based Signature Scheme in IEEE P1363 on GPU. 25:1-25:35 - Atanu Kundu, Sarthak Das, Rajarshi Ray:
SAT-Reach: A Bounded Model Checker for Affine Hybrid Systems. 26:1-26:36 - Ümit Y. Ogras, Radu Marculescu, Trevor N. Mudge, Michael Kishinevsky:
Introduction to the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques. 27:1-27:3 - Anish Krishnakumar, Ümit Y. Ogras, Radu Marculescu, Michael Kishinevsky, Trevor N. Mudge:
Domain-Specific Architectures: Research Problems and Promising Approaches. 28:1-28:26 - Yueting Li, Wang Kang, Kunyu Zhou, Keni Qiu, Weisheng Zhao:
Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies. 29:1-29:24 - Reza Yazdani Aminabadi, Olatunji Ruwase, Minjia Zhang, Yuxiong He, José-María Arnau, Antonio González:
SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks. 30:1-30:23 - Behzad Boroujerdian, Ying Jing, Devashree Tripathy, Amit Kumar, Lavanya Subramanian, Luke Yen, Vincent Lee, Vivek Venkatesan, Amit Jindal, Robert Shearer, Vijay Janapa Reddi:
FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity. 31:1-31:35 - Iulian Brumar, Georgios Zacharopoulos, Yuan Yao, Saketh Rama, David Brooks, Gu-Yeon Wei:
Early DSE and Automatic Generation of Coarse-grained Merged Accelerators. 32:1-32:29 - Ahmet Inci, Siri Garudanagiri Virupaksha, Aman Jain, Ting-Wu Chin, Venkata Vivek Thallam, Ruizhou Ding, Diana Marculescu:
QUIDAM: A Framework for Quantization-aware DNN Accelerator and Model Co-Exploration. 33:1-33:21 - Hamzeh Ahangari, Muhammet Mustafa Ozdal, Özcan Özturk:
HLS-based High-throughput and Work-efficient Synthesizable Graph Processing Template Pipeline. 34:1-34:24 - Kalhan Koul, Jackson Melchert, Kavya Sreedhar, Leonard Truong, Gedeon Nyengele, Keyi Zhang, Qiaoyi Liu, Jeff Setter, Po-Han Chen, Yuchen Mei, Maxwell Strange, Ross Daly, Caleb Donovick, Alex Carsello, Taeyoung Kong, Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar Setaluri, James Thomas, Nikhil Bhagdikar, David Durst, Zachary Myers, Nestan Tsiskaridze, Stephen Richardson, Rick Bahr, Kayvon Fatahalian, Pat Hanrahan, Clark W. Barrett, Mark Horowitz, Christopher Torng, Fredrik Kjolstad, Priyanka Raina:
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. 35:1-35:34 - Joshua Mack, Md Sahil Hassan, Nirmal Kumbhare, Miguel Castro-Gonzalez, Ali Akoglu:
CEDR: A Compiler-integrated, Extensible DSSoC Runtime. 36:1-36:34 - Huili Chen, Xinqiao Zhang, Ke Huang, Farinaz Koushanfar:
AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection. 37:1-37:23 - Jeff Anderson, Engin Kayraklioglu, Hamid Reza Imani, Chen Shen, Mario Miscuglio, Volker J. Sorger, Tarek A. El-Ghazawi:
Virtualizing a Post-Moore's Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator. 38:1-38:26 - N. S. Aswathy, Arnab Sarkar, Hemangee K. Kapoor:
A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems. 39:1-39:25
Volume 22, Number 3, May 2023
- Joseph Sifakis, David Harel:
Trustworthy Autonomous System Development. 40:1-40:24 - Aviral Shrivastava, Jian-Jia Chen, Akash Kumar, Anup Das:
ACM TECS Special Issue on Embedded System Security Tutorials. 41:1-41:2 - Huili Chen, Farinaz Koushanfar:
Tutorial: Toward Robust Deep Learning against Poisoning Attacks. 42:1-42:15 - Jakob Feldtkeller, Pascal Sasdrich, Tim Güneysu:
Challenges and Opportunities of Security-Aware EDA. 43:1-43:34 - Antti Rautakoura, Timo Hämäläinen:
Does SoC Hardware Development Become Agile by Saying So: A Literature Review and Mapping Study. 44:1-44:27 - Hammond Pearce, Ramesh Karri, Benjamin Tan:
High-Level Approaches to Hardware Security: A Tutorial. 45:1-45:40 - Kevin Immanuel Gubbi, Banafsheh Saber Latibari, Anirudh Srikanth, Tyler Sheaves, Sayed Arash Beheshti-Shirazi, Sai Manoj PD, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, Soheil Salehi:
Hardware Trojan Detection Using Machine Learning: A Tutorial. 46:1-46:26 - Tailin Liang, Lei Wang, Shaobo Shi, John Glossner, Xiaotong Zhang:
TCX: A RISC Style Tensor Computing Extension and a Programmable Tensor Processor. 47:1-47:27 - Yi Dong, Wei Huang, Vibhav Bharti, Victoria Cox, Alec Banks, Sen Wang, Xingyu Zhao, Sven Schewe, Xiaowei Huang:
Reliability Assessment and Safety Arguments for Machine Learning Components in System Assurance. 48:1-48:48 - Zujia Yan, Yi Zhuang, Weining Zheng, Jingjing Gu:
Multi-bit Data Flow Error Detection Method Based on SDC Vulnerability Analysis. 49:1-49:30 - Leonie Köhler, Phil Hertha, Matthias Beckert, Alex Bendrick, Rolf Ernst:
Robust Cause-Effect Chains with Bounded Execution Time and System-Level Logical Execution Time. 50:1-50:28 - Shikhar Tuli, Chia-Hao Li, Ritvik Sharma, Niraj K. Jha:
CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. 51:1-51:30 - Saehanseul Yi, Tae-Wook Kim, Jong-Chan Kim, Nikil D. Dutt:
EASYR: Energy-Efficient Adaptive System Reconfiguration for Dynamic Deadlines in Autonomous Driving on Multicore Processors. 52:1-52:29 - Georgios Zacharopoulos, Adel Ejjeh, Ying Jing, En-Yu Yang, Tianyu Jia, Iulian Brumar, Jeremy Intan, Muhammad Huzaifa, Sarita V. Adve, Vikram S. Adve, Gu-Yeon Wei, David Brooks:
Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration. 53:1-53:23 - Lars Lindemann, Lejun Jiang, Nikolai Matni, George J. Pappas:
Risk of Stochastic Systems for Temporal Logic Specifications. 54:1-54:31 - Jun Yin, Marian Verhelst:
CNN-based Robust Sound Source Localization with SRP-PHAT for the Extreme Edge. 55:1-55:27 - Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini:
DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors. 56:1-56:33 - Yirui Wu, Lilai Zhang, Zonghua Gu, Hu Lu, Shaohua Wan:
Edge-AI-Driven Framework with Efficient Mobile Network Design for Facial Expression Recognition. 57:1-57:17 - Berivan Isik, Kristy Choi, Xin Zheng, Tsachy Weissman, Stefano Ermon, H.-S. Philip Wong, Armin Alaghi:
Neural Network Compression for Noisy Storage Devices. 58:1-58:29 - Tomasz Kloda, Giovani Gracioli, Rohan Tabish, Reza Mirosanlou, Renato Mancuso, Rodolfo Pellizzoni, Marco Caccamo:
Lazy Load Scheduling for Mixed-criticality Applications in Heterogeneous MPSoCs. 59:1-59:26
Volume 22, Number 4, July 2023
- Pablo Parra, Antonio da Silva, Borja Losa, Ignacio García, Oscar R. Polo, Agustín Martínez-Hellín, Sebastián Sánchez:
Tailor-made Virtualization Monitor Design for CPU Virtualization on LEON Processors. 60:1-60:32 - Alexios Papaioannou, Charalampos S. Kouzinopoulos, Dimosthenis Ioannidis, Dimitrios Tzovaras:
An Ultra-low-power Embedded AI Fire Detection and Crowd Counting System for Indoor Areas. 61:1-61:20 - Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda:
XploreNAS: Explore Adversarially Robust and Hardware-efficient Neural Architectures for Non-ideal Xbars. 62:1-62:17 - Mario Günzel, Kuan-Hsun Chen, Niklas Ueter, Georg von der Brüggen, Marco Dürr, Jian-Jia Chen:
Compositional Timing Analysis of Asynchronized Distributed Cause-effect Chains. 63:1-63:34 - Rakin Muhammad Shadab, Yu Zou, Sanjay Gandham, Amro Awad, Mingjie Lin:
HMT: A Hardware-centric Hybrid Bonsai Merkle Tree Algorithm for High-performance Authentication. 64:1-64:28 - Donghyun Min, Kihyun Kim, Chaewon Moon, Awais Khan, Seungjin Lee, Changhwan Youn, Woosuk Chung, Youngjae Kim:
A Multi-tenant Key-value SSD with Secondary Index for Search Query Processing and Analysis. 65:1-65:27 - Lin Zhang, Zifan Wang, Fanxin Kong:
Optimal Checkpointing Strategy for Real-time Systems with Both Logical and Timing Correctness. 66:1-66:21 - Richard West, Ahmad Golchin, Anton Njavro:
Real-Time USB Networking and Device I/O. 67:1-67:38 - Maximilian A. Köhl, Holger Hermanns:
Model-Based Diagnosis of Real-Time Systems: Robustness Against Varying Latency, Clock Drift, and Out-of-Order Observations. 68:1-68:48 - Prerit Terway, Niraj K. Jha:
REPAIRS: Gaussian Mixture Model-based Completion and Optimization of Partially Specified Systems. 69:1-69:36 - Yao-Jen Hsu, Chin-Hsien Wu, Yu-Chieh Tsai, Chia-Cheng Liu:
A Granularity-Based Clustering Method for Reducing Write Amplification in Solid-State Drives. 70:1-70:32 - Mina Niknafs, Petru Eles, Zebo Peng:
Runtime Resource Management with Multiple-Step-Ahead Workload Prediction. 71:1-71:34
- Alberto Bosio, Lara Dolecek, Alexandra Kourfali, Sri Parameswaran, Alessandro Savino:
Special Issue: "Approximation at the Edge". 72:1-72:4 - Chetana Pradhan, Martín Letras, Jürgen Teich:
Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation. 73:1-73:24 - Sibendu Paul, Utsav Drolia, Y. Charlie Hu, Srimat Chakradhar:
AQuA: A New Image Quality Metric for Optimizing Video Analytics Systems. 74:1-74:29 - Luis G. León-Vega, Eduardo Salazar-Villalobos, Alejandro Rodriguez-Figueroa, Jorge Castro-Godínez:
Automatic Generation of Resource and Accuracy Configurable Processing Elements. 75:1-75:27 - Muhammad Awais, Ali Zahir, Syed Ayaz Ali Shah, Pedro Reviriego, Anees Ullah, Nasim Ullah, Adam Khan, Hazrat Ali:
Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs. 76:1-76:19 - Soumendu Kumar Ghosh, Arnab Raha, Vijay Raghunathan:
Energy-Efficient Approximate Edge Inference Systems. 77:1-77:50 - Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis:
A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators. 78:1-78:31
Volume 22, Number 5, September 2023
- David Metz, Vineet Kumar, Magnus Själander:
BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers. 79:1-79:22 - Hyeokdong Kwon, Hyunjun Kim, Minjoo Sim, Wai-Kong Lee, Hwajeong Seo:
Look-up the Rainbow: Table-based Implementation of Rainbow Signature on 64-bit ARMv8 Processors. 80:1-80:19 - Klaus Schneider, Anoop Bhagyanath:
Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann Architectures. 81:1-81:25 - Luca Caronti, Khakim Akhunov, Matteo Nardello, Kasim Sinan Yildirim, Davide Brunelli:
Fine-grained Hardware Acceleration for Efficient Batteryless Intermittent Inference on the Edge. 82:1-82:19 - Douwei Lei, Debiao He, Cong Peng, Min Luo, Zhe Liu, Xinyi Huang:
Faster Implementation of Ideal Lattice-Based Cryptography Using AVX512. 83:1-83:18 - Wei-Ju Chen, Peng Wu, Pei-Chi Huang, Aloysius K. Mok, Song Han:
Regular Composite Resource Partitioning and Reconfiguration in Open Systems. 84:1-84:29 - Saya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi:
Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis. 85:1-85:17 - Yuling Luo, Shiqi Zhang, Shunsheng Zhang, Junxiu Liu, Yanhu Wang, Su Yang:
A Secure and Efficient Framework for Outsourcing Large-scale Matrix Determinant and Linear Equations. 86:1-86:22 - Davide Li Calsi, Vittorio Zaccaria:
Interruptible Remote Attestation of Low-end IoT Microcontrollers via Performance Counters. 87:1-87:19 - Leandro Soares Indrusiak, Alan Burns:
Real-Time Guarantees in Routerless Networks-on-Chip. 88:1-88:27
Volume 22, Number 5s, October 2023
- Yunjie Pan, Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks. 98:1-98:24 - Zhao Yang, Qingshuang Sun:
Energy-efficient Personalized Federated Search with Graph for Edge Computing. 99:1-99:24 - Yitu Wang, Shiyu Li, Qilin Zheng, Andrew Chang, Hai Li, Yiran Chen:
EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference. 100:1-100:22 - Siva Satyendra Sahoo, Salim Ullah, Akash Kumar:
AxOTreeS: A Tree Search Approach to Synthesizing FPGA-based Approximate Operators. 101:1-101:26 - Salma Afifi, Febin Sunny, Amin Shafiee, Mahdi Nikdast, Sudeep Pasricha:
GHOST: A Graph Neural Network Accelerator using Silicon Photonics. 102:1-102:25 - Jiankang Ren, Chunxiao Liu, Chi Lin, Ran Bi, Simeng Li, Zheng Wang, Yicheng Qian, Zhichao Zhao, Guozhen Tan:
Protection Window Based Security-Aware Scheduling against Schedule-Based Attacks. 103:1-103:22 - Zhibing Sha, Jiaojiao Wu, Jun Li, Balazs Gerofi, Zhigang Cai, Jianwei Liao:
Proactive Stripe Reconstruction to Improve Cache Use Efficiency of SSD-Based RAID Systems. 104:1-104:18 - Hamid Mousavi, Mohammad Loni, Mina Alibeigi, Masoud Daneshtalab:
DASS: Differentiable Architecture Search for Sparse Neural Networks. 105:1-105:21 - Judicael Clair, Guy Eichler, Luca P. Carloni:
SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip. 106:1-106:22 - Artem Klashtorny, Zhuanhao Wu, Anirudh Mohan Kaushik, Hiren D. Patel:
Predictable GPU Wavefront Splitting for Safety-Critical Systems. 107:1-107:25 - Mohanad Odema, Halima Bouzidi, Hamza Ouarnoughi, Smaïl Niar, Mohammad Abdullah Al Faruque:
MaGNAS: A Mapping-Aware Graph Neural Architecture Search Framework for Heterogeneous MPSoC Deployment. 108:1-108:26 - Anupam Mondal, Shreya Gangopadhyay, Durba Chatterjee, Harishma Boyapally, Debdeep Mukhopadhyay:
PReFeR : Physically Related Function based Remote Attestation Protocol. 109:1-109:23 - Sosei Ikeda, Hiromitsu Awano, Takashi Sato:
Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility. 110:1-110:20 - Vishesh Mishra, Sparsh Mittal, Neelofar Hassan, Rekha Singhal, Urbi Chatterjee:
VADF: Versatile Approximate Data Formats for Energy-Efficient Computing. 111:1-111:21 - Dipal Halder, Maneesh Merugu, Sandip Ray:
ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks. 112:1-112:21 - Toygun Basaklar, A. Alper Goksoy, Anish Krishnakumar, Suat Gumussoy, Ümit Y. Ogras:
DTRL: Decision Tree-based Multi-Objective Reinforcement Learning for Runtime Task Scheduling in Domain-Specific System-on-Chips. 113:1-113:22 - Tzung-Han Juang, Christof Schlaak, Christophe Dubach:
Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs. 114:1-114:23 - Suyash Bakshi, Lennart Johnsson:
Computationally Efficient DNN Mapping Search Heuristic using Deep Reinforcement Learning. 115:1-115:21 - Dina Hussein, Ganapati Bhat:
CIM: A Novel Clustering-based Energy-Efficient Data Imputation Method for Human Activity Recognition. 116:1-116:26 - Akshara Ravi, Vivek Chaturvedi, Muhammad Shafique:
ViT4Mal: Lightweight Vision Transformer for Malware Detection on Edge Devices. 117:1-117:26 - Dipika Deb, John Jose:
ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs. 118:1-118:25
- Shin-Ting Wu, Liang-Chi Chen, Po-Chun Huang, Yuan-Hao Chang, Chien-Chung Ho, Wei-Kuan Shih:
WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories. 119:1-119:26 - Yixian Shen, Leo Schreuders, Anuj Pathania, Andy D. Pimentel:
Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation. 120:1-120:26 - Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza:
Overflow-free Compute Memories for Edge AI Acceleration. 121:1-121:23 - Kourosh Vali, Ata Vafi, Begum Kasap, Soheil Ghiasi:
BASS: Safe Deep Tissue Optical Sensing for Wearable Embedded Systems. 122:1-122:22 - Shuo Huai, Hao Kong, Xiangzhong Luo, Shiqing Li, Ravi Subramaniam, Christian Makaya, Qian Lin, Weichen Liu:
CRIMP: Compact & Reliable DNN Inference on In-Memory Processing via Crossbar-Aligned Compression and Non-ideality Adaptation. 123:1-123:25 - Chih-Hsuan Yen, Hashan Roshantha Mendis, Tei-Wei Kuo, Pi-Cheng Hsiu:
Keep in Balance: Runtime-reconfigurable Intermittent Deep Inference. 124:1-124:25 - Danish Gufran, Sudeep Pasricha:
FedHIL: Heterogeneity Resilient Federated Learning for Robust Indoor Localization with Mobile Devices. 125:1-125:24 - Chengpeng Xia, Yawen Chen, Haibo Zhang, Jigang Wu:
STADIA: Photonic Stochastic Gradient Descent for Neural Network Accelerators. 126:1-126:23 - Jung-Hsiu Chang, Tzu-Yu Chang, Yi-Chao Shih, Tseng-Yi Chen:
LaDy: Enabling Locality-aware Deduplication Technology on Shingled Magnetic Recording Drives. 127:1-127:25 - Yi-Han Lien, Yen-Ting Chen, Yuan-Hao Chang, Yu-Pei Liang, Wei-Kuan Shih:
FSIMR: File-system-aware Data Management for Interlaced Magnetic Recording. 128:1-128:18 - Wentong Li, Liang Shi, Hang Li, Changlong Li, Edwin Hsing-Mean Sha:
IOSR: Improving I/O Efficiency for Memory Swapping on Mobile Devices Via Scheduling and Reshaping. 129:1-129:23 - Garima Modi, Aritra Bagchi, Neetu Jindal, Ayan Mandal, Preeti Ranjan Panda:
CABARRE: Request Response Arbitration for Shared Cache Management. 130:1-130:24 - Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures. 131:1-131:25 - Harsh Sharma, Lukas Pfromm, Rasit Onur Topaloglu, Janardhan Rao Doppa, Ümit Y. Ogras, Ananth Kalyanaraman, Partha Pratim Pande:
Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference Tasks. 132:1-132:21 - Hassan Nassar, Lars Bauer, Jörg Henkel:
ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF. 133:1-133:23 - Giuseppe Sorrentino, Marco Venere, Davide Conficconi, Eleonora D'Arnese, Marco Domenico Santambrogio:
Hephaestus: Codesigning and Automating 3D Image Registration on Reconfigurable Architectures. 134:1-134:24 - Yigit Tuncel, Toygun Basaklar, Dina Carpenter-Graffy, Ümit Y. Ogras:
A Self-Sustained CPS Design for Reliable Wildfire Monitoring. 135:1-135:23
- Debasmita Lohar, Clothilde Jeangoudoux, Anastasia Volkova, Eva Darulova:
Sound Mixed Fixed-Point Quantization of Neural Networks. 136:1-136:26 - Timothy Bourke, Basile Pesin, Marc Pouzet:
Verified Compilation of Synchronous Dataflow with State Machines. 137:1-137:26 - Edward A. Lee, Ravi Akella, Soroush Bateni, Shaokai Lin, Marten Lohstroh, Christian Menard:
Consistency vs. Availability in Distributed Cyber-Physical Systems. 138:1-138:24 - Jonas Peeck, Rolf Ernst:
Improving Worst-case TSN Communication Times of Large Sensor Data Samples by Exploiting Synchronization. 139:1-139:25 - Yi-Quan Chou, Lin-Wei Shen, Li-Pin Chang:
Rectifying Skewed Kernel Page Reclamation in Mobile Devices for Improving User-Perceivable Latency. 140:1-140:22 - Rupak Majumdar, Mahmoud Salamati, Sadegh Soudjani:
Neural Abstraction-Based Controller Synthesis and Deployment. 141:1-141:25 - Osama Khan, Gwanjong Park, Euiseong Seo:
DaCapo: An On-Device Learning Scheme for Memory-Constrained Embedded Systems. 142:1-142:23 - Mario Günzel, Niklas Ueter, Kuan-Hsun Chen, Georg von der Brüggen, Jian-Jia Chen:
Probabilistic Reaction Time Analysis. 143:1-143:22 - Nils Vreman, Martina Maggio:
Stochastic Analysis of Control Systems Subject to Communication and Computation Faults. 144:1-144:25 - Yongchun Zheng, Changlong Li, Yi Xiong, Weihong Liu, Cheng Ji, Zongwei Zhu, Lichen Yu:
iAware: Interaction Aware Task Scheduling for Reducing Resource Contention in Mobile Systems. 145:1-145:24 - Hanrui Zhao, Niuniu Qi, Lydia Dehbi, Xia Zeng, Zhengfeng Yang:
Formal Synthesis of Neural Barrier Certificates for Continuous Systems via Counterexample Guided Learning. 146:1-146:21 - Andrew D. Loveless, Linh Thi Xuan Phan, Lisa Erickson, Ronald G. Dreslinski, Baris Kasikci:
CrossTalk: Making Low-Latency Fault Tolerance Cheap by Exploiting Redundant Networks. 147:1-147:25 - Junya Shijubo, Masaki Waga, Kohei Suenaga:
Probabilistic Black-Box Checking via Active MDP Learning. 148:1-148:26 - Nikhilesh Singh, Karthikeyan Renganathan, Chester Rebeiro, Jithin Jose, Ralph Mader:
Kryptonite: Worst-Case Program Interference Estimation on Multi-Core Embedded Systems. 149:1-149:23 - Sanjoy K. Baruah, Alan Burns, Robert Ian Davis:
Optimal Synthesis of Robust IDK Classifier Cascades. 150:1-150:26 - Lélio Brun, Christophe Garion, Pierre-Loïc Garoche, Xavier Thirioux:
Equation-Directed Axiomatization of Lustre Semantics to Enable Optimized Code Validation. 151:1-151:24 - Jean-Louis Colaço, Michael Mendler, Baptiste Pauget, Marc Pouzet:
A Constructive State-based Semantics and Interpreter for a Synchronous Data-flow Language with State Machines. 152:1-152:26 - Thilanka Thilakasiri, Matthias Becker:
Methods to Realize Preemption in Phased Execution Models. 153:1-153:25 - Matthew Szeto, Edward Andert, Aviral Shrivastava, Martin Reisslein, Chung-Wei Lin, Christ D. Richmond:
B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles. 154:1-154:23 - Shaokai Lin, Yatin A. Manerkar, Marten Lohstroh, Elizabeth Polgreen, Sheng-Jung Yu, Chadlia Jerad, Edward A. Lee, Sanjit A. Seshia:
Towards Building Verifiable CPS using Lingua Franca. 155:1-155:24 - Ezio Bartocci, Cristinel Mateis, Eleonora Nesterini, Dejan Nickovic:
Mining Hyperproperties using Temporal Logics. 156:1-156:26
Volume 22, Number 6, November 2023
- Yun Liang, Wei Zhang, Stephen Neuendorffer, Wayne Luk:
Special Issue: "AI Acceleration on FPGAs". 89:1-89:3 - Xianghong Hu, Hongmin Huang, Xueming Li, Xin Zheng, Qinyuan Ren, Jingyu He, Xiaoming Xiong:
High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System. 90:1-90:20 - Xiaoyang Wang, Zhe Zhou, Zhihang Yuan, Jingchen Zhu, Yulong Cao, Yao Zhang, Kangrui Sun, Guangyu Sun:
FD-CNN: A Frequency-Domain FPGA Acceleration Scheme for CNN-Based Image-Processing Applications. 91:1-91:30 - Zhengzheng Ma, Tuo Dai, Xuechao Wei, Guojie Luo:
An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA. 92:1-92:22 - Wenhua Ye, Xu Zhou, Joey Zhou, Cen Chen, Kenli Li:
Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array. 93:1-93:22 - Syed Asad Alam, David Gregg, Giulio Gambardella, Thomas B. Preußer, Michaela Blott:
On the RTL Implementation of FINN Matrix Vector Unit. 94:1-94:27 - Kaijie Feng, Xiaoya Fan, Jianfeng An, Chuxi Li, Kaiyue Di, Jiangfei Li:
ACDSE: A Design Space Exploration Method for CNN Accelerator based on Adaptive Compression Mechanism. 95:1-95:26 - Jiwu Shu, Kedong Fang, Youmin Chen, Shuo Wang:
TH-iSSD: Design and Implementation of a Generic and Reconfigurable Near-Data Processing Framework. 96:1-96:23
- Yu Fu, Jingqiang Lin, Dengguo Feng, Wei Wang, Mingyu Wang, Wenjie Wang:
RegKey: A Register-based Implementation of ECC Signature Algorithms Against One-shot Memory Disclosure. 97:1-97:22 - Chulhong Min, Akhil Mathur, Utku Günay Acer, Alessandro Montanari, Fahim Kawsar:
SensiX++: Bringing MLOps and Multi-tenant Model Serving to Sensory Edge Devices. 98:1-98:27 - Ahmed El Yaacoub, Luca Mottola, Thiemo Voigt, Philipp Rümmer:
Scheduling Dynamic Software Updates in Mobile Robots. 99:1-99:27 - Ankita Samaddar, Arvind Easwaran:
Online Distributed Schedule Randomization to Mitigate Timing Attacks in Industrial Control Systems. 100:1-100:39 - Jun-Shen Wu, Tsen-Wei Hsu, Ren-Shuo Liu:
SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs. 101:1-101:22 - Chen-Tui Hung, Kai-Xuan Lee, Yi-Zheng Liu, Ya-Shu Chen, Zhong-Han Chan:
Energy-Efficient Communications for Improving Timely Progress of Intermittent-Powered BLE Devices. 102:1-102:20 - Mohammad Haji Seyed Javadi, Mohsen Faryabi, Hamid Reza Mahdiani:
A Comprehensive Model for Efficient Design Space Exploration of Imprecise Computational Blocks. 103:1-103:20 - Lokesh Siddhu, Aritra Bagchi, Rajesh Kedia, Isaar Ahmad, Shailja Pandey, Preeti Ranjan Panda:
Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure. 104:1-104:27 - Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. 105:1-105:19 - Ebrahim Farahmand, Ali Mahani, Muhammad Abdullah Hanif, Muhammad Shafique:
Design and Analysis of High Performance Heterogeneous Block-based Approximate Adders. 106:1-106:32
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-26 00:36 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
