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ORCIDCharles C. Chiang
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2010 – 2019
- 2017
[j9]Fan Yang
, Subarna Sinha, Charles C. Chiang, Xuan Zeng, Dian Zhou:
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1545-1556 (2017)- [c39]Fan Yang, Charles C. Chiang, Xuan Zeng, Dian Zhou:
Efficient SVM-based hotspot detection using spectral clustering. ISCAS 2017: 1-4 - 2015
- [j8]Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang:
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 460-470 (2015) - 2014
- [j7]Wei Zhao, Hailong Yao, Yici Cai, Subarna Sinha, Charles C. Chiang:
Fast and scalable parallel layout decomposition in double patterning lithography. Integr. 47(2): 175-183 (2014) - [c38]Cristian Andrades, M. Andrea Rodríguez, Charles C. Chiang:
Signature indexing of design layouts for hotspot detection. DATE 2014: 1-6 - [c37]Yen-Ting Yu, Iris Hui-Ru Jiang, Yumin Zhang, Charles C. Chiang:
DRC-based hotspot detection considering edge tolerance and incomplete specification. ICCAD 2014: 101-107 - 2013
- [c36]Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang:
Machine-learning-based hotspot detection using topological classification and critical feature extraction. DAC 2013: 67:1-67:6 - 2012
- [c35]Yen-Ting Yu, Ya-Chung Chan, Subarna Sinha, Iris Hui-Ru Jiang, Charles C. Chiang:
Accurate process-hotspot detection using critical design rule extraction. DAC 2012: 1167-1172 - [c34]Jing Guo, Fan Yang, Subarna Sinha, Charles C. Chiang, Xuan Zeng:
Improved tangent space based distance metric for accurate lithographic hotspot classification. DAC 2012: 1173-1178 - 2011
- [c33]Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Charles C. Chiang, Tsung-Yi Ho:
A distributed algorithm for layout geometry operations. DAC 2011: 182-187
2000 – 2009
- 2009
- [c32]Charles C. Chiang, Subarna Sinha:
The road to 3D EDA tool readiness. ASP-DAC 2009: 429-436 - 2008
- [j6]Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong:
Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. 2(1): 2-15 (2008) - [c31]Qing Su, Charles C. Chiang, Jamil Kawa:
Hotspot Based Yield Prediction with Consideration of Correlations. ISQED 2008: 338-343 - 2007
- [b1]Charles C. Chiang, Jamil Kawa:
Design for Manufacturability and Yield for Nano-Scale CMOS. Series on Integrated Circuits and Systems, Springer 2007, ISBN 978-1-4020-5187-6, pp. 1-254 - [j5]Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 115-126 (2007) - [c30]Subarna Sinha, Jianfeng Luo, Charles C. Chiang:
Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process. ASP-DAC 2007: 1-6 - [c29]Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou, Charles C. Chiang:
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. ASP-DAC 2007: 474-479 - [c28]Jamil Kawa, Charles C. Chiang:
DFM issues for 65nm and beyond. ACM Great Lakes Symposium on VLSI 2007: 318-322 - [c27]Subarna Sinha, Charles C. Chiang:
A methodology for fast and accurate yield factor estimation during global routing. ICCAD 2007: 481-487 - [c26]Jingyu Xu, Subarna Sinha, Charles C. Chiang:
Accurate detection for process-hotspots with vias and incomplete specification. ICCAD 2007: 839-846 - [c25]Subarna Sinha, Qing Su, Linni Wen, Frank Lee, Charles C. Chiang, Yi-Kan Cheng, Jin-Lien Lin, Yu-Chyi Harn:
A New Flexible Algorithm for Random Yield Improvement. ISQED 2007: 795-800 - [i1]Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
Bright-Field AAPSM Conflict Detection and Correction. CoRR abs/0710.4661 (2007) - 2006
- [j4]Qing Su, Jamil Kawa, Charles C. Chiang, Yehia Massoud:
Accurate modeling of substrate resistive coupling for floating substrates. ACM Trans. Design Autom. Electr. Syst. 11(1): 44-51 (2006) - [c24]Charles C. Chiang, Jamil Kawa:
Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation. APCCAS 2006: 1099-1102 - [c23]Jamil Kawa, Charles C. Chiang, Raul Camposano:
EDA Challenges in Nano-scale Technology. CICC 2006: 845-851 - [c22]Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles C. Chiang:
An IC manufacturing yield model considering intra-die variations. DAC 2006: 749-754 - [c21]Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles C. Chiang:
Time domain model order reduction by wavelet collocation method. DATE 2006: 21-26 - [c20]Dan Page, Jamil Kawa, Charles C. Chiang:
DFM: swimming upstream. ACM Great Lakes Symposium on VLSI 2006: 1 - [c19]Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai:
Efficient process-hotspot detection using range pattern matching. ICCAD 2006: 625-632 - [c18]Jun Tao, Xuan Zeng, Fan Yang, Yangfeng Su, Lihong Feng, Wei Cai, Dian Zhou, Charles C. Chiang:
A one-shot projection method for interconnects with process variations. ISCAS 2006 - 2005
- [c17]Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles C. Chiang, Dian Zhou:
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. ASP-DAC 2005: 244-249 - [c16]Xuan Zeng, Bang Liu, Jun Tao, Charles C. Chiang, Dian Zhou:
A novel wavelet method for noise analysis of nonlinear circuits. ASP-DAC 2005: 471-476 - [c15]Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
Bright-Field AAPSM Conflict Detection and Correction. DATE 2005: 908-913 - [c14]Wen Yujie, Jiarong Tong, Charles C. Chiang:
Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only). FPGA 2005: 269 - [c13]Jianfeng Luo, Qing Su, Charles C. Chiang, Jamil Kawa:
A layout dependent full-chip copper electroplating topography model. ICCAD 2005: 133-140 - [c12]Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu:
Fast and efficient phase conflict detection and correction in standard-cell layouts. ICCAD 2005: 149-156 - [c11]Xin Wang, Charles C. Chiang, Jamil Kawa, Qing Su:
A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing. ISQED 2005: 258-263 - 2004
- [c10]Jian Wang, Jun Tao, Xuan Zeng, Charles C. Chiang, Dian Zhou:
Analog circuit behavioral modeling via wavelet collocation method with auto-companding. ASP-DAC 2004: 45-50 - [c9]Lihong Feng, Xuan Zeng, Charles C. Chiang, Dian Zhou, Qiang Fang:
Direct Nonlinear Order Reduction with Variational Analysis. DATE 2004: 1316-1321 - [c8]Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles C. Chiang:
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. DATE 2004: 1322-1326 - [c7]Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles C. Chiang, Dian Zhou:
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. ICCAD 2004: 74-79 - [c6]Bo-Kyung Choi, Charles C. Chiang, Jamil Kawa, Majid Sarrafzadeh:
Routing resources consumption on M-arch and X-arch. ISCAS (5) 2004: 73-76 - [c5]Jian Wang, Xuan Zeng, Wei Cai, Charles C. Chiang, Jiarong Tong, Dian Zhou:
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. ISCAS (5) 2004: 321-324 - [c4]Lihong Feng, Xuan Zeng, Jiarong Tong, Charles C. Chiang, Dian Zhou:
Two-sided projection method in variational equation model order reduction of nonlinear circuits. ISCAS (4) 2004: 816-819 - 2003
- [c3]Charles C. Chiang, Qing Su, Ching-Shoei Chiang:
Wirelength reduction by using diagonal wire. ACM Great Lakes Symposium on VLSI 2003: 104-107
1990 – 1999
- 1994
- [j3]Charles C. Chiang, Chak-Kuen Wong, Majid Sarrafzadeh:
A weighted Steiner tree-based global router with simultaneous length and density minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1461-1469 (1994) - 1991
- [j2]Charles C. Chiang, Majid Sarrafzadeh, C. K. Wong:
An optimal algorithm for rectilinear steiner trees for channels with obstacles. Int. J. Circuit Theory Appl. 19(6): 551-563 (1991) - [c2]Charles C. Chiang:
On wiring overlap layouts. Great Lakes Symposium on VLSI 1991: 25-30 - 1990
- [j1]Charles C. Chiang, Majid Sarrafzadeh, Chak-Kuen Wong:
Global routing based on Steiner min-max trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1318-1325 (1990)
1980 – 1989
- 1989
- [c1]Charles C. Chiang, Majid Sarrafzadeh, Chak-Kuen Wong:
A powerful global router: based on Steiner min-max trees. ICCAD 1989: 2-5
Coauthor Index
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