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2020 – today
- 2024
[j23]Quang-Manh Duong
, Khoa-Sang Nguyen, Hai-Duong Nguyen, Xuan-Uoc Dao, Anh-Tuan Do, Quang-Kien Trinh:
FeCBF: A Novel Sub-Optimal Cascaded Bloom Filter Structure Based on Feature Extraction. IEEE Access 12: 67619-67631 (2024)- [j22]Dongrui Li, Ming Ming Wong, Yi Sheng Chong, Jun Zhou, Mohit Upadhyay, Ananta Narayanan Balaji, Aarthy Mani, Weng-Fai Wong, Li-Shiuan Peh, Anh Tuan Do, Bo Wang:
1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2085-2092 (2024) - [c73]Zehao Li, Yuncheng Lu, Anh Tuan Do, Tony Tae-Hyoung Kim:
A 4.2pJ/Pixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-Path Aggregation Semi-Global Matching. CICC 2024: 1-2 - [c72]Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do:
PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications. HCS 2024: 1 - [c71]Byung-Kwon An, Xueyong Zhang, Anh Tuan Do, Tony Tae-Hyoung Kim:
Time-based Sensing with Linear Current-to-Time Conversion for Multi-level Resistive Memory. ISCAS 2024: 1-5 - [c70]Yi Sheng Chong, Hongyu Cao, Wang Ling Goh, Patrick Bore, Yuanzheng Paul Tan, Yung Szen Yap, Rainer Dumke, Vishnu P. Nambiar, Anh Tuan Do:
Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature. ISCAS 2024: 1-5 - [c69]Yi Sheng Chong, Rakshith Harish, Rajesh Chandrasekhara Panicker, Vishnu P. Nambiar, Anh Tuan Do:
A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation. ISCAS 2024: 1-5 - [c68]Nazim Altar Koca, Chip-Hong Chang, Anh Tuan Do, Vishnu P. Nambiar:
Exploring Error Correction Circuits on RISC-V based Systems for Space Applications. ISCAS 2024: 1-5 - [c67]Zhangyi Pei, Vishnu P. Nambiar, Yi Sheng Chong, Wang Ling Goh, Anh Tuan Do:
3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications. ISCAS 2024: 1-5 - 2023
- [j21]Tao Luo, Weng-Fai Wong, Rick Siow Mong Goh, Anh Tuan Do, Zhixian Chen, Haizhou Li, Wenyu Jiang, Weiyun Yau:
Achieving Green AI with Energy-Efficient Deep Learning Using Neuromorphic Computing. Commun. ACM 66(7): 52-57 (2023) - [j20]Lu Lu, Anh-Tuan Do:
A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3599-3603 (2023) - [c66]Qibang Zang, Wang Ling Goh, Yi Sheng Chong, Anh Tuan Do:
4b/4b/8b Precision Charge-Domain 8T-SRAM Based CiM for CNN Processing. AICAS 2023: 1-5 - [c65]Lu Lu, Aarthy Mani, Anh Tuan Do:
A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips. ISCAS 2023: 1-5 - [c64]Bo Wang, Ming Ming Wong, Dongrui Li, Yi Sheng Chong, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh, Aarthy Mani, Mohit Upadhyay, Ananta Narayanan Balaji, Anh Tuan Do:
1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing. ISCAS 2023: 1-5 - [c63]Seong-Beom Kim, Aarthy Mani, Leong Xu Heng Victor, Yuanjin Zheng, Anh Tuan Do:
Stability Analysis of 6T SRAM at Deep Cryogenic Temperature for Quantum Computing Applications. ISCAS 2023: 1-5 - [c62]Nazim Altar Koca, Anh Tuan Do, Chip-Hong Chang:
Hardware-efficient Softmax Approximation for Self-Attention Networks. ISCAS 2023: 1-5 - [c61]Aarthy Mani, Chong Yi Sheng, Di Zhu, Rasna Maruthiyodan Veetil, Moitra Parikshit, Tobias Wilhelm W. Mass, Chong Ser Choong, Xuewu Xu, Ramon José Paniagua Domínguez, Arseniy I. Kuznetsov, P. Krishna, P. Keyi, Kevin Tshun Chuan Chai, Anh Tuan Do:
1V, 1.13μm pixel pitch Liquid Crystal Driver with Charge-Balancing Scheme for SLM Applications. ISCAS 2023: 1-5 - [c60]Chen Shen, Junran Pu, Yi Sheng Chong, Zhongyi Zhang, Wang Ling Goh, Bin Zhao, Anh Tuan Do, Yuan Gao:
A 110nW Always-on Keyword Spotting Chip using Spiking CNN in 40nm CMOS. ISCAS 2023: 1-5 - [c59]Qibang Zang, Wang Ling Goh, Lu Lu, Chengshuo Yu, Junjie Mu, Tony Tae-Hyoung Kim, Bongjin Kim, Dongrui Li, Anh Tuan Do:
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. ISCAS 2023: 1-5 - [c58]Dongrui Li, Tomomasa Yamasaki, Aarthy Mani, Anh Tuan Do, Niangjun Chen, Bo Wang:
LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing. ISLPED 2023: 1-6 - [c57]Aarthy Mani, Leong Xu Heng Victor, Anh Tuan Do:
Cryogenic Characterization of 40nm CMOS for Quantum Control Applications. ISOCC 2023: 3-4 - [c56]Chan Kuen Sim, Aarthy Mani, Anh Tuan Do:
0.85 mW, 8-bit, 1GS/s, 58dB SFDR Cryogenic DAC for Superconducting Qubit Control Applications. ISOCC 2023: 93-94 - [c55]Byung-Kwon An, Xueyong Zhang, Anh Tuan Do, Tony Tae-Hyoung Kim:
Design of a Current Sense Amplifier with Dynamic Reference for Reliable Resistive Memory. NEWCAS 2023: 1-5 - 2022
- [j19]Liwei Yang, Huaipeng Zhang, Tao Luo, Chuping Qu, Myat Thu Linn Aung, Yingnan Cui, Jun Zhou, Ming Ming Wong, Junran Pu, Anh Tuan Do, Rick Siow Mong Goh, Weng-Fai Wong:
Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency. Neurocomputing 474: 128-140 (2022) - [j18]Liwei Yang, Huaipeng Zhang, Tao Luo, Chuping Qu, Myat Thu Linn Aung, Yingnan Cui, Jun Zhou, Ming Ming Wong, Junran Pu, Anh Tuan Do, Rick Siow Mong Goh, Weng-Fai Wong:
Corrigendum to "Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency" [Neurocomputing (2022) 128-140]. Neurocomputing 508: 109 (2022) - [j17]Yi Sheng Chong, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do:
A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1662-1666 (2022) - [c54]Jingjing Lan, Vishnu P. Nambiar, Ming Ming Wong, Fei Li, Yuan Gao, Kevin Tshun Chuan Chai, Anh Tuan Do:
A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS. ISCAS 2022: 2433-2437 - [c53]Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications. ISCAS 2022: 2680-2684 - [c52]Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training. ISCAS 2022: 2958-2962 - [c51]Qibang Zang, Wang Ling Goh, Fei Li, Lu Lu, Anh Tuan Do:
Temperature Compensation on SRAM-Based Computation in Memory Array. ISOCC 2022: 1-2 - [c50]Yingfeng Wang, Yi Sheng Chong, Wang Ling Goh, Anh Tuan Do:
Noise-Aware and Lightweight LSTM for Keyword Spotting Applications. ISOCC 2022: 135-136 - [c49]Z. Di, Aarthy Mani, Anh Tuan Do, A. Baranikov, R. M. Veetil, R. P. Domínguez, Arseniy I. Kuznetsov, Kevin T. C. Chai:
Linearity Characterization of Hybrid Driving Scheme for Spatial Light Modulator System. ISOCC 2022: 312-313 - 2021
- [j16]Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Ming Ming Wong, Anh Tuan Do:
A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 5081-5094 (2021) - [j15]Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do:
A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 471-475 (2021) - [j14]Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Yi Sheng Chong, Anh Tuan Do:
A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1398-1402 (2021) - [j13]Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do:
Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3148-3152 (2021) - [c48]Xuyang Huang, Ming Ming Wong, Anh Tuan Do, Wang Ling Goh:
A Backpropagation Extreme Learning Machine Approach to Fast Training Neural Network-Based Side-Channel Attack. AsianHOST 2021: 1-6 - [c47]Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do:
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSCIRC 2021: 95-98 - [c46]Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do:
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSDERC 2021: 95-98 - [c45]Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks. ISCAS 2021: 1-5 - [c44]Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
Efficient Implementation of Activation Functions for LSTM accelerators. VLSI-SoC 2021: 1-5 - [c43]Ming Ming Wong, Lu Chen, Anh Tuan Do:
A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design. VLSI-SoC 2021: 1-6 - [c42]Ming Ming Wong, Lu Chen, Anh Tuan Do:
An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design. VLSI-SoC (Selected Papers) 2021: 245-266 - 2020
- [j12]Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim:
Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2154-2158 (2020) - [c41]Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Tao Luo, L. Yang, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do:
0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. A-SSCC 2020: 1-4 - [c40]Zhehui Wang, Huaipeng Zhang, Tao Luo, Weng-Fai Wong, Anh-Tuan Do, Paramasivam Vishnu, Wei Zhang, Rick Siow Mong Goh:
NCPower: Power Modelling for NVM-based Neuromorphic Chip. ICONS 2020: 15:1-15:7 - [c39]Bin Zhao, Yi Sheng Chong, Anh-Tuan Do:
Area and Energy Efficient 2D Max-Pooling For Convolutional Neural Network Hardware Accelerator. IECON 2020: 423-427 - [c38]Anh Tuan Do, Xuanyao Fong, Fei Li:
Aggressive Leakage Current Reduction for Embedded MRAM Using Block-Level Power Gating. IECON 2020: 2249-2254 - [c37]Yun Kwan Lee, Vishnu P. Nambiar, Kim Seng Goh, Anh Tuan Do:
Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware. IECON 2020: 3836-3840 - [c36]Anh Tuan Do, Tony Tae-Hyoung Kim, Xin Liu, Jun Zhou:
Design and Characterization of Radiation-Hardened MCU for Space Application using Error Correction SRAM and Glitch Removal Clock Buffer Cell. ISCAS 2020: 1-4 - [c35]Aarthy Mani, Fei Li, Ming Ming Wong, Luo Tao, Liwei Yang, Vishnu Paramasivam, Anh Tuan Do:
Ultra-Low Leakage, High Fan-Out Neuro Connection Map with TCAM-Based LUT, Localized Priority Encoder and Decoder-Less SRAM. ISCAS 2020: 1-4 - [c34]Vishnu P. Nambiar, Eng-Kiat Koh, Junran Pu, Aarthy Mani, Ming Ming Wong, Li Fei, Wang Ling Goh, Anh Tuan Do:
Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j11]Kian Ann Ng, Chao Yuan, Astrid Rusly, Anh-Tuan Do, Bin Zhao, Shih-Chiang Liu, Wendy Yen Xian Peh, Thow Xin Yuan, Kai Voges, Sanghoon Lee, Gil Gerald Lasam Gammad, Khay-Wai Leong, John S. Ho, Silvia Bossi, Gemma Taverni, Annarita Cutrone, Shih-Cheng Yen, Yong Ping Xu:
A Wireless Multi-Channel Peripheral Nerve Signal Acquisition System-on-Chip. IEEE J. Solid State Circuits 54(8): 2266-2280 (2019) - [j10]Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim:
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 126-137 (2019) - [c33]Fei Li, Ming Ming Wong, Aarthy Mani, Vishnu Paramasivam, Anh-Tuan Do:
0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications. A-SSCC 2019: 141-144 - [c32]Junran Pu, Vishnu P. Nambiar, Anh-Tuan Do, Wang Ling Goh:
Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm. ISCAS 2019: 1-5 - [c31]Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do:
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing. SoCC 2019: 27-32 - [c30]Ming Ming Wong, Anh-Tuan Do:
Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function. SoCC 2019: 103-108 - [c29]Yun Kwan Lee, Vishnu P. Nambiar, Junran Pu, Wang Ling Goh, Anh-Tuan Do:
Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers. SoCC 2019: 242-247 - [c28]Anh-Tuan Do:
0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique. SoCC 2019: 312-317 - 2017
- [c27]Anh-Tuan Do, Xin Liu:
25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme. A-SSCC 2017: 61-64 - 2016
- [j9]Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Xin Liu, Tony Tae-Hyoung Kim:
0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization. IEEE J. Solid State Circuits 51(6): 1487-1498 (2016) - [c26]Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim:
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS. APCCAS 2016: 734-735 - [c25]Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim:
A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications. A-SSCC 2016: 173-176 - [c24]Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim:
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j8]Bo Wang, Truc Quynh Nguyen, Anh-Tuan Do, Jun Zhou, Minkyu Je, Tony Tae-Hyoung Kim:
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 441-448 (2015) - [c23]Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. ISCAS 2015: 794-797 - [c22]Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation. ISCAS 2015: 2553-2556 - 2014
- [j7]Anh-Tuan Do, Chun Yin, Kavitha Velayudhan, Zhao Chuan Lee, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance. IEEE J. Solid State Circuits 49(7): 1487-1498 (2014) - [c21]Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Tony Tae-Hyoung Kim:
0.2 V 8T SRAM with improved bitline sensing using column-based data randomization. A-SSCC 2014: 141-144 - [c20]Anh-Tuan Do, Kiat Seng Yeo:
A hybrid NEO-based spike detection algorithm for implantable brain-IC interface applications. ISCAS 2014: 2393-2396 - [c19]Kiat Seng Yeo, Mojy Curtis Chian, Tony Chon Wee Ng, Anh-Tuan Do:
Internet of Things: Trends, challenges and applications. ISIC 2014: 568-571 - 2013
- [j6]Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 151-156 (2013) - [c18]Anh Tuan Do, Chun Yin, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Design of a power-efficient CAM using automated background checking scheme for small match line swing. ESSCIRC 2013: 209-212 - [c17]Anh-Tuan Do, Karthik G. Jayaraman, Pushpapraj Singh, Chua Geng Li, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset. ESSDERC 2013: 284-287 - [c16]Anh-Tuan Do, Yung Sern Tan, Gordon M. Xiong, Cleo Choong, Zhi-Hui Kong, Kiat Seng Yeo:
A current-mode stimulator circuit with two-step charge balancing background calibration. ISCAS 2013: 409-412 - [c15]Anh-Tuan Do, Karthik G. Jayaraman, Vincent Pott, Chua Geng Li, Pushpapraj Singh, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
An improved read/write scheme for anchorless NEMS-CMOS non-volatile memory. ISCAS 2013: 1456-1459 - 2012
- [j5]Anh-Tuan Do, Truc Quynh Nguyen, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 868-872 (2012) - [c14]Vikas Chandan, Anh-Tuan Do, Baoduo Jin, Faryar Jabbari, Jack Brouwer, Ioannis Akrotirianakis, Amit Chakraborty, Andrew G. Alleyne:
Modeling and optimization of a combined cooling, heating and power plant system. ACC 2012: 3069-3074 - [c13]Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Lei Yao, Meng Tong Tan, Minkyu Je:
A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems. APCCAS 2012: 1-4 - [c12]Tony T. Kim, Bo Wang, Anh-Tuan Do:
High energy efficient ultra-low voltage SRAM design: Device, circuit, and architecture. ISOCC 2012: 367-370 - [c11]Haitao Wang, Kiat Seng Yeo, Anh-Tuan Do, Yung Sern Tan, Kai Kang, Zhenghao Lu:
A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor. ISOCC 2012: 383-386 - [c10]Anh-Tuan Do, Yung Sern Tan, Chun Kit Lam, Minkyu Je, Kiat Seng Yeo:
Low power implantable neural recording front-end. ISOCC 2012: 387-390 - [c9]Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Xiaodan Zou, Lei Yao, Kuang-Wei Cheng, Minkyu Je:
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. NEWCAS 2012: 525-528 - 2011
- [j4]Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat Seng Yeo:
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1252-1263 (2011) - [j3]Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low:
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 196-204 (2011) - [c8]Xiaoliang Tan, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo, Zhi-Hui Kong:
A new match line sensing technique in Content Addressable Memory. COOL Chips 2011: 1-3 - [c7]Anh-Tuan Do, Xiaoliang Tan, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs. ACM Great Lakes Symposium on VLSI 2011: 371-374 - [c6]Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
A low-power CAM with efficient power and delay trade-off. ISCAS 2011: 2573-2576 - [c5]Myat Thu Linn Aung, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo:
Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor. VLSI-SoC 2011: 66-71 - 2010
- [j2]Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo:
Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 83-92 (2010) - [c4]Anh-Tuan Do, Kiat Seng Yeo, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong:
An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. APCCAS 2010: 704-707 - [c3]Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
Low IR drop and low power parallel CAM design using gated power transistor technique. APCCAS 2010: 708-711 - [c2]Zhi-Hui Kong, Anh-Tuan Do:
A 16Kb 10T-SRAM with 4x read-power reduction. ISCAS 2010: 3485-3488
2000 – 2009
- 2008
- [j1]Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo:
Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 986-990 (2008) - [c1]Anh-Tuan Do, Jeremy Yung Shern Low, Zhi-Hui Kong, Kiat Seng Yeo, Joshua Yung Low Yung Lih:
A full current-mode sense amplifier for low-power SRAM applications. APCCAS 2008: 1402-1405
Coauthor Index
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